summaryrefslogtreecommitdiff
path: root/arch/powerpc/boot/dts/mpc5200b.dtsi
blob: 648fe31795f494093df0fe570b4ea0215351c3a1 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * base MPC5200b Device Tree Source
 *
 * Copyright (C) 2010 SecretLab
 * Grant Likely <grant@secretlab.ca>
 * John Bonesio <bones@secretlab.ca>
 */

/dts-v1/;

/ {
	model = "fsl,mpc5200b";
	compatible = "fsl,mpc5200b";
	#address-cells = <1>;
	#size-cells = <1>;
	interrupt-parent = <&mpc5200_pic>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		powerpc: PowerPC,5200@0 {
			device_type = "cpu";
			reg = <0>;
			d-cache-line-size = <32>;
			i-cache-line-size = <32>;
			d-cache-size = <0x4000>;	// L1, 16K
			i-cache-size = <0x4000>;	// L1, 16K
			timebase-frequency = <0>;	// from bootloader
			bus-frequency = <0>;		// from bootloader
			clock-frequency = <0>;		// from bootloader
		};
	};

	memory: memory {
		device_type = "memory";
		reg = <0x00000000 0x04000000>;	// 64MB
	};

	soc: soc5200@f0000000 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "fsl,mpc5200b-immr";
		ranges = <0 0xf0000000 0x0000c000>;
		reg = <0xf0000000 0x00000100>;
		bus-frequency = <0>;		// from bootloader
		system-frequency = <0>;		// from bootloader

		cdm@200 {
			compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
			reg = <0x200 0x38>;
		};

		mpc5200_pic: interrupt-controller@500 {
			// 5200 interrupts are encoded into two levels;
			interrupt-controller;
			#interrupt-cells = <3>;
			compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
			reg = <0x500 0x80>;
		};

		gpt0: timer@600 {	// General Purpose Timer
			compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
			#gpio-cells = <2>;  // Add 'gpio-controller;' to enable gpio mode
			reg = <0x600 0x10>;
			interrupts = <1 9 0>;
			// add 'fsl,has-wdt' to enable watchdog
		};

		gpt1: timer@610 {	// General Purpose Timer
			compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
			#gpio-cells = <2>;  // Add 'gpio-controller;' to enable gpio mode
			reg = <0x610 0x10>;
			interrupts = <1 10 0>;
		};

		gpt2: timer@620 {	// General Purpose Timer
			compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
			#gpio-cells = <2>;  // Add 'gpio-controller;' to enable gpio mode
			reg = <0x620 0x10>;
			interrupts = <1 11 0>;
		};

		gpt3: timer@630 {	// General Purpose Timer
			compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
			#gpio-cells = <2>;  // Add 'gpio-controller;' to enable gpio mode
			reg = <0x630 0x10>;
			interrupts = <1 12 0>;
		};

		gpt4: timer@640 {	// General Purpose Timer
			compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
			#gpio-cells = <2>;  // Add 'gpio-controller;' to enable gpio mode
			reg = <0x640 0x10>;
			interrupts = <1 13 0>;
		};

		gpt5: timer@650 {	// General Purpose Timer
			compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
			#gpio-cells = <2>;  // Add 'gpio-controller;' to enable gpio mode
			reg = <0x650 0x10>;
			interrupts = <1 14 0>;
		};

		gpt6: timer@660 {	// General Purpose Timer
			compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
			#gpio-cells = <2>;  // Add 'gpio-controller;' to enable gpio mode
			reg = <0x660 0x10>;
			interrupts = <1 15 0>;
		};

		gpt7: timer@670 {	// General Purpose Timer
			compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
			#gpio-cells = <2>;  // Add 'gpio-controller;' to enable gpio mode
			reg = <0x670 0x10>;
			interrupts = <1 16 0>;
		};

		rtc@800 {	// Real time clock
			compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
			reg = <0x800 0x100>;
			interrupts = <1 5 0 1 6 0>;
		};

		can@900 {
			compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
			interrupts = <2 17 0>;
			reg = <0x900 0x80>;
		};

		can@980 {
			compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
			interrupts = <2 18 0>;
			reg = <0x980 0x80>;
		};

		gpio_simple: gpio@b00 {
			compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
			reg = <0xb00 0x40>;
			interrupts = <1 7 0>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		gpio_wkup: gpio@c00 {
			compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
			reg = <0xc00 0x40>;
			interrupts = <1 8 0 0 3 0>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		spi@f00 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
			reg = <0xf00 0x20>;
			interrupts = <2 13 0 2 14 0>;
		};

		usb: usb@1000 {
			compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
			reg = <0x1000 0xff>;
			interrupts = <2 6 0>;
		};

		dma-controller@1200 {
			compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
			reg = <0x1200 0x80>;
			interrupts = <3 0 0  3 1 0  3 2 0  3 3 0
			              3 4 0  3 5 0  3 6 0  3 7 0
			              3 8 0  3 9 0  3 10 0  3 11 0
			              3 12 0  3 13 0  3 14 0  3 15 0>;
		};

		xlb@1f00 {
			compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
			reg = <0x1f00 0x100>;
		};

		psc1: psc@2000 {		// PSC1
			compatible = "fsl,mpc5200b-psc","fsl,mpc5200-psc";
			reg = <0x2000 0x100>;
			interrupts = <2 1 0>;
		};

		psc2: psc@2200 {		// PSC2
			compatible = "fsl,mpc5200b-psc","fsl,mpc5200-psc";
			reg = <0x2200 0x100>;
			interrupts = <2 2 0>;
		};

		psc3: psc@2400 {		// PSC3
			compatible = "fsl,mpc5200b-psc","fsl,mpc5200-psc";
			reg = <0x2400 0x100>;
			interrupts = <2 3 0>;
		};

		psc4: psc@2600 {		// PSC4
			compatible = "fsl,mpc5200b-psc","fsl,mpc5200-psc";
			reg = <0x2600 0x100>;
			interrupts = <2 11 0>;
		};

		psc5: psc@2800 {		// PSC5
			compatible = "fsl,mpc5200b-psc","fsl,mpc5200-psc";
			reg = <0x2800 0x100>;
			interrupts = <2 12 0>;
		};

		psc6: psc@2c00 {		// PSC6
			compatible = "fsl,mpc5200b-psc","fsl,mpc5200-psc";
			reg = <0x2c00 0x100>;
			interrupts = <2 4 0>;
		};

		eth0: ethernet@3000 {
			compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
			reg = <0x3000 0x400>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <2 5 0>;
		};

		mdio@3000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
			reg = <0x3000 0x400>;	// fec range, since we need to setup fec interrupts
			interrupts = <2 5 0>;	// these are for "mii command finished", not link changes & co.
		};

		ata@3a00 {
			compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
			reg = <0x3a00 0x100>;
			interrupts = <2 7 0>;
		};

		sclpc@3c00 {
			compatible = "fsl,mpc5200-lpbfifo";
			reg = <0x3c00 0x60>;
			interrupts = <2 23 0>;
		};

		i2c@3d00 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
			reg = <0x3d00 0x40>;
			interrupts = <2 15 0>;
		};

		i2c@3d40 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
			reg = <0x3d40 0x40>;
			interrupts = <2 16 0>;
		};

		sram@8000 {
			compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
			reg = <0x8000 0x4000>;
		};
	};

	pci: pci@f0000d00 {
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		device_type = "pci";
		compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci";
		reg = <0xf0000d00 0x100>;
		// interrupt-map-mask = need to add
		// interrupt-map = need to add
		clock-frequency = <0>; // From boot loader
		interrupts = <2 8 0 2 9 0 2 10 0>;
		bus-range = <0 0>;
		// ranges = need to add
	};

	localbus: localbus {
		compatible = "fsl,mpc5200b-lpb","fsl,mpc5200-lpb","simple-bus";
		#address-cells = <2>;
		#size-cells = <1>;
		ranges = <0 0 0xfc000000 0x2000000>;
	};
};