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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/* Copyright (c) 2020-2021 Microchip Technology Inc */
/dts-v1/;
#include "microchip-mpfs.dtsi"
/* Clock frequency (in Hz) of the rtcclk */
#define RTCCLK_FREQ 1000000
/ {
model = "Microchip PolarFire-SoC Icicle Kit";
compatible = "microchip,mpfs-icicle-kit", "microchip,mpfs";
aliases {
ethernet0 = &mac1;
serial0 = &mmuart0;
serial1 = &mmuart1;
serial2 = &mmuart2;
serial3 = &mmuart3;
};
chosen {
stdout-path = "serial0:115200n8";
};
cpus {
timebase-frequency = <RTCCLK_FREQ>;
};
memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x40000000>;
clocks = <&clkcfg CLK_DDRC>;
};
};
&refclk {
clock-frequency = <600000000>;
};
&mmuart0 {
status = "okay";
};
&mmuart1 {
status = "okay";
};
&mmuart2 {
status = "okay";
};
&mmuart3 {
status = "okay";
};
&mmc {
status = "okay";
bus-width = <4>;
disable-wp;
cap-sd-highspeed;
cap-mmc-highspeed;
card-detect-delay = <200>;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr50;
sd-uhs-sdr104;
};
&i2c2 {
status = "okay";
};
&mac0 {
phy-mode = "sgmii";
phy-handle = <&phy0>;
};
&mac1 {
status = "okay";
phy-mode = "sgmii";
phy-handle = <&phy1>;
phy1: ethernet-phy@9 {
reg = <9>;
ti,fifo-depth = <0x1>;
};
phy0: ethernet-phy@8 {
reg = <8>;
ti,fifo-depth = <0x1>;
};
};
&core_pwm0 {
status = "okay";
};
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