1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
|
/*
* Copyright 2022 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include "priv.h"
#include <subdev/mc.h>
#include <subdev/timer.h>
static bool
ga102_flcn_dma_done(struct nvkm_falcon *falcon)
{
return !!(nvkm_falcon_rd32(falcon, 0x118) & 0x00000002);
}
static void
ga102_flcn_dma_xfer(struct nvkm_falcon *falcon, u32 mem_base, u32 dma_base, u32 cmd)
{
nvkm_falcon_wr32(falcon, 0x114, mem_base);
nvkm_falcon_wr32(falcon, 0x11c, dma_base);
nvkm_falcon_wr32(falcon, 0x118, cmd);
}
static int
ga102_flcn_dma_init(struct nvkm_falcon *falcon, u64 dma_addr, int xfer_len,
enum nvkm_falcon_mem mem_type, bool sec, u32 *cmd)
{
*cmd = (ilog2(xfer_len) - 2) << 8;
if (mem_type == IMEM)
*cmd |= 0x00000010;
if (sec)
*cmd |= 0x00000004;
nvkm_falcon_wr32(falcon, 0x110, dma_addr >> 8);
nvkm_falcon_wr32(falcon, 0x128, 0x00000000);
return 0;
}
const struct nvkm_falcon_func_dma
ga102_flcn_dma = {
.init = ga102_flcn_dma_init,
.xfer = ga102_flcn_dma_xfer,
.done = ga102_flcn_dma_done,
};
int
ga102_flcn_reset_wait_mem_scrubbing(struct nvkm_falcon *falcon)
{
nvkm_falcon_mask(falcon, 0x040, 0x00000000, 0x00000000);
if (nvkm_msec(falcon->owner->device, 20,
if (!(nvkm_falcon_rd32(falcon, 0x0f4) & 0x00001000))
break;
) < 0)
return -ETIMEDOUT;
return 0;
}
int
ga102_flcn_reset_prep(struct nvkm_falcon *falcon)
{
nvkm_falcon_rd32(falcon, 0x0f4);
nvkm_usec(falcon->owner->device, 150,
if (nvkm_falcon_rd32(falcon, 0x0f4) & 0x80000000)
break;
_warn = false;
);
return 0;
}
int
ga102_flcn_select(struct nvkm_falcon *falcon)
{
if ((nvkm_falcon_rd32(falcon, falcon->addr2 + 0x668) & 0x00000010) != 0x00000000) {
nvkm_falcon_wr32(falcon, falcon->addr2 + 0x668, 0x00000000);
if (nvkm_msec(falcon->owner->device, 10,
if (nvkm_falcon_rd32(falcon, falcon->addr2 + 0x668) & 0x00000001)
break;
) < 0)
return -ETIMEDOUT;
}
return 0;
}
int
ga102_flcn_fw_boot(struct nvkm_falcon_fw *fw, u32 *mbox0, u32 *mbox1, u32 mbox0_ok, u32 irqsclr)
{
struct nvkm_falcon *falcon = fw->falcon;
nvkm_falcon_wr32(falcon, falcon->addr2 + 0x210, fw->dmem_sign);
nvkm_falcon_wr32(falcon, falcon->addr2 + 0x19c, fw->engine_id);
nvkm_falcon_wr32(falcon, falcon->addr2 + 0x198, fw->ucode_id);
nvkm_falcon_wr32(falcon, falcon->addr2 + 0x180, 0x00000001);
return gm200_flcn_fw_boot(fw, mbox0, mbox1, mbox0_ok, irqsclr);
}
int
ga102_flcn_fw_load(struct nvkm_falcon_fw *fw)
{
struct nvkm_falcon *falcon = fw->falcon;
int ret = 0;
nvkm_falcon_mask(falcon, 0x624, 0x00000080, 0x00000080);
nvkm_falcon_wr32(falcon, 0x10c, 0x00000000);
nvkm_falcon_mask(falcon, 0x600, 0x00010007, (0 << 16) | (1 << 2) | 1);
ret = nvkm_falcon_dma_wr(falcon, fw->fw.img, fw->fw.phys, fw->imem_base_img,
IMEM, fw->imem_base, fw->imem_size, true);
if (ret)
return ret;
ret = nvkm_falcon_dma_wr(falcon, fw->fw.img, fw->fw.phys, fw->dmem_base_img,
DMEM, fw->dmem_base, fw->dmem_size, false);
if (ret)
return ret;
return 0;
}
const struct nvkm_falcon_fw_func
ga102_flcn_fw = {
.signature = ga100_flcn_fw_signature,
.reset = gm200_flcn_fw_reset,
.load = ga102_flcn_fw_load,
.boot = ga102_flcn_fw_boot,
};
|
