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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2022 Microchip UNG
*/
#include <dt-bindings/clock/microchip,lan966x.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/mfd/atmel-flexcom.h>
#include <dt-bindings/phy/phy-lan966x-serdes.h>
/dts-v1/;
/plugin/;
/ {
fragment@0 {
target-path = "";
/*
* These properties allow to avoid a dtc warnings.
* The real interrupt controller is the PCI device itself. It
* is the node on which the device tree overlay will be applied.
* This node has those properties.
*/
#interrupt-cells = <1>;
interrupt-controller;
__overlay__ {
#address-cells = <3>;
#size-cells = <2>;
cpu_clk: clock-600000000 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <600000000>; /* CPU clock = 600MHz */
};
ddr_clk: clock-30000000 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <30000000>; /* Fabric clock = 30MHz */
};
sys_clk: clock-15625000 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <15625000>; /* System clock = 15.625MHz */
};
pci-ep-bus@0 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
/*
* map @0xe2000000 (32MB) to BAR0 (CPU)
* map @0xe0000000 (16MB) to BAR1 (AMBA)
*/
ranges = <0xe2000000 0x00 0x00 0x00 0x2000000
0xe0000000 0x01 0x00 0x00 0x1000000>;
oic: oic@e00c0120 {
compatible = "microchip,lan966x-oic";
#interrupt-cells = <2>;
interrupt-controller;
interrupts = <0>; /* PCI INTx assigned interrupt */
reg = <0xe00c0120 0x190>;
};
cpu_ctrl: syscon@e00c0000 {
compatible = "microchip,lan966x-cpu-syscon", "syscon";
reg = <0xe00c0000 0xa8>;
};
reset: reset@e200400c {
compatible = "microchip,lan966x-switch-reset";
reg = <0xe200400c 0x4>, <0xe00c0000 0xa8>;
reg-names = "gcb","cpu";
#reset-cells = <1>;
cpu-syscon = <&cpu_ctrl>;
};
gpio: pinctrl@e2004064 {
compatible = "microchip,lan966x-pinctrl";
reg = <0xe2004064 0xb4>,
<0xe2010024 0x138>;
resets = <&reset 0>;
reset-names = "switch";
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&gpio 0 0 78>;
interrupt-parent = <&oic>;
interrupt-controller;
interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
tod_pins: tod_pins {
pins = "GPIO_36";
function = "ptpsync_1";
};
fc0_a_pins: fcb4-i2c-pins {
/* RXD, TXD */
pins = "GPIO_9", "GPIO_10";
function = "fc0_a";
};
};
serdes: serdes@e202c000 {
compatible = "microchip,lan966x-serdes";
reg = <0xe202c000 0x9c>,
<0xe2004010 0x4>;
#phy-cells = <2>;
};
mdio1: mdio@e200413c {
#address-cells = <1>;
#size-cells = <0>;
compatible = "microchip,lan966x-miim";
reg = <0xe200413c 0x24>,
<0xe2010020 0x4>;
resets = <&reset 0>;
reset-names = "switch";
lan966x_phy0: ethernet-lan966x_phy@1 {
reg = <1>;
};
lan966x_phy1: ethernet-lan966x_phy@2 {
reg = <2>;
};
};
switch: switch@e0000000 {
compatible = "microchip,lan966x-switch";
reg = <0xe0000000 0x0100000>,
<0xe2000000 0x0800000>;
reg-names = "cpu", "gcb";
interrupt-parent = <&oic>;
interrupts = <12 IRQ_TYPE_LEVEL_HIGH>,
<9 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "xtr", "ana";
resets = <&reset 0>;
reset-names = "switch";
pinctrl-names = "default";
pinctrl-0 = <&tod_pins>;
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
port0: port@0 {
phy-handle = <&lan966x_phy0>;
reg = <0>;
phy-mode = "gmii";
phys = <&serdes 0 CU(0)>;
};
port1: port@1 {
phy-handle = <&lan966x_phy1>;
reg = <1>;
phy-mode = "gmii";
phys = <&serdes 1 CU(1)>;
};
};
};
};
};
};
};
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