summaryrefslogtreecommitdiff
path: root/drivers/net/ethernet/broadcom/bnxt/bnxt_hsi.h
blob: 04a96cc3498a8035e8aa3820ba04d1a13b7b11e3 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730
1731
1732
1733
1734
1735
1736
1737
1738
1739
1740
1741
1742
1743
1744
1745
1746
1747
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759
1760
1761
1762
1763
1764
1765
1766
1767
1768
1769
1770
1771
1772
1773
1774
1775
1776
1777
1778
1779
1780
1781
1782
1783
1784
1785
1786
1787
1788
1789
1790
1791
1792
1793
1794
1795
1796
1797
1798
1799
1800
1801
1802
1803
1804
1805
1806
1807
1808
1809
1810
1811
1812
1813
1814
1815
1816
1817
1818
1819
1820
1821
1822
1823
1824
1825
1826
1827
1828
1829
1830
1831
1832
1833
1834
1835
1836
1837
1838
1839
1840
1841
1842
1843
1844
1845
1846
1847
1848
1849
1850
1851
1852
1853
1854
1855
1856
1857
1858
1859
1860
1861
1862
1863
1864
1865
1866
1867
1868
1869
1870
1871
1872
1873
1874
1875
1876
1877
1878
1879
1880
1881
1882
1883
1884
1885
1886
1887
1888
1889
1890
1891
1892
1893
1894
1895
1896
1897
1898
1899
1900
1901
1902
1903
1904
1905
1906
1907
1908
1909
1910
1911
1912
1913
1914
1915
1916
1917
1918
1919
1920
1921
1922
1923
1924
1925
1926
1927
1928
1929
1930
1931
1932
1933
1934
1935
1936
1937
1938
1939
1940
1941
1942
1943
1944
1945
1946
1947
1948
1949
1950
1951
1952
1953
1954
1955
1956
1957
1958
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
1976
1977
1978
1979
1980
1981
1982
1983
1984
1985
1986
1987
1988
1989
1990
1991
1992
1993
1994
1995
1996
1997
1998
1999
2000
2001
2002
2003
2004
2005
2006
2007
2008
2009
2010
2011
2012
2013
2014
2015
2016
2017
2018
2019
2020
2021
2022
2023
2024
2025
2026
2027
2028
2029
2030
2031
2032
2033
2034
2035
2036
2037
2038
2039
2040
2041
2042
2043
2044
2045
2046
2047
2048
2049
2050
2051
2052
2053
2054
2055
2056
2057
2058
2059
2060
2061
2062
2063
2064
2065
2066
2067
2068
2069
2070
2071
2072
2073
2074
2075
2076
2077
2078
2079
2080
2081
2082
2083
2084
2085
2086
2087
2088
2089
2090
2091
2092
2093
2094
2095
2096
2097
2098
2099
2100
2101
2102
2103
2104
2105
2106
2107
2108
2109
2110
2111
2112
2113
2114
2115
2116
2117
2118
2119
2120
2121
2122
2123
2124
2125
2126
2127
2128
2129
2130
2131
2132
2133
2134
2135
2136
2137
2138
2139
2140
2141
2142
2143
2144
2145
2146
2147
2148
2149
2150
2151
2152
2153
2154
2155
2156
2157
2158
2159
2160
2161
2162
2163
2164
2165
2166
2167
2168
2169
2170
2171
2172
2173
2174
2175
2176
2177
2178
2179
2180
2181
2182
2183
2184
2185
2186
2187
2188
2189
2190
2191
2192
2193
2194
2195
2196
2197
2198
2199
2200
2201
2202
2203
2204
2205
2206
2207
2208
2209
2210
2211
2212
2213
2214
2215
2216
2217
2218
2219
2220
2221
2222
2223
2224
2225
2226
2227
2228
2229
2230
2231
2232
2233
2234
2235
2236
2237
2238
2239
2240
2241
2242
2243
2244
2245
2246
2247
2248
2249
2250
2251
2252
2253
2254
2255
2256
2257
2258
2259
2260
2261
2262
2263
2264
2265
2266
2267
2268
2269
2270
2271
2272
2273
2274
2275
2276
2277
2278
2279
2280
2281
2282
2283
2284
2285
2286
2287
2288
2289
2290
2291
2292
2293
2294
2295
2296
2297
2298
2299
2300
2301
2302
2303
2304
2305
2306
2307
2308
2309
2310
2311
2312
2313
2314
2315
2316
2317
2318
2319
2320
2321
2322
2323
2324
2325
2326
2327
2328
2329
2330
2331
2332
2333
2334
2335
2336
2337
2338
2339
2340
2341
2342
2343
2344
2345
2346
2347
2348
2349
2350
2351
2352
2353
2354
2355
2356
2357
2358
2359
2360
2361
2362
2363
2364
2365
2366
2367
2368
2369
2370
2371
2372
2373
2374
2375
2376
2377
2378
2379
2380
2381
2382
2383
2384
2385
2386
2387
2388
2389
2390
2391
2392
2393
2394
2395
2396
2397
2398
2399
2400
2401
2402
2403
2404
2405
2406
2407
2408
2409
2410
2411
2412
2413
2414
2415
2416
2417
2418
2419
2420
2421
2422
2423
2424
2425
2426
2427
2428
2429
2430
2431
2432
2433
2434
2435
2436
2437
2438
2439
2440
2441
2442
2443
2444
2445
2446
2447
2448
2449
2450
2451
2452
2453
2454
2455
2456
2457
2458
2459
2460
2461
2462
2463
2464
2465
2466
2467
2468
2469
2470
2471
2472
2473
2474
2475
2476
2477
2478
2479
2480
2481
2482
2483
2484
2485
2486
2487
2488
2489
2490
2491
2492
2493
2494
2495
2496
2497
2498
2499
2500
2501
2502
2503
2504
2505
2506
2507
2508
2509
2510
2511
2512
2513
2514
2515
2516
2517
2518
2519
2520
2521
2522
2523
2524
2525
2526
2527
2528
2529
2530
2531
2532
2533
2534
2535
2536
2537
2538
2539
2540
2541
2542
2543
2544
2545
2546
2547
2548
2549
2550
2551
2552
2553
2554
2555
2556
2557
2558
2559
2560
2561
2562
2563
2564
2565
2566
2567
2568
2569
2570
2571
2572
2573
2574
2575
2576
2577
2578
2579
2580
2581
2582
2583
2584
2585
2586
2587
2588
2589
2590
2591
2592
2593
2594
2595
2596
2597
2598
2599
2600
2601
2602
2603
2604
2605
2606
2607
2608
2609
2610
2611
2612
2613
2614
2615
2616
2617
2618
2619
2620
2621
2622
2623
2624
2625
2626
2627
2628
2629
2630
2631
2632
2633
2634
2635
2636
2637
2638
2639
2640
2641
2642
2643
2644
2645
2646
2647
2648
2649
2650
2651
2652
2653
2654
2655
2656
2657
2658
2659
2660
2661
2662
2663
2664
2665
2666
2667
2668
2669
2670
2671
2672
2673
2674
2675
2676
2677
2678
2679
2680
2681
2682
2683
2684
2685
2686
2687
2688
2689
2690
2691
2692
2693
2694
2695
2696
2697
2698
2699
2700
2701
2702
2703
2704
2705
2706
2707
2708
2709
2710
2711
2712
2713
2714
2715
2716
2717
2718
2719
2720
2721
2722
2723
2724
2725
2726
2727
2728
2729
2730
2731
2732
2733
2734
2735
2736
2737
2738
2739
2740
2741
2742
2743
2744
2745
2746
2747
2748
2749
2750
2751
2752
2753
2754
2755
2756
2757
2758
2759
2760
2761
2762
2763
2764
2765
2766
2767
2768
2769
2770
2771
2772
2773
2774
2775
2776
2777
2778
2779
2780
2781
2782
2783
2784
2785
2786
2787
2788
2789
2790
2791
2792
2793
2794
2795
2796
2797
2798
2799
2800
2801
2802
2803
2804
2805
2806
2807
2808
2809
2810
2811
2812
2813
2814
2815
2816
2817
2818
2819
2820
2821
2822
2823
2824
2825
2826
2827
2828
2829
2830
2831
2832
2833
2834
2835
2836
2837
2838
2839
2840
2841
2842
2843
2844
2845
2846
2847
2848
2849
2850
2851
2852
2853
2854
2855
2856
2857
2858
2859
2860
2861
2862
2863
2864
2865
2866
2867
2868
2869
2870
2871
2872
2873
2874
2875
2876
2877
2878
2879
2880
2881
2882
2883
2884
2885
2886
2887
2888
2889
2890
2891
2892
2893
2894
2895
2896
2897
2898
2899
2900
2901
2902
2903
2904
2905
2906
2907
2908
2909
2910
2911
2912
2913
2914
2915
2916
2917
2918
2919
2920
2921
2922
2923
2924
2925
2926
2927
2928
2929
2930
2931
2932
2933
2934
2935
2936
2937
2938
2939
2940
2941
2942
2943
2944
2945
2946
2947
2948
2949
2950
2951
2952
2953
2954
2955
2956
2957
2958
2959
2960
2961
2962
2963
2964
2965
2966
2967
2968
2969
2970
2971
2972
2973
2974
2975
2976
2977
2978
2979
2980
2981
2982
2983
2984
2985
2986
2987
2988
2989
2990
2991
2992
2993
2994
2995
2996
2997
2998
2999
3000
3001
3002
3003
3004
3005
3006
3007
3008
3009
3010
3011
3012
3013
3014
3015
3016
3017
3018
3019
3020
3021
3022
3023
3024
3025
3026
3027
3028
3029
3030
3031
3032
3033
3034
3035
3036
3037
3038
3039
3040
3041
3042
3043
3044
3045
3046
3047
3048
3049
3050
3051
3052
3053
3054
3055
3056
3057
3058
3059
3060
3061
3062
3063
3064
3065
3066
3067
3068
3069
3070
3071
3072
3073
3074
3075
3076
3077
3078
3079
3080
3081
3082
3083
3084
3085
3086
3087
3088
3089
3090
3091
3092
3093
3094
3095
3096
3097
3098
3099
3100
3101
3102
3103
3104
3105
3106
3107
3108
3109
3110
3111
3112
3113
3114
3115
3116
3117
3118
3119
3120
3121
3122
3123
3124
3125
3126
3127
3128
3129
3130
3131
3132
3133
3134
3135
3136
3137
3138
3139
3140
3141
3142
3143
3144
3145
3146
3147
3148
3149
3150
3151
3152
3153
3154
3155
3156
3157
3158
3159
3160
3161
3162
3163
3164
3165
3166
3167
3168
3169
3170
3171
3172
3173
3174
3175
3176
3177
3178
3179
3180
3181
3182
3183
3184
3185
3186
3187
3188
3189
3190
3191
3192
3193
3194
3195
3196
3197
3198
3199
3200
3201
3202
3203
3204
3205
3206
3207
3208
3209
3210
3211
3212
3213
3214
3215
3216
3217
3218
3219
3220
3221
3222
3223
3224
3225
3226
3227
3228
3229
3230
3231
3232
3233
3234
3235
3236
3237
3238
3239
3240
3241
3242
3243
3244
3245
3246
3247
3248
3249
3250
3251
3252
3253
3254
3255
3256
3257
3258
3259
3260
3261
3262
3263
3264
3265
3266
3267
3268
3269
3270
3271
3272
3273
3274
3275
3276
3277
3278
3279
3280
3281
3282
3283
3284
3285
3286
3287
3288
3289
3290
3291
3292
3293
3294
3295
3296
3297
3298
3299
3300
3301
3302
3303
3304
3305
3306
3307
3308
3309
3310
3311
3312
3313
3314
3315
3316
3317
3318
3319
3320
3321
3322
3323
3324
3325
3326
3327
3328
3329
3330
3331
3332
3333
3334
3335
3336
3337
3338
3339
3340
3341
3342
3343
3344
3345
3346
3347
3348
3349
3350
3351
3352
3353
3354
3355
3356
3357
3358
3359
3360
3361
3362
3363
3364
3365
3366
3367
3368
3369
3370
3371
3372
3373
3374
3375
3376
3377
3378
3379
3380
3381
3382
3383
3384
3385
3386
3387
3388
3389
3390
3391
3392
3393
3394
3395
3396
3397
3398
3399
3400
3401
3402
3403
3404
3405
3406
3407
3408
3409
3410
3411
3412
3413
3414
3415
3416
3417
3418
3419
3420
3421
3422
3423
3424
3425
3426
3427
3428
3429
3430
3431
3432
3433
3434
3435
3436
3437
3438
3439
3440
3441
3442
3443
3444
3445
3446
3447
3448
3449
3450
3451
3452
3453
3454
3455
3456
3457
3458
3459
3460
3461
3462
3463
3464
3465
3466
3467
3468
3469
3470
3471
3472
3473
3474
3475
3476
3477
3478
3479
3480
3481
3482
3483
3484
3485
3486
3487
3488
3489
3490
3491
3492
3493
3494
3495
3496
3497
3498
3499
3500
3501
3502
3503
3504
3505
3506
3507
3508
3509
3510
3511
3512
3513
3514
3515
3516
3517
3518
3519
3520
3521
3522
3523
3524
3525
3526
3527
3528
3529
3530
3531
3532
3533
3534
3535
3536
3537
3538
3539
3540
3541
3542
3543
3544
3545
3546
3547
3548
3549
3550
3551
3552
3553
3554
3555
3556
3557
3558
3559
3560
3561
3562
3563
3564
3565
3566
3567
3568
3569
3570
3571
3572
3573
3574
3575
3576
3577
3578
3579
3580
3581
3582
3583
3584
3585
3586
3587
3588
3589
3590
3591
3592
3593
3594
3595
3596
3597
3598
3599
3600
3601
3602
3603
3604
3605
3606
3607
3608
3609
3610
3611
3612
3613
3614
3615
3616
3617
3618
3619
3620
3621
3622
3623
3624
3625
3626
3627
3628
3629
3630
3631
3632
3633
3634
3635
3636
3637
3638
3639
3640
3641
3642
3643
3644
3645
3646
3647
3648
3649
3650
3651
3652
3653
3654
3655
3656
3657
3658
3659
3660
3661
3662
3663
3664
3665
3666
3667
3668
3669
3670
3671
3672
3673
3674
3675
3676
3677
3678
3679
3680
3681
3682
3683
3684
3685
3686
3687
3688
3689
3690
3691
3692
3693
3694
3695
3696
3697
3698
3699
3700
3701
3702
3703
3704
3705
3706
3707
3708
3709
3710
3711
3712
3713
3714
3715
3716
3717
3718
3719
3720
3721
3722
3723
3724
3725
3726
3727
3728
3729
3730
3731
3732
3733
3734
3735
3736
3737
3738
3739
3740
3741
3742
3743
3744
3745
3746
3747
3748
3749
3750
3751
3752
3753
3754
3755
3756
3757
3758
3759
3760
3761
3762
3763
3764
3765
3766
3767
3768
3769
3770
3771
3772
3773
3774
3775
3776
3777
3778
3779
3780
3781
3782
3783
3784
3785
3786
3787
3788
3789
3790
3791
3792
3793
3794
3795
3796
3797
3798
3799
3800
3801
3802
3803
3804
3805
3806
3807
3808
3809
3810
3811
3812
3813
3814
3815
3816
3817
3818
3819
3820
3821
3822
3823
3824
3825
3826
3827
3828
3829
3830
3831
3832
3833
3834
3835
3836
3837
3838
3839
3840
3841
3842
3843
3844
3845
3846
3847
3848
3849
3850
3851
3852
3853
3854
3855
3856
3857
3858
3859
3860
3861
3862
3863
3864
3865
3866
3867
3868
3869
3870
3871
3872
3873
3874
3875
3876
3877
3878
3879
3880
3881
3882
3883
3884
3885
3886
3887
3888
3889
3890
3891
3892
3893
3894
3895
3896
3897
3898
3899
3900
3901
3902
3903
3904
3905
3906
3907
3908
3909
3910
3911
3912
3913
3914
3915
3916
3917
3918
3919
3920
3921
3922
3923
3924
3925
3926
3927
3928
3929
3930
3931
3932
3933
3934
3935
3936
3937
3938
3939
3940
3941
3942
3943
3944
3945
3946
3947
3948
3949
3950
3951
3952
3953
3954
3955
3956
3957
3958
3959
3960
3961
3962
3963
3964
3965
3966
3967
3968
3969
3970
3971
3972
3973
3974
3975
3976
3977
3978
3979
3980
3981
3982
3983
3984
3985
3986
3987
3988
3989
3990
3991
3992
3993
3994
3995
3996
3997
3998
3999
4000
4001
4002
4003
4004
4005
4006
4007
4008
4009
4010
4011
4012
4013
4014
4015
4016
4017
4018
4019
4020
4021
4022
4023
4024
4025
4026
4027
4028
4029
4030
4031
4032
4033
4034
4035
4036
4037
4038
4039
4040
4041
4042
4043
4044
4045
4046
4047
4048
4049
4050
4051
4052
4053
4054
4055
4056
4057
4058
4059
4060
4061
4062
4063
4064
4065
4066
4067
4068
4069
4070
4071
4072
4073
4074
4075
4076
4077
4078
4079
4080
4081
4082
4083
4084
4085
4086
4087
4088
4089
4090
4091
4092
4093
4094
4095
4096
4097
4098
4099
4100
4101
4102
4103
4104
4105
4106
4107
4108
4109
4110
4111
4112
4113
4114
4115
4116
4117
4118
4119
4120
4121
4122
4123
4124
4125
4126
4127
4128
4129
4130
4131
4132
4133
4134
4135
4136
4137
4138
4139
4140
4141
4142
4143
4144
4145
4146
4147
4148
4149
4150
4151
4152
4153
4154
4155
4156
4157
4158
4159
4160
4161
4162
4163
4164
4165
4166
4167
4168
4169
4170
4171
4172
4173
4174
4175
4176
4177
4178
4179
4180
4181
4182
4183
4184
4185
4186
4187
4188
4189
4190
4191
4192
4193
4194
4195
4196
4197
4198
4199
4200
4201
4202
4203
4204
4205
4206
4207
4208
4209
4210
4211
4212
4213
4214
4215
4216
4217
4218
4219
4220
4221
4222
4223
4224
4225
4226
4227
4228
4229
4230
4231
4232
4233
4234
4235
4236
4237
4238
4239
4240
4241
4242
4243
4244
4245
4246
4247
4248
4249
4250
4251
4252
4253
4254
4255
4256
4257
4258
4259
4260
4261
4262
4263
4264
4265
4266
4267
4268
4269
4270
4271
4272
4273
4274
4275
4276
4277
4278
4279
4280
4281
4282
4283
4284
4285
4286
4287
4288
4289
4290
4291
4292
4293
4294
4295
4296
4297
4298
4299
4300
4301
4302
4303
4304
4305
4306
4307
4308
4309
4310
4311
4312
4313
4314
4315
4316
4317
4318
4319
4320
4321
4322
4323
4324
4325
4326
4327
4328
4329
4330
4331
4332
4333
4334
4335
4336
4337
4338
4339
4340
4341
4342
4343
4344
4345
4346
4347
4348
4349
4350
4351
4352
4353
4354
4355
4356
4357
4358
4359
4360
4361
4362
4363
4364
4365
4366
4367
4368
4369
4370
4371
4372
4373
4374
4375
4376
4377
4378
4379
4380
4381
4382
4383
4384
4385
4386
4387
4388
4389
4390
4391
4392
4393
4394
4395
4396
4397
4398
4399
4400
4401
4402
4403
4404
4405
4406
4407
4408
4409
4410
4411
4412
4413
4414
4415
4416
4417
4418
4419
4420
4421
4422
4423
4424
4425
4426
4427
4428
4429
4430
4431
4432
4433
4434
4435
4436
4437
4438
4439
4440
4441
4442
4443
4444
4445
4446
4447
4448
4449
4450
4451
4452
4453
4454
4455
4456
4457
4458
4459
4460
4461
4462
4463
4464
4465
4466
4467
4468
4469
4470
4471
4472
4473
4474
4475
4476
4477
4478
4479
4480
4481
4482
4483
4484
4485
4486
4487
4488
4489
4490
4491
4492
4493
4494
4495
4496
4497
4498
4499
4500
4501
4502
4503
4504
4505
4506
4507
4508
4509
4510
4511
4512
4513
4514
4515
4516
4517
4518
/* Broadcom NetXtreme-C/E network driver.
 *
 * Copyright (c) 2014-2016 Broadcom Corporation
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation.
 */

#ifndef BNXT_HSI_H
#define BNXT_HSI_H

/* per-context HW statistics -- chip view */
struct ctx_hw_stats  {
	__le64 rx_ucast_pkts;
	__le64 rx_mcast_pkts;
	__le64 rx_bcast_pkts;
	__le64 rx_discard_pkts;
	__le64 rx_drop_pkts;
	__le64 rx_ucast_bytes;
	__le64 rx_mcast_bytes;
	__le64 rx_bcast_bytes;
	__le64 tx_ucast_pkts;
	__le64 tx_mcast_pkts;
	__le64 tx_bcast_pkts;
	__le64 tx_discard_pkts;
	__le64 tx_drop_pkts;
	__le64 tx_ucast_bytes;
	__le64 tx_mcast_bytes;
	__le64 tx_bcast_bytes;
	__le64 tpa_pkts;
	__le64 tpa_bytes;
	__le64 tpa_events;
	__le64 tpa_aborts;
};

/* Statistics Ejection Buffer Completion Record (16 bytes) */
struct eject_cmpl {
	__le16 type;
	#define EJECT_CMPL_TYPE_MASK				    0x3fUL
	#define EJECT_CMPL_TYPE_SFT				    0
	#define EJECT_CMPL_TYPE_STAT_EJECT			   0x1aUL
	__le16 len;
	__le32 opaque;
	__le32 v;
	#define EJECT_CMPL_V					    0x1UL
	__le32 unused_2;
};

/* HWRM Completion Record (16 bytes) */
struct hwrm_cmpl {
	__le16 type;
	#define HWRM_CMPL_TYPE_MASK				    0x3fUL
	#define HWRM_CMPL_TYPE_SFT				    0
	#define HWRM_CMPL_TYPE_HWRM_DONE			   0x20UL
	__le16 sequence_id;
	__le32 unused_1;
	__le32 v;
	#define HWRM_CMPL_V					    0x1UL
	__le32 unused_3;
};

/* HWRM Forwarded Request (16 bytes) */
struct hwrm_fwd_req_cmpl {
	__le16 req_len_type;
	#define HWRM_FWD_REQ_CMPL_TYPE_MASK			    0x3fUL
	#define HWRM_FWD_REQ_CMPL_TYPE_SFT			    0
	#define HWRM_FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ		   0x22UL
	#define HWRM_FWD_REQ_CMPL_REQ_LEN_MASK			    0xffc0UL
	#define HWRM_FWD_REQ_CMPL_REQ_LEN_SFT			    6
	__le16 source_id;
	__le32 unused_0;
	__le32 req_buf_addr_v[2];
	#define HWRM_FWD_REQ_CMPL_V				    0x1UL
	#define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_MASK		    0xfffffffeUL
	#define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_SFT		    1
};

/* HWRM Forwarded Response (16 bytes) */
struct hwrm_fwd_resp_cmpl {
	__le16 type;
	#define HWRM_FWD_RESP_CMPL_TYPE_MASK			    0x3fUL
	#define HWRM_FWD_RESP_CMPL_TYPE_SFT			    0
	#define HWRM_FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP		   0x24UL
	__le16 source_id;
	__le16 resp_len;
	__le16 unused_1;
	__le32 resp_buf_addr_v[2];
	#define HWRM_FWD_RESP_CMPL_V				    0x1UL
	#define HWRM_FWD_RESP_CMPL_RESP_BUF_ADDR_MASK		    0xfffffffeUL
	#define HWRM_FWD_RESP_CMPL_RESP_BUF_ADDR_SFT		    1
};

/* HWRM Asynchronous Event Completion Record (16 bytes) */
struct hwrm_async_event_cmpl {
	__le16 type;
	#define HWRM_ASYNC_EVENT_CMPL_TYPE_MASK		    0x3fUL
	#define HWRM_ASYNC_EVENT_CMPL_TYPE_SFT			    0
	#define HWRM_ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT       0x2eUL
	__le16 event_id;
	#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE 0x0UL
	#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE    0x1UL
	#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE  0x2UL
	#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE  0x3UL
	#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL
	#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED 0x5UL
	#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL
	#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE 0x7UL
	#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD   0x10UL
	#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD     0x11UL
	#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_FLR_PROC_CMPLT 0x12UL
	#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD     0x20UL
	#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD       0x21UL
	#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR		   0x30UL
	#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE 0x31UL
	#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE 0x32UL
	#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE      0x33UL
	#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR	   0xffUL
	__le32 event_data2;
	u8 opaque_v;
	#define HWRM_ASYNC_EVENT_CMPL_V			    0x1UL
	#define HWRM_ASYNC_EVENT_CMPL_OPAQUE_MASK		    0xfeUL
	#define HWRM_ASYNC_EVENT_CMPL_OPAQUE_SFT		    1
	u8 timestamp_lo;
	__le16 timestamp_hi;
	__le32 event_data1;
};

/* HWRM Asynchronous Event Completion Record for link status change (16 bytes) */
struct hwrm_async_event_cmpl_link_status_change {
	__le16 type;
	#define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK 0x3fUL
	#define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_SFT  0
	#define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
	__le16 event_id;
	#define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE 0x0UL
	__le32 event_data2;
	u8 opaque_v;
	#define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V	    0x1UL
	#define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_MASK 0xfeUL
	#define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_SFT 1
	u8 timestamp_lo;
	__le16 timestamp_hi;
	__le32 event_data1;
	#define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE 0x1UL
	#define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_DOWN (0x0UL << 0)
	#define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP (0x1UL << 0)
	#define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_LAST    HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP
	#define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_MASK 0xeUL
	#define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_SFT 1
	#define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffff0UL
	#define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_SFT 4
};

/* HWRM Asynchronous Event Completion Record for link MTU change (16 bytes) */
struct hwrm_async_event_cmpl_link_mtu_change {
	__le16 type;
	#define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_MASK    0x3fUL
	#define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_SFT     0
	#define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
	__le16 event_id;
	#define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LINK_MTU_CHANGE 0x1UL
	__le32 event_data2;
	u8 opaque_v;
	#define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_V	    0x1UL
	#define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_MASK  0xfeUL
	#define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_SFT   1
	u8 timestamp_lo;
	__le16 timestamp_hi;
	__le32 event_data1;
	#define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_MASK 0xffffUL
	#define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_SFT 0
};

/* HWRM Asynchronous Event Completion Record for link speed change (16 bytes) */
struct hwrm_async_event_cmpl_link_speed_change {
	__le16 type;
	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_MASK  0x3fUL
	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_SFT   0
	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
	__le16 event_id;
	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LINK_SPEED_CHANGE 0x2UL
	__le32 event_data2;
	u8 opaque_v;
	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_V	    0x1UL
	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_MASK 0xfeUL
	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_SFT 1
	u8 timestamp_lo;
	__le16 timestamp_hi;
	__le32 event_data1;
	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_FORCE 0x1UL
	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_MASK 0xfffeUL
	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_SFT 1
	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100MB (0x1UL << 1)
	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_1GB (0xaUL << 1)
	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2GB (0x14UL << 1)
	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2_5GB (0x19UL << 1)
	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_10GB (0x64UL << 1)
	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_20GB (0xc8UL << 1)
	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_25GB (0xfaUL << 1)
	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_40GB (0x190UL << 1)
	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_50GB (0x1f4UL << 1)
	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100GB (0x3e8UL << 1)
	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_LAST    HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100GB
	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffff0000UL
	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_SFT 16
};

/* HWRM Asynchronous Event Completion Record for DCB Config change (16 bytes) */
struct hwrm_async_event_cmpl_dcb_config_change {
	__le16 type;
	#define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_MASK  0x3fUL
	#define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_SFT   0
	#define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
	__le16 event_id;
	#define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_DCB_CONFIG_CHANGE 0x3UL
	__le32 event_data2;
	u8 opaque_v;
	#define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_V	    0x1UL
	#define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_MASK 0xfeUL
	#define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_SFT 1
	u8 timestamp_lo;
	__le16 timestamp_hi;
	__le32 event_data1;
	#define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffffUL
	#define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_SFT 0
};

/* HWRM Asynchronous Event Completion Record for port connection not allowed (16 bytes) */
struct hwrm_async_event_cmpl_port_conn_not_allowed {
	__le16 type;
	#define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK 0x3fUL
	#define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_SFT 0
	#define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT 0x2eUL
	__le16 event_id;
	#define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL
	__le32 event_data2;
	u8 opaque_v;
	#define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V      0x1UL
	#define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_MASK 0xfeUL
	#define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_SFT 1
	u8 timestamp_lo;
	__le16 timestamp_hi;
	__le32 event_data1;
	#define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK 0xffffUL
	#define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT 0
	#define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_MASK 0xff0000UL
	#define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_SFT 16
	#define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_NONE (0x0UL << 16)
	#define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_DISABLETX (0x1UL << 16)
	#define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_WARNINGMSG (0x2UL << 16)
	#define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN (0x3UL << 16)
	#define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_LAST    HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN
};

/* HWRM Asynchronous Event Completion Record for link speed config not allowed (16 bytes) */
struct hwrm_async_event_cmpl_link_speed_cfg_not_allowed {
	__le16 type;
	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_MASK 0x3fUL
	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_SFT 0
	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT 0x2eUL
	__le16 event_id;
	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED 0x5UL
	__le32 event_data2;
	u8 opaque_v;
	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_V 0x1UL
	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_MASK 0xfeUL
	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_SFT 1
	u8 timestamp_lo;
	__le16 timestamp_hi;
	__le32 event_data1;
	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK 0xffffUL
	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT 0
};

/* HWRM Asynchronous Event Completion Record for link speed configuration change (16 bytes) */
struct hwrm_async_event_cmpl_link_speed_cfg_change {
	__le16 type;
	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_MASK 0x3fUL
	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_SFT 0
	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
	__le16 event_id;
	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL
	__le32 event_data2;
	u8 opaque_v;
	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_V      0x1UL
	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_MASK 0xfeUL
	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_SFT 1
	u8 timestamp_lo;
	__le16 timestamp_hi;
	__le32 event_data1;
	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffffUL
	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT 0
	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_SUPPORTED_LINK_SPEEDS_CHANGE 0x10000UL
	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_ILLEGAL_LINK_SPEED_CFG 0x20000UL
};

/* HWRM Asynchronous Event Completion Record for Function Driver Unload (16 bytes) */
struct hwrm_async_event_cmpl_func_drvr_unload {
	__le16 type;
	#define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_MASK   0x3fUL
	#define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_SFT    0
	#define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT 0x2eUL
	__le16 event_id;
	#define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_FUNC_DRVR_UNLOAD 0x10UL
	__le32 event_data2;
	u8 opaque_v;
	#define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_V	    0x1UL
	#define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_MASK 0xfeUL
	#define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_SFT  1
	u8 timestamp_lo;
	__le16 timestamp_hi;
	__le32 event_data1;
	#define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK 0xffffUL
	#define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT 0
};

/* HWRM Asynchronous Event Completion Record for Function Driver load (16 bytes) */
struct hwrm_async_event_cmpl_func_drvr_load {
	__le16 type;
	#define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_MASK     0x3fUL
	#define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_SFT      0
	#define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT 0x2eUL
	__le16 event_id;
	#define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_FUNC_DRVR_LOAD 0x11UL
	__le32 event_data2;
	u8 opaque_v;
	#define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_V		    0x1UL
	#define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_MASK   0xfeUL
	#define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_SFT    1
	u8 timestamp_lo;
	__le16 timestamp_hi;
	__le32 event_data1;
	#define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK 0xffffUL
	#define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0
};

/* HWRM Asynchronous Event Completion Record for PF Driver Unload (16 bytes) */
struct hwrm_async_event_cmpl_pf_drvr_unload {
	__le16 type;
	#define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_MASK     0x3fUL
	#define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_SFT      0
	#define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT 0x2eUL
	__le16 event_id;
	#define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_PF_DRVR_UNLOAD 0x20UL
	__le32 event_data2;
	u8 opaque_v;
	#define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_V		    0x1UL
	#define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_MASK   0xfeUL
	#define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_SFT    1
	u8 timestamp_lo;
	__le16 timestamp_hi;
	__le32 event_data1;
	#define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK 0xffffUL
	#define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT 0
	#define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_MASK 0x70000UL
	#define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_SFT 16
};

/* HWRM Asynchronous Event Completion Record for PF Driver load (16 bytes) */
struct hwrm_async_event_cmpl_pf_drvr_load {
	__le16 type;
	#define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_MASK       0x3fUL
	#define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_SFT	    0
	#define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT 0x2eUL
	__le16 event_id;
	#define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_PF_DRVR_LOAD 0x21UL
	__le32 event_data2;
	u8 opaque_v;
	#define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_V		    0x1UL
	#define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_MASK     0xfeUL
	#define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_SFT      1
	u8 timestamp_lo;
	__le16 timestamp_hi;
	__le32 event_data1;
	#define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK 0xffffUL
	#define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0
	#define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_MASK 0x70000UL
	#define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_SFT 16
};

/* HWRM Asynchronous Event Completion Record for VF FLR (16 bytes) */
struct hwrm_async_event_cmpl_vf_flr {
	__le16 type;
	#define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_MASK		    0x3fUL
	#define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_SFT		    0
	#define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_HWRM_ASYNC_EVENT 0x2eUL
	__le16 event_id;
	#define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_VF_FLR      0x30UL
	__le32 event_data2;
	u8 opaque_v;
	#define HWRM_ASYNC_EVENT_CMPL_VF_FLR_V			    0x1UL
	#define HWRM_ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_MASK	    0xfeUL
	#define HWRM_ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_SFT	    1
	u8 timestamp_lo;
	__le16 timestamp_hi;
	__le32 event_data1;
	#define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_MASK 0xffffUL
	#define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_SFT 0
};

/* HWRM Asynchronous Event Completion Record for VF MAC Addr change (16 bytes) */
struct hwrm_async_event_cmpl_vf_mac_addr_change {
	__le16 type;
	#define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_MASK 0x3fUL
	#define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_SFT  0
	#define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
	__le16 event_id;
	#define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_VF_MAC_ADDR_CHANGE 0x31UL
	__le32 event_data2;
	u8 opaque_v;
	#define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_V	    0x1UL
	#define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_MASK 0xfeUL
	#define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_SFT 1
	u8 timestamp_lo;
	__le16 timestamp_hi;
	__le32 event_data1;
	#define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_MASK 0xffffUL
	#define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_SFT 0
};

/* HWRM Asynchronous Event Completion Record for PF-VF communication status change (16 bytes) */
struct hwrm_async_event_cmpl_pf_vf_comm_status_change {
	__le16 type;
	#define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_MASK 0x3fUL
	#define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_SFT 0
	#define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
	__le16 event_id;
	#define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_PF_VF_COMM_STATUS_CHANGE 0x32UL
	__le32 event_data2;
	u8 opaque_v;
	#define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_V   0x1UL
	#define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_MASK 0xfeUL
	#define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_SFT 1
	u8 timestamp_lo;
	__le16 timestamp_hi;
	__le32 event_data1;
	#define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_DATA1_COMM_ESTABLISHED 0x1UL
};

/* HWRM Asynchronous Event Completion Record for VF configuration change (16 bytes) */
struct hwrm_async_event_cmpl_vf_cfg_change {
	__le16 type;
	#define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_MASK      0x3fUL
	#define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_SFT       0
	#define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
	__le16 event_id;
	#define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE 0x33UL
	__le32 event_data2;
	u8 opaque_v;
	#define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_V		    0x1UL
	#define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_MASK    0xfeUL
	#define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_SFT     1
	u8 timestamp_lo;
	__le16 timestamp_hi;
	__le32 event_data1;
	#define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MTU_CHANGE 0x1UL
	#define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MRU_CHANGE 0x2UL
	#define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_MAC_ADDR_CHANGE 0x4UL
	#define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE 0x8UL
};

/* HWRM Asynchronous Event Completion Record for HWRM Error (16 bytes) */
struct hwrm_async_event_cmpl_hwrm_error {
	__le16 type;
	#define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_MASK	    0x3fUL
	#define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_SFT	    0
	#define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT 0x2eUL
	__le16 event_id;
	#define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR 0xffUL
	__le32 event_data2;
	#define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_MASK 0xffUL
	#define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_SFT 0
	#define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_WARNING 0x0UL
	#define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_NONFATAL 0x1UL
	#define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL 0x2UL
	#define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_LAST    HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL
	u8 opaque_v;
	#define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_V		    0x1UL
	#define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_MASK       0xfeUL
	#define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_SFT	    1
	u8 timestamp_lo;
	__le16 timestamp_hi;
	__le32 event_data1;
	#define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA1_TIMESTAMP 0x1UL
};

/* HW Resource Manager Specification 1.5.1 */
#define HWRM_VERSION_MAJOR	1
#define HWRM_VERSION_MINOR	5
#define HWRM_VERSION_UPDATE	1

#define HWRM_VERSION_STR	"1.5.1"
/*
 * Following is the signature for HWRM message field that indicates not
 * applicable (All F's). Need to cast it the size of the field if needed.
 */
#define HWRM_NA_SIGNATURE	((__le32)(-1))
#define HWRM_MAX_REQ_LEN    (128)  /* hwrm_func_buf_rgtr */
#define HWRM_MAX_RESP_LEN    (176)  /* hwrm_func_qstats */
#define HW_HASH_INDEX_SIZE      0x80    /* 7 bit indirection table index. */
#define HW_HASH_KEY_SIZE	40
#define HWRM_RESP_VALID_KEY      1 /* valid key for HWRM response */
/* Input (16 bytes) */
struct input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
};

/* Output (8 bytes) */
struct output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
};

/* Command numbering (8 bytes) */
struct cmd_nums {
	__le16 req_type;
	#define HWRM_VER_GET					   (0x0UL)
	#define HWRM_FUNC_BUF_UNRGTR				   (0xeUL)
	#define HWRM_FUNC_VF_CFG				   (0xfUL)
	#define RESERVED1					   (0x10UL)
	#define HWRM_FUNC_RESET				   (0x11UL)
	#define HWRM_FUNC_GETFID				   (0x12UL)
	#define HWRM_FUNC_VF_ALLOC				   (0x13UL)
	#define HWRM_FUNC_VF_FREE				   (0x14UL)
	#define HWRM_FUNC_QCAPS				   (0x15UL)
	#define HWRM_FUNC_QCFG					   (0x16UL)
	#define HWRM_FUNC_CFG					   (0x17UL)
	#define HWRM_FUNC_QSTATS				   (0x18UL)
	#define HWRM_FUNC_CLR_STATS				   (0x19UL)
	#define HWRM_FUNC_DRV_UNRGTR				   (0x1aUL)
	#define HWRM_FUNC_VF_RESC_FREE				   (0x1bUL)
	#define HWRM_FUNC_VF_VNIC_IDS_QUERY			   (0x1cUL)
	#define HWRM_FUNC_DRV_RGTR				   (0x1dUL)
	#define HWRM_FUNC_DRV_QVER				   (0x1eUL)
	#define HWRM_FUNC_BUF_RGTR				   (0x1fUL)
	#define HWRM_PORT_PHY_CFG				   (0x20UL)
	#define HWRM_PORT_MAC_CFG				   (0x21UL)
	#define HWRM_PORT_TS_QUERY				   (0x22UL)
	#define HWRM_PORT_QSTATS				   (0x23UL)
	#define HWRM_PORT_LPBK_QSTATS				   (0x24UL)
	#define HWRM_PORT_CLR_STATS				   (0x25UL)
	#define HWRM_PORT_LPBK_CLR_STATS			   (0x26UL)
	#define HWRM_PORT_PHY_QCFG				   (0x27UL)
	#define HWRM_PORT_MAC_QCFG				   (0x28UL)
	#define HWRM_PORT_BLINK_LED				   (0x29UL)
	#define HWRM_PORT_PHY_QCAPS				   (0x2aUL)
	#define HWRM_PORT_PHY_I2C_WRITE			   (0x2bUL)
	#define HWRM_PORT_PHY_I2C_READ				   (0x2cUL)
	#define HWRM_QUEUE_QPORTCFG				   (0x30UL)
	#define HWRM_QUEUE_QCFG				   (0x31UL)
	#define HWRM_QUEUE_CFG					   (0x32UL)
	#define RESERVED2					   (0x33UL)
	#define RESERVED3					   (0x34UL)
	#define HWRM_QUEUE_PFCENABLE_QCFG			   (0x35UL)
	#define HWRM_QUEUE_PFCENABLE_CFG			   (0x36UL)
	#define HWRM_QUEUE_PRI2COS_QCFG			   (0x37UL)
	#define HWRM_QUEUE_PRI2COS_CFG				   (0x38UL)
	#define HWRM_QUEUE_COS2BW_QCFG				   (0x39UL)
	#define HWRM_QUEUE_COS2BW_CFG				   (0x3aUL)
	#define HWRM_VNIC_ALLOC				   (0x40UL)
	#define HWRM_VNIC_FREE					   (0x41UL)
	#define HWRM_VNIC_CFG					   (0x42UL)
	#define HWRM_VNIC_QCFG					   (0x43UL)
	#define HWRM_VNIC_TPA_CFG				   (0x44UL)
	#define HWRM_VNIC_TPA_QCFG				   (0x45UL)
	#define HWRM_VNIC_RSS_CFG				   (0x46UL)
	#define HWRM_VNIC_RSS_QCFG				   (0x47UL)
	#define HWRM_VNIC_PLCMODES_CFG				   (0x48UL)
	#define HWRM_VNIC_PLCMODES_QCFG			   (0x49UL)
	#define HWRM_VNIC_QCAPS				   (0x4aUL)
	#define HWRM_RING_ALLOC				   (0x50UL)
	#define HWRM_RING_FREE					   (0x51UL)
	#define HWRM_RING_CMPL_RING_QAGGINT_PARAMS		   (0x52UL)
	#define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS		   (0x53UL)
	#define HWRM_RING_RESET				   (0x5eUL)
	#define HWRM_RING_GRP_ALLOC				   (0x60UL)
	#define HWRM_RING_GRP_FREE				   (0x61UL)
	#define RESERVED5					   (0x64UL)
	#define RESERVED6					   (0x65UL)
	#define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC			   (0x70UL)
	#define HWRM_VNIC_RSS_COS_LB_CTX_FREE			   (0x71UL)
	#define HWRM_CFA_L2_FILTER_ALLOC			   (0x90UL)
	#define HWRM_CFA_L2_FILTER_FREE			   (0x91UL)
	#define HWRM_CFA_L2_FILTER_CFG				   (0x92UL)
	#define HWRM_CFA_L2_SET_RX_MASK			   (0x93UL)
	#define RESERVED4					   (0x94UL)
	#define HWRM_CFA_TUNNEL_FILTER_ALLOC			   (0x95UL)
	#define HWRM_CFA_TUNNEL_FILTER_FREE			   (0x96UL)
	#define HWRM_CFA_ENCAP_RECORD_ALLOC			   (0x97UL)
	#define HWRM_CFA_ENCAP_RECORD_FREE			   (0x98UL)
	#define HWRM_CFA_NTUPLE_FILTER_ALLOC			   (0x99UL)
	#define HWRM_CFA_NTUPLE_FILTER_FREE			   (0x9aUL)
	#define HWRM_CFA_NTUPLE_FILTER_CFG			   (0x9bUL)
	#define HWRM_CFA_EM_FLOW_ALLOC				   (0x9cUL)
	#define HWRM_CFA_EM_FLOW_FREE				   (0x9dUL)
	#define HWRM_CFA_EM_FLOW_CFG				   (0x9eUL)
	#define HWRM_TUNNEL_DST_PORT_QUERY			   (0xa0UL)
	#define HWRM_TUNNEL_DST_PORT_ALLOC			   (0xa1UL)
	#define HWRM_TUNNEL_DST_PORT_FREE			   (0xa2UL)
	#define HWRM_STAT_CTX_ALLOC				   (0xb0UL)
	#define HWRM_STAT_CTX_FREE				   (0xb1UL)
	#define HWRM_STAT_CTX_QUERY				   (0xb2UL)
	#define HWRM_STAT_CTX_CLR_STATS			   (0xb3UL)
	#define HWRM_FW_RESET					   (0xc0UL)
	#define HWRM_FW_QSTATUS				   (0xc1UL)
	#define HWRM_FW_SET_TIME				   (0xc8UL)
	#define HWRM_FW_GET_TIME				   (0xc9UL)
	#define HWRM_EXEC_FWD_RESP				   (0xd0UL)
	#define HWRM_REJECT_FWD_RESP				   (0xd1UL)
	#define HWRM_FWD_RESP					   (0xd2UL)
	#define HWRM_FWD_ASYNC_EVENT_CMPL			   (0xd3UL)
	#define HWRM_TEMP_MONITOR_QUERY			   (0xe0UL)
	#define HWRM_WOL_FILTER_ALLOC				   (0xf0UL)
	#define HWRM_WOL_FILTER_FREE				   (0xf1UL)
	#define HWRM_WOL_FILTER_QCFG				   (0xf2UL)
	#define HWRM_WOL_REASON_QCFG				   (0xf3UL)
	#define HWRM_DBG_READ_DIRECT				   (0xff10UL)
	#define HWRM_DBG_READ_INDIRECT				   (0xff11UL)
	#define HWRM_DBG_WRITE_DIRECT				   (0xff12UL)
	#define HWRM_DBG_WRITE_INDIRECT			   (0xff13UL)
	#define HWRM_DBG_DUMP					   (0xff14UL)
	#define HWRM_NVM_INSTALL_UPDATE			   (0xfff3UL)
	#define HWRM_NVM_MODIFY				   (0xfff4UL)
	#define HWRM_NVM_VERIFY_UPDATE				   (0xfff5UL)
	#define HWRM_NVM_GET_DEV_INFO				   (0xfff6UL)
	#define HWRM_NVM_ERASE_DIR_ENTRY			   (0xfff7UL)
	#define HWRM_NVM_MOD_DIR_ENTRY				   (0xfff8UL)
	#define HWRM_NVM_FIND_DIR_ENTRY			   (0xfff9UL)
	#define HWRM_NVM_GET_DIR_ENTRIES			   (0xfffaUL)
	#define HWRM_NVM_GET_DIR_INFO				   (0xfffbUL)
	#define HWRM_NVM_RAW_DUMP				   (0xfffcUL)
	#define HWRM_NVM_READ					   (0xfffdUL)
	#define HWRM_NVM_WRITE					   (0xfffeUL)
	#define HWRM_NVM_RAW_WRITE_BLK				   (0xffffUL)
	__le16 unused_0[3];
};

/* Return Codes (8 bytes) */
struct ret_codes {
	__le16 error_code;
	#define HWRM_ERR_CODE_SUCCESS				   (0x0UL)
	#define HWRM_ERR_CODE_FAIL				   (0x1UL)
	#define HWRM_ERR_CODE_INVALID_PARAMS			   (0x2UL)
	#define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED		   (0x3UL)
	#define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR		   (0x4UL)
	#define HWRM_ERR_CODE_INVALID_FLAGS			   (0x5UL)
	#define HWRM_ERR_CODE_INVALID_ENABLES			   (0x6UL)
	#define HWRM_ERR_CODE_HWRM_ERROR			   (0xfUL)
	#define HWRM_ERR_CODE_UNKNOWN_ERR			   (0xfffeUL)
	#define HWRM_ERR_CODE_CMD_NOT_SUPPORTED		   (0xffffUL)
	__le16 unused_0[3];
};

/* Output (16 bytes) */
struct hwrm_err_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le32 opaque_0;
	__le16 opaque_1;
	u8 cmd_err;
	u8 valid;
};

/* Port Tx Statistics Formats (408 bytes) */
struct tx_port_stats {
	__le64 tx_64b_frames;
	__le64 tx_65b_127b_frames;
	__le64 tx_128b_255b_frames;
	__le64 tx_256b_511b_frames;
	__le64 tx_512b_1023b_frames;
	__le64 tx_1024b_1518_frames;
	__le64 tx_good_vlan_frames;
	__le64 tx_1519b_2047_frames;
	__le64 tx_2048b_4095b_frames;
	__le64 tx_4096b_9216b_frames;
	__le64 tx_9217b_16383b_frames;
	__le64 tx_good_frames;
	__le64 tx_total_frames;
	__le64 tx_ucast_frames;
	__le64 tx_mcast_frames;
	__le64 tx_bcast_frames;
	__le64 tx_pause_frames;
	__le64 tx_pfc_frames;
	__le64 tx_jabber_frames;
	__le64 tx_fcs_err_frames;
	__le64 tx_control_frames;
	__le64 tx_oversz_frames;
	__le64 tx_single_dfrl_frames;
	__le64 tx_multi_dfrl_frames;
	__le64 tx_single_coll_frames;
	__le64 tx_multi_coll_frames;
	__le64 tx_late_coll_frames;
	__le64 tx_excessive_coll_frames;
	__le64 tx_frag_frames;
	__le64 tx_err;
	__le64 tx_tagged_frames;
	__le64 tx_dbl_tagged_frames;
	__le64 tx_runt_frames;
	__le64 tx_fifo_underruns;
	__le64 tx_pfc_ena_frames_pri0;
	__le64 tx_pfc_ena_frames_pri1;
	__le64 tx_pfc_ena_frames_pri2;
	__le64 tx_pfc_ena_frames_pri3;
	__le64 tx_pfc_ena_frames_pri4;
	__le64 tx_pfc_ena_frames_pri5;
	__le64 tx_pfc_ena_frames_pri6;
	__le64 tx_pfc_ena_frames_pri7;
	__le64 tx_eee_lpi_events;
	__le64 tx_eee_lpi_duration;
	__le64 tx_llfc_logical_msgs;
	__le64 tx_hcfc_msgs;
	__le64 tx_total_collisions;
	__le64 tx_bytes;
	__le64 tx_xthol_frames;
	__le64 tx_stat_discard;
	__le64 tx_stat_error;
};

/* Port Rx Statistics Formats (528 bytes) */
struct rx_port_stats {
	__le64 rx_64b_frames;
	__le64 rx_65b_127b_frames;
	__le64 rx_128b_255b_frames;
	__le64 rx_256b_511b_frames;
	__le64 rx_512b_1023b_frames;
	__le64 rx_1024b_1518_frames;
	__le64 rx_good_vlan_frames;
	__le64 rx_1519b_2047b_frames;
	__le64 rx_2048b_4095b_frames;
	__le64 rx_4096b_9216b_frames;
	__le64 rx_9217b_16383b_frames;
	__le64 rx_total_frames;
	__le64 rx_ucast_frames;
	__le64 rx_mcast_frames;
	__le64 rx_bcast_frames;
	__le64 rx_fcs_err_frames;
	__le64 rx_ctrl_frames;
	__le64 rx_pause_frames;
	__le64 rx_pfc_frames;
	__le64 rx_unsupported_opcode_frames;
	__le64 rx_unsupported_da_pausepfc_frames;
	__le64 rx_wrong_sa_frames;
	__le64 rx_align_err_frames;
	__le64 rx_oor_len_frames;
	__le64 rx_code_err_frames;
	__le64 rx_false_carrier_frames;
	__le64 rx_ovrsz_frames;
	__le64 rx_jbr_frames;
	__le64 rx_mtu_err_frames;
	__le64 rx_match_crc_frames;
	__le64 rx_promiscuous_frames;
	__le64 rx_tagged_frames;
	__le64 rx_double_tagged_frames;
	__le64 rx_trunc_frames;
	__le64 rx_good_frames;
	__le64 rx_pfc_xon2xoff_frames_pri0;
	__le64 rx_pfc_xon2xoff_frames_pri1;
	__le64 rx_pfc_xon2xoff_frames_pri2;
	__le64 rx_pfc_xon2xoff_frames_pri3;
	__le64 rx_pfc_xon2xoff_frames_pri4;
	__le64 rx_pfc_xon2xoff_frames_pri5;
	__le64 rx_pfc_xon2xoff_frames_pri6;
	__le64 rx_pfc_xon2xoff_frames_pri7;
	__le64 rx_pfc_ena_frames_pri0;
	__le64 rx_pfc_ena_frames_pri1;
	__le64 rx_pfc_ena_frames_pri2;
	__le64 rx_pfc_ena_frames_pri3;
	__le64 rx_pfc_ena_frames_pri4;
	__le64 rx_pfc_ena_frames_pri5;
	__le64 rx_pfc_ena_frames_pri6;
	__le64 rx_pfc_ena_frames_pri7;
	__le64 rx_sch_crc_err_frames;
	__le64 rx_undrsz_frames;
	__le64 rx_frag_frames;
	__le64 rx_eee_lpi_events;
	__le64 rx_eee_lpi_duration;
	__le64 rx_llfc_physical_msgs;
	__le64 rx_llfc_logical_msgs;
	__le64 rx_llfc_msgs_with_crc_err;
	__le64 rx_hcfc_msgs;
	__le64 rx_hcfc_msgs_with_crc_err;
	__le64 rx_bytes;
	__le64 rx_runt_bytes;
	__le64 rx_runt_frames;
	__le64 rx_stat_discard;
	__le64 rx_stat_err;
};

/* hwrm_ver_get */
/* Input (24 bytes) */
struct hwrm_ver_get_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	u8 hwrm_intf_maj;
	u8 hwrm_intf_min;
	u8 hwrm_intf_upd;
	u8 unused_0[5];
};

/* Output (128 bytes) */
struct hwrm_ver_get_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	u8 hwrm_intf_maj;
	u8 hwrm_intf_min;
	u8 hwrm_intf_upd;
	u8 hwrm_intf_rsvd;
	u8 hwrm_fw_maj;
	u8 hwrm_fw_min;
	u8 hwrm_fw_bld;
	u8 hwrm_fw_rsvd;
	u8 mgmt_fw_maj;
	u8 mgmt_fw_min;
	u8 mgmt_fw_bld;
	u8 mgmt_fw_rsvd;
	u8 netctrl_fw_maj;
	u8 netctrl_fw_min;
	u8 netctrl_fw_bld;
	u8 netctrl_fw_rsvd;
	__le32 dev_caps_cfg;
	#define VER_GET_RESP_DEV_CAPS_CFG_SECURE_FW_UPD_SUPPORTED  0x1UL
	#define VER_GET_RESP_DEV_CAPS_CFG_FW_DCBX_AGENT_SUPPORTED  0x2UL
	u8 roce_fw_maj;
	u8 roce_fw_min;
	u8 roce_fw_bld;
	u8 roce_fw_rsvd;
	char hwrm_fw_name[16];
	char mgmt_fw_name[16];
	char netctrl_fw_name[16];
	__le32 reserved2[4];
	char roce_fw_name[16];
	__le16 chip_num;
	u8 chip_rev;
	u8 chip_metal;
	u8 chip_bond_id;
	u8 chip_platform_type;
	#define VER_GET_RESP_CHIP_PLATFORM_TYPE_ASIC		   0x0UL
	#define VER_GET_RESP_CHIP_PLATFORM_TYPE_FPGA		   0x1UL
	#define VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM	   0x2UL
	__le16 max_req_win_len;
	__le16 max_resp_len;
	__le16 def_req_timeout;
	u8 unused_0;
	u8 unused_1;
	u8 unused_2;
	u8 valid;
};

/* hwrm_func_reset */
/* Input (24 bytes) */
struct hwrm_func_reset_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	__le32 enables;
	#define FUNC_RESET_REQ_ENABLES_VF_ID_VALID		    0x1UL
	__le16 vf_id;
	u8 func_reset_level;
	#define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETALL	   0x0UL
	#define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETME	   0x1UL
	#define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETCHILDREN     0x2UL
	#define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF	   0x3UL
	u8 unused_0;
};

/* Output (16 bytes) */
struct hwrm_func_reset_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le32 unused_0;
	u8 unused_1;
	u8 unused_2;
	u8 unused_3;
	u8 valid;
};

/* hwrm_func_getfid */
/* Input (24 bytes) */
struct hwrm_func_getfid_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	__le32 enables;
	#define FUNC_GETFID_REQ_ENABLES_PCI_ID			    0x1UL
	__le16 pci_id;
	__le16 unused_0;
};

/* Output (16 bytes) */
struct hwrm_func_getfid_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le16 fid;
	u8 unused_0;
	u8 unused_1;
	u8 unused_2;
	u8 unused_3;
	u8 unused_4;
	u8 valid;
};

/* hwrm_func_vf_alloc */
/* Input (24 bytes) */
struct hwrm_func_vf_alloc_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	__le32 enables;
	#define FUNC_VF_ALLOC_REQ_ENABLES_FIRST_VF_ID		    0x1UL
	__le16 first_vf_id;
	__le16 num_vfs;
};

/* Output (16 bytes) */
struct hwrm_func_vf_alloc_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le16 first_vf_id;
	u8 unused_0;
	u8 unused_1;
	u8 unused_2;
	u8 unused_3;
	u8 unused_4;
	u8 valid;
};

/* hwrm_func_vf_free */
/* Input (24 bytes) */
struct hwrm_func_vf_free_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	__le32 enables;
	#define FUNC_VF_FREE_REQ_ENABLES_FIRST_VF_ID		    0x1UL
	__le16 first_vf_id;
	__le16 num_vfs;
};

/* Output (16 bytes) */
struct hwrm_func_vf_free_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le32 unused_0;
	u8 unused_1;
	u8 unused_2;
	u8 unused_3;
	u8 valid;
};

/* hwrm_func_vf_cfg */
/* Input (32 bytes) */
struct hwrm_func_vf_cfg_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	__le32 enables;
	#define FUNC_VF_CFG_REQ_ENABLES_MTU			    0x1UL
	#define FUNC_VF_CFG_REQ_ENABLES_GUEST_VLAN		    0x2UL
	#define FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR		    0x4UL
	#define FUNC_VF_CFG_REQ_ENABLES_DFLT_MAC_ADDR		    0x8UL
	__le16 mtu;
	__le16 guest_vlan;
	__le16 async_event_cr;
	u8 dflt_mac_addr[6];
};

/* Output (16 bytes) */
struct hwrm_func_vf_cfg_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le32 unused_0;
	u8 unused_1;
	u8 unused_2;
	u8 unused_3;
	u8 valid;
};

/* hwrm_func_qcaps */
/* Input (24 bytes) */
struct hwrm_func_qcaps_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	__le16 fid;
	__le16 unused_0[3];
};

/* Output (80 bytes) */
struct hwrm_func_qcaps_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le16 fid;
	__le16 port_id;
	__le32 flags;
	#define FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED	    0x1UL
	#define FUNC_QCAPS_RESP_FLAGS_GLOBAL_MSIX_AUTOMASKING      0x2UL
	#define FUNC_QCAPS_RESP_FLAGS_PTP_SUPPORTED		    0x4UL
	#define FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED	    0x8UL
	#define FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED	    0x10UL
	#define FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED       0x20UL
	#define FUNC_QCAPS_RESP_FLAGS_WOL_BMP_SUPPORTED	    0x40UL
	#define FUNC_QCAPS_RESP_FLAGS_TX_RING_RL_SUPPORTED	    0x80UL
	#define FUNC_QCAPS_RESP_FLAGS_TX_BW_CFG_SUPPORTED	    0x100UL
	#define FUNC_QCAPS_RESP_FLAGS_VF_TX_RING_RL_SUPPORTED      0x200UL
	#define FUNC_QCAPS_RESP_FLAGS_VF_BW_CFG_SUPPORTED	    0x400UL
	u8 mac_address[6];
	__le16 max_rsscos_ctx;
	__le16 max_cmpl_rings;
	__le16 max_tx_rings;
	__le16 max_rx_rings;
	__le16 max_l2_ctxs;
	__le16 max_vnics;
	__le16 first_vf_id;
	__le16 max_vfs;
	__le16 max_stat_ctx;
	__le32 max_encap_records;
	__le32 max_decap_records;
	__le32 max_tx_em_flows;
	__le32 max_tx_wm_flows;
	__le32 max_rx_em_flows;
	__le32 max_rx_wm_flows;
	__le32 max_mcast_filters;
	__le32 max_flow_id;
	__le32 max_hw_ring_grps;
	__le16 max_sp_tx_rings;
	u8 unused_0;
	u8 valid;
};

/* hwrm_func_qcfg */
/* Input (24 bytes) */
struct hwrm_func_qcfg_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	__le16 fid;
	__le16 unused_0[3];
};

/* Output (72 bytes) */
struct hwrm_func_qcfg_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le16 fid;
	__le16 port_id;
	__le16 vlan;
	__le16 flags;
	#define FUNC_QCFG_RESP_FLAGS_OOB_WOL_MAGICPKT_ENABLED      0x1UL
	#define FUNC_QCFG_RESP_FLAGS_OOB_WOL_BMP_ENABLED	    0x2UL
	#define FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED	    0x4UL
	u8 mac_address[6];
	__le16 pci_id;
	__le16 alloc_rsscos_ctx;
	__le16 alloc_cmpl_rings;
	__le16 alloc_tx_rings;
	__le16 alloc_rx_rings;
	__le16 alloc_l2_ctx;
	__le16 alloc_vnics;
	__le16 mtu;
	__le16 mru;
	__le16 stat_ctx_id;
	u8 port_partition_type;
	#define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_SPF		   0x0UL
	#define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_MPFS	   0x1UL
	#define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0	   0x2UL
	#define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5	   0x3UL
	#define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0	   0x4UL
	#define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN	   0xffUL
	u8 unused_0;
	__le16 dflt_vnic_id;
	u8 unused_1;
	u8 unused_2;
	__le32 min_bw;
	#define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_MASK		    0xfffffffUL
	#define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_SFT		    0
	#define FUNC_QCFG_RESP_MIN_BW_RSVD			    0x10000000UL
	#define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MASK	    0xe0000000UL
	#define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_SFT	    29
	#define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MBPS	   (0x0UL << 29)
	#define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
	#define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
	#define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_LAST    FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID
	__le32 max_bw;
	#define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_MASK		    0xfffffffUL
	#define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_SFT		    0
	#define FUNC_QCFG_RESP_MAX_BW_RSVD			    0x10000000UL
	#define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MASK	    0xe0000000UL
	#define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_SFT	    29
	#define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MBPS	   (0x0UL << 29)
	#define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
	#define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
	#define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_LAST    FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID
	u8 evb_mode;
	#define FUNC_QCFG_RESP_EVB_MODE_NO_EVB			   0x0UL
	#define FUNC_QCFG_RESP_EVB_MODE_VEB			   0x1UL
	#define FUNC_QCFG_RESP_EVB_MODE_VEPA			   0x2UL
	u8 unused_3;
	__le16 alloc_vfs;
	__le32 alloc_mcast_filters;
	__le32 alloc_hw_ring_grps;
	__le16 alloc_sp_tx_rings;
	u8 unused_4;
	u8 valid;
};

/* hwrm_func_cfg */
/* Input (88 bytes) */
struct hwrm_func_cfg_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	__le16 fid;
	u8 unused_0;
	u8 unused_1;
	__le32 flags;
	#define FUNC_CFG_REQ_FLAGS_PROM_MODE			    0x1UL
	#define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK		    0x2UL
	#define FUNC_CFG_REQ_FLAGS_SRC_IP_ADDR_CHECK		    0x4UL
	#define FUNC_CFG_REQ_FLAGS_VLAN_PRI_MATCH		    0x8UL
	#define FUNC_CFG_REQ_FLAGS_DFLT_PRI_NOMATCH		    0x10UL
	#define FUNC_CFG_REQ_FLAGS_DISABLE_PAUSE		    0x20UL
	#define FUNC_CFG_REQ_FLAGS_DISABLE_STP			    0x40UL
	#define FUNC_CFG_REQ_FLAGS_DISABLE_LLDP		    0x80UL
	#define FUNC_CFG_REQ_FLAGS_DISABLE_PTPV2		    0x100UL
	__le32 enables;
	#define FUNC_CFG_REQ_ENABLES_MTU			    0x1UL
	#define FUNC_CFG_REQ_ENABLES_MRU			    0x2UL
	#define FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS		    0x4UL
	#define FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS		    0x8UL
	#define FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS		    0x10UL
	#define FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS		    0x20UL
	#define FUNC_CFG_REQ_ENABLES_NUM_L2_CTXS		    0x40UL
	#define FUNC_CFG_REQ_ENABLES_NUM_VNICS			    0x80UL
	#define FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS		    0x100UL
	#define FUNC_CFG_REQ_ENABLES_DFLT_MAC_ADDR		    0x200UL
	#define FUNC_CFG_REQ_ENABLES_DFLT_VLAN			    0x400UL
	#define FUNC_CFG_REQ_ENABLES_DFLT_IP_ADDR		    0x800UL
	#define FUNC_CFG_REQ_ENABLES_MIN_BW			    0x1000UL
	#define FUNC_CFG_REQ_ENABLES_MAX_BW			    0x2000UL
	#define FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR		    0x4000UL
	#define FUNC_CFG_REQ_ENABLES_VLAN_ANTISPOOF_MODE	    0x8000UL
	#define FUNC_CFG_REQ_ENABLES_ALLOWED_VLAN_PRIS		    0x10000UL
	#define FUNC_CFG_REQ_ENABLES_EVB_MODE			    0x20000UL
	#define FUNC_CFG_REQ_ENABLES_NUM_MCAST_FILTERS		    0x40000UL
	#define FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS		    0x80000UL
	__le16 mtu;
	__le16 mru;
	__le16 num_rsscos_ctxs;
	__le16 num_cmpl_rings;
	__le16 num_tx_rings;
	__le16 num_rx_rings;
	__le16 num_l2_ctxs;
	__le16 num_vnics;
	__le16 num_stat_ctxs;
	__le16 num_hw_ring_grps;
	u8 dflt_mac_addr[6];
	__le16 dflt_vlan;
	__be32 dflt_ip_addr[4];
	__le32 min_bw;
	#define FUNC_CFG_REQ_MIN_BW_BW_VALUE_MASK		    0xfffffffUL
	#define FUNC_CFG_REQ_MIN_BW_BW_VALUE_SFT		    0
	#define FUNC_CFG_REQ_MIN_BW_RSVD			    0x10000000UL
	#define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MASK		    0xe0000000UL
	#define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_SFT		    29
	#define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MBPS		   (0x0UL << 29)
	#define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_PERCENT1_100    (0x1UL << 29)
	#define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID	   (0x7UL << 29)
	#define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_LAST    FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID
	__le32 max_bw;
	#define FUNC_CFG_REQ_MAX_BW_BW_VALUE_MASK		    0xfffffffUL
	#define FUNC_CFG_REQ_MAX_BW_BW_VALUE_SFT		    0
	#define FUNC_CFG_REQ_MAX_BW_RSVD			    0x10000000UL
	#define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MASK		    0xe0000000UL
	#define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_SFT		    29
	#define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MBPS		   (0x0UL << 29)
	#define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100    (0x1UL << 29)
	#define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID	   (0x7UL << 29)
	#define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_LAST    FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID
	__le16 async_event_cr;
	u8 vlan_antispoof_mode;
	#define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_NOCHECK	   0x0UL
	#define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN    0x1UL
	#define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_IF_VLANDNE 0x2UL
	#define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN 0x3UL
	u8 allowed_vlan_pris;
	u8 evb_mode;
	#define FUNC_CFG_REQ_EVB_MODE_NO_EVB			   0x0UL
	#define FUNC_CFG_REQ_EVB_MODE_VEB			   0x1UL
	#define FUNC_CFG_REQ_EVB_MODE_VEPA			   0x2UL
	u8 unused_2;
	__le16 num_mcast_filters;
};

/* Output (16 bytes) */
struct hwrm_func_cfg_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le32 unused_0;
	u8 unused_1;
	u8 unused_2;
	u8 unused_3;
	u8 valid;
};

/* hwrm_func_qstats */
/* Input (24 bytes) */
struct hwrm_func_qstats_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	__le16 fid;
	__le16 unused_0[3];
};

/* Output (176 bytes) */
struct hwrm_func_qstats_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le64 tx_ucast_pkts;
	__le64 tx_mcast_pkts;
	__le64 tx_bcast_pkts;
	__le64 tx_err_pkts;
	__le64 tx_drop_pkts;
	__le64 tx_ucast_bytes;
	__le64 tx_mcast_bytes;
	__le64 tx_bcast_bytes;
	__le64 rx_ucast_pkts;
	__le64 rx_mcast_pkts;
	__le64 rx_bcast_pkts;
	__le64 rx_err_pkts;
	__le64 rx_drop_pkts;
	__le64 rx_ucast_bytes;
	__le64 rx_mcast_bytes;
	__le64 rx_bcast_bytes;
	__le64 rx_agg_pkts;
	__le64 rx_agg_bytes;
	__le64 rx_agg_events;
	__le64 rx_agg_aborts;
	__le32 unused_0;
	u8 unused_1;
	u8 unused_2;
	u8 unused_3;
	u8 valid;
};

/* hwrm_func_clr_stats */
/* Input (24 bytes) */
struct hwrm_func_clr_stats_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	__le16 fid;
	__le16 unused_0[3];
};

/* Output (16 bytes) */
struct hwrm_func_clr_stats_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le32 unused_0;
	u8 unused_1;
	u8 unused_2;
	u8 unused_3;
	u8 valid;
};

/* hwrm_func_vf_resc_free */
/* Input (24 bytes) */
struct hwrm_func_vf_resc_free_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	__le16 vf_id;
	__le16 unused_0[3];
};

/* Output (16 bytes) */
struct hwrm_func_vf_resc_free_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le32 unused_0;
	u8 unused_1;
	u8 unused_2;
	u8 unused_3;
	u8 valid;
};

/* hwrm_func_vf_vnic_ids_query */
/* Input (32 bytes) */
struct hwrm_func_vf_vnic_ids_query_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	__le16 vf_id;
	u8 unused_0;
	u8 unused_1;
	__le32 max_vnic_id_cnt;
	__le64 vnic_id_tbl_addr;
};

/* Output (16 bytes) */
struct hwrm_func_vf_vnic_ids_query_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le32 vnic_id_cnt;
	u8 unused_0;
	u8 unused_1;
	u8 unused_2;
	u8 valid;
};

/* hwrm_func_drv_rgtr */
/* Input (80 bytes) */
struct hwrm_func_drv_rgtr_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	__le32 flags;
	#define FUNC_DRV_RGTR_REQ_FLAGS_FWD_ALL_MODE		    0x1UL
	#define FUNC_DRV_RGTR_REQ_FLAGS_FWD_NONE_MODE		    0x2UL
	__le32 enables;
	#define FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE		    0x1UL
	#define FUNC_DRV_RGTR_REQ_ENABLES_VER			    0x2UL
	#define FUNC_DRV_RGTR_REQ_ENABLES_TIMESTAMP		    0x4UL
	#define FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD		    0x8UL
	#define FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD	    0x10UL
	__le16 os_type;
	#define FUNC_DRV_RGTR_REQ_OS_TYPE_UNKNOWN		   0x0UL
	#define FUNC_DRV_RGTR_REQ_OS_TYPE_OTHER		   0x1UL
	#define FUNC_DRV_RGTR_REQ_OS_TYPE_MSDOS		   0xeUL
	#define FUNC_DRV_RGTR_REQ_OS_TYPE_WINDOWS		   0x12UL
	#define FUNC_DRV_RGTR_REQ_OS_TYPE_SOLARIS		   0x1dUL
	#define FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX		   0x24UL
	#define FUNC_DRV_RGTR_REQ_OS_TYPE_FREEBSD		   0x2aUL
	#define FUNC_DRV_RGTR_REQ_OS_TYPE_ESXI			   0x68UL
	#define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN864		   0x73UL
	#define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN2012R2		   0x74UL
	u8 ver_maj;
	u8 ver_min;
	u8 ver_upd;
	u8 unused_0;
	__le16 unused_1;
	__le32 timestamp;
	__le32 unused_2;
	__le32 vf_req_fwd[8];
	__le32 async_event_fwd[8];
};

/* Output (16 bytes) */
struct hwrm_func_drv_rgtr_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le32 unused_0;
	u8 unused_1;
	u8 unused_2;
	u8 unused_3;
	u8 valid;
};

/* hwrm_func_drv_unrgtr */
/* Input (24 bytes) */
struct hwrm_func_drv_unrgtr_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	__le32 flags;
	#define FUNC_DRV_UNRGTR_REQ_FLAGS_PREPARE_FOR_SHUTDOWN     0x1UL
	__le32 unused_0;
};

/* Output (16 bytes) */
struct hwrm_func_drv_unrgtr_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le32 unused_0;
	u8 unused_1;
	u8 unused_2;
	u8 unused_3;
	u8 valid;
};

/* hwrm_func_buf_rgtr */
/* Input (128 bytes) */
struct hwrm_func_buf_rgtr_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	__le32 enables;
	#define FUNC_BUF_RGTR_REQ_ENABLES_VF_ID		    0x1UL
	#define FUNC_BUF_RGTR_REQ_ENABLES_ERR_BUF_ADDR		    0x2UL
	__le16 vf_id;
	__le16 req_buf_num_pages;
	__le16 req_buf_page_size;
	#define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_16B	   0x4UL
	#define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4K		   0xcUL
	#define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_8K		   0xdUL
	#define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_64K	   0x10UL
	#define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_2M		   0x15UL
	#define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4M		   0x16UL
	#define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G		   0x1eUL
	__le16 req_buf_len;
	__le16 resp_buf_len;
	u8 unused_0;
	u8 unused_1;
	__le64 req_buf_page_addr0;
	__le64 req_buf_page_addr1;
	__le64 req_buf_page_addr2;
	__le64 req_buf_page_addr3;
	__le64 req_buf_page_addr4;
	__le64 req_buf_page_addr5;
	__le64 req_buf_page_addr6;
	__le64 req_buf_page_addr7;
	__le64 req_buf_page_addr8;
	__le64 req_buf_page_addr9;
	__le64 error_buf_addr;
	__le64 resp_buf_addr;
};

/* Output (16 bytes) */
struct hwrm_func_buf_rgtr_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le32 unused_0;
	u8 unused_1;
	u8 unused_2;
	u8 unused_3;
	u8 valid;
};

/* hwrm_func_drv_qver */
/* Input (24 bytes) */
struct hwrm_func_drv_qver_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	__le32 reserved;
	__le16 fid;
	__le16 unused_0;
};

/* Output (16 bytes) */
struct hwrm_func_drv_qver_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le16 os_type;
	#define FUNC_DRV_QVER_RESP_OS_TYPE_UNKNOWN		   0x0UL
	#define FUNC_DRV_QVER_RESP_OS_TYPE_OTHER		   0x1UL
	#define FUNC_DRV_QVER_RESP_OS_TYPE_MSDOS		   0xeUL
	#define FUNC_DRV_QVER_RESP_OS_TYPE_WINDOWS		   0x12UL
	#define FUNC_DRV_QVER_RESP_OS_TYPE_SOLARIS		   0x1dUL
	#define FUNC_DRV_QVER_RESP_OS_TYPE_LINUX		   0x24UL
	#define FUNC_DRV_QVER_RESP_OS_TYPE_FREEBSD		   0x2aUL
	#define FUNC_DRV_QVER_RESP_OS_TYPE_ESXI		   0x68UL
	#define FUNC_DRV_QVER_RESP_OS_TYPE_WIN864		   0x73UL
	#define FUNC_DRV_QVER_RESP_OS_TYPE_WIN2012R2		   0x74UL
	u8 ver_maj;
	u8 ver_min;
	u8 ver_upd;
	u8 unused_0;
	u8 unused_1;
	u8 valid;
};

/* hwrm_port_phy_cfg */
/* Input (56 bytes) */
struct hwrm_port_phy_cfg_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	__le32 flags;
	#define PORT_PHY_CFG_REQ_FLAGS_RESET_PHY		    0x1UL
	#define PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DOWN		    0x2UL
	#define PORT_PHY_CFG_REQ_FLAGS_FORCE			    0x4UL
	#define PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG		    0x8UL
	#define PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE		    0x10UL
	#define PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE		    0x20UL
	#define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE	    0x40UL
	#define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE	    0x80UL
	#define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_ENABLE	    0x100UL
	#define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE	    0x200UL
	#define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_ENABLE	    0x400UL
	#define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE	    0x800UL
	#define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE	    0x1000UL
	#define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_DISABLE	    0x2000UL
	__le32 enables;
	#define PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE		    0x1UL
	#define PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX		    0x2UL
	#define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE		    0x4UL
	#define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED	    0x8UL
	#define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK      0x10UL
	#define PORT_PHY_CFG_REQ_ENABLES_WIRESPEED		    0x20UL
	#define PORT_PHY_CFG_REQ_ENABLES_LPBK			    0x40UL
	#define PORT_PHY_CFG_REQ_ENABLES_PREEMPHASIS		    0x80UL
	#define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE		    0x100UL
	#define PORT_PHY_CFG_REQ_ENABLES_EEE_LINK_SPEED_MASK       0x200UL
	#define PORT_PHY_CFG_REQ_ENABLES_TX_LPI_TIMER		    0x400UL
	__le16 port_id;
	__le16 force_link_speed;
	#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100MB	   0x1UL
	#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB		   0xaUL
	#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2GB		   0x14UL
	#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2_5GB	   0x19UL
	#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB		   0x64UL
	#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_20GB		   0xc8UL
	#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB		   0xfaUL
	#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB		   0x190UL
	#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB		   0x1f4UL
	#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB	   0x3e8UL
	#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB		   0xffffUL
	u8 auto_mode;
	#define PORT_PHY_CFG_REQ_AUTO_MODE_NONE		   0x0UL
	#define PORT_PHY_CFG_REQ_AUTO_MODE_ALL_SPEEDS		   0x1UL
	#define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_SPEED		   0x2UL
	#define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_OR_BELOW	   0x3UL
	#define PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK		   0x4UL
	u8 auto_duplex;
	#define PORT_PHY_CFG_REQ_AUTO_DUPLEX_HALF		   0x0UL
	#define PORT_PHY_CFG_REQ_AUTO_DUPLEX_FULL		   0x1UL
	#define PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH		   0x2UL
	u8 auto_pause;
	#define PORT_PHY_CFG_REQ_AUTO_PAUSE_TX			    0x1UL
	#define PORT_PHY_CFG_REQ_AUTO_PAUSE_RX			    0x2UL
	#define PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE	    0x4UL
	u8 unused_0;
	__le16 auto_link_speed;
	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100MB		   0x1UL
	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_1GB		   0xaUL
	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2GB		   0x14UL
	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2_5GB		   0x19UL
	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10GB		   0x64UL
	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_20GB		   0xc8UL
	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_25GB		   0xfaUL
	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_40GB		   0x190UL
	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_50GB		   0x1f4UL
	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100GB		   0x3e8UL
	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB		   0xffffUL
	__le16 auto_link_speed_mask;
	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MBHD      0x1UL
	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MB	    0x2UL
	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GBHD	    0x4UL
	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GB	    0x8UL
	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2GB	    0x10UL
	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2_5GB	    0x20UL
	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10GB	    0x40UL
	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_20GB	    0x80UL
	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_25GB	    0x100UL
	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_40GB	    0x200UL
	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_50GB	    0x400UL
	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100GB	    0x800UL
	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MBHD       0x1000UL
	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MB	    0x2000UL
	u8 wirespeed;
	#define PORT_PHY_CFG_REQ_WIRESPEED_OFF			   0x0UL
	#define PORT_PHY_CFG_REQ_WIRESPEED_ON			   0x1UL
	u8 lpbk;
	#define PORT_PHY_CFG_REQ_LPBK_NONE			   0x0UL
	#define PORT_PHY_CFG_REQ_LPBK_LOCAL			   0x1UL
	#define PORT_PHY_CFG_REQ_LPBK_REMOTE			   0x2UL
	u8 force_pause;
	#define PORT_PHY_CFG_REQ_FORCE_PAUSE_TX		    0x1UL
	#define PORT_PHY_CFG_REQ_FORCE_PAUSE_RX		    0x2UL
	u8 unused_1;
	__le32 preemphasis;
	__le16 eee_link_speed_mask;
	#define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD1	    0x1UL
	#define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_100MB	    0x2UL
	#define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD2	    0x4UL
	#define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_1GB	    0x8UL
	#define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD3	    0x10UL
	#define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD4	    0x20UL
	#define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_10GB	    0x40UL
	u8 unused_2;
	u8 unused_3;
	__le32 tx_lpi_timer;
	__le32 unused_4;
	#define PORT_PHY_CFG_REQ_TX_LPI_TIMER_MASK		    0xffffffUL
	#define PORT_PHY_CFG_REQ_TX_LPI_TIMER_SFT		    0
};

/* Output (16 bytes) */
struct hwrm_port_phy_cfg_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le32 unused_0;
	u8 unused_1;
	u8 unused_2;
	u8 unused_3;
	u8 valid;
};

/* hwrm_port_phy_qcfg */
/* Input (24 bytes) */
struct hwrm_port_phy_qcfg_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	__le16 port_id;
	__le16 unused_0[3];
};

/* Output (96 bytes) */
struct hwrm_port_phy_qcfg_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	u8 link;
	#define PORT_PHY_QCFG_RESP_LINK_NO_LINK		   0x0UL
	#define PORT_PHY_QCFG_RESP_LINK_SIGNAL			   0x1UL
	#define PORT_PHY_QCFG_RESP_LINK_LINK			   0x2UL
	u8 unused_0;
	__le16 link_speed;
	#define PORT_PHY_QCFG_RESP_LINK_SPEED_100MB		   0x1UL
	#define PORT_PHY_QCFG_RESP_LINK_SPEED_1GB		   0xaUL
	#define PORT_PHY_QCFG_RESP_LINK_SPEED_2GB		   0x14UL
	#define PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB		   0x19UL
	#define PORT_PHY_QCFG_RESP_LINK_SPEED_10GB		   0x64UL
	#define PORT_PHY_QCFG_RESP_LINK_SPEED_20GB		   0xc8UL
	#define PORT_PHY_QCFG_RESP_LINK_SPEED_25GB		   0xfaUL
	#define PORT_PHY_QCFG_RESP_LINK_SPEED_40GB		   0x190UL
	#define PORT_PHY_QCFG_RESP_LINK_SPEED_50GB		   0x1f4UL
	#define PORT_PHY_QCFG_RESP_LINK_SPEED_100GB		   0x3e8UL
	#define PORT_PHY_QCFG_RESP_LINK_SPEED_10MB		   0xffffUL
	u8 duplex;
	#define PORT_PHY_QCFG_RESP_DUPLEX_HALF			   0x0UL
	#define PORT_PHY_QCFG_RESP_DUPLEX_FULL			   0x1UL
	u8 pause;
	#define PORT_PHY_QCFG_RESP_PAUSE_TX			    0x1UL
	#define PORT_PHY_QCFG_RESP_PAUSE_RX			    0x2UL
	__le16 support_speeds;
	#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MBHD	    0x1UL
	#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB	    0x2UL
	#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GBHD	    0x4UL
	#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB		    0x8UL
	#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB		    0x10UL
	#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB	    0x20UL
	#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB		    0x40UL
	#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB		    0x80UL
	#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB		    0x100UL
	#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB		    0x200UL
	#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB		    0x400UL
	#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB	    0x800UL
	#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MBHD	    0x1000UL
	#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MB		    0x2000UL
	__le16 force_link_speed;
	#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100MB	   0x1UL
	#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_1GB	   0xaUL
	#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2GB	   0x14UL
	#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2_5GB	   0x19UL
	#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10GB	   0x64UL
	#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_20GB	   0xc8UL
	#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_25GB	   0xfaUL
	#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_40GB	   0x190UL
	#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_50GB	   0x1f4UL
	#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100GB	   0x3e8UL
	#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB	   0xffffUL
	u8 auto_mode;
	#define PORT_PHY_QCFG_RESP_AUTO_MODE_NONE		   0x0UL
	#define PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS	   0x1UL
	#define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED		   0x2UL
	#define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW	   0x3UL
	#define PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK	   0x4UL
	u8 auto_pause;
	#define PORT_PHY_QCFG_RESP_AUTO_PAUSE_TX		    0x1UL
	#define PORT_PHY_QCFG_RESP_AUTO_PAUSE_RX		    0x2UL
	#define PORT_PHY_QCFG_RESP_AUTO_PAUSE_AUTONEG_PAUSE	    0x4UL
	__le16 auto_link_speed;
	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100MB	   0x1UL
	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_1GB		   0xaUL
	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2GB		   0x14UL
	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2_5GB	   0x19UL
	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10GB	   0x64UL
	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_20GB	   0xc8UL
	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_25GB	   0xfaUL
	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_40GB	   0x190UL
	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_50GB	   0x1f4UL
	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100GB	   0x3e8UL
	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB	   0xffffUL
	__le16 auto_link_speed_mask;
	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MBHD    0x1UL
	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MB      0x2UL
	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GBHD      0x4UL
	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GB	    0x8UL
	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2GB	    0x10UL
	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2_5GB      0x20UL
	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10GB       0x40UL
	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_20GB       0x80UL
	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_25GB       0x100UL
	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_40GB       0x200UL
	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_50GB       0x400UL
	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100GB      0x800UL
	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MBHD     0x1000UL
	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MB       0x2000UL
	u8 wirespeed;
	#define PORT_PHY_QCFG_RESP_WIRESPEED_OFF		   0x0UL
	#define PORT_PHY_QCFG_RESP_WIRESPEED_ON		   0x1UL
	u8 lpbk;
	#define PORT_PHY_QCFG_RESP_LPBK_NONE			   0x0UL
	#define PORT_PHY_QCFG_RESP_LPBK_LOCAL			   0x1UL
	#define PORT_PHY_QCFG_RESP_LPBK_REMOTE			   0x2UL
	u8 force_pause;
	#define PORT_PHY_QCFG_RESP_FORCE_PAUSE_TX		    0x1UL
	#define PORT_PHY_QCFG_RESP_FORCE_PAUSE_RX		    0x2UL
	u8 module_status;
	#define PORT_PHY_QCFG_RESP_MODULE_STATUS_NONE		   0x0UL
	#define PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX	   0x1UL
	#define PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG       0x2UL
	#define PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN	   0x3UL
	#define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTINSERTED      0x4UL
	#define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE    0xffUL
	__le32 preemphasis;
	u8 phy_maj;
	u8 phy_min;
	u8 phy_bld;
	u8 phy_type;
	#define PORT_PHY_QCFG_RESP_PHY_TYPE_UNKNOWN		   0x0UL
	#define PORT_PHY_QCFG_RESP_PHY_TYPE_BASECR		   0x1UL
	#define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR4		   0x2UL
	#define PORT_PHY_QCFG_RESP_PHY_TYPE_BASELR		   0x3UL
	#define PORT_PHY_QCFG_RESP_PHY_TYPE_BASESR		   0x4UL
	#define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR2		   0x5UL
	#define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKX		   0x6UL
	#define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR		   0x7UL
	#define PORT_PHY_QCFG_RESP_PHY_TYPE_BASET		   0x8UL
	#define PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE		   0x9UL
	#define PORT_PHY_QCFG_RESP_PHY_TYPE_SGMIIEXTPHY	   0xaUL
	u8 media_type;
	#define PORT_PHY_QCFG_RESP_MEDIA_TYPE_UNKNOWN		   0x0UL
	#define PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP		   0x1UL
	#define PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC		   0x2UL
	#define PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE		   0x3UL
	u8 xcvr_pkg_type;
	#define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_INTERNAL    0x1UL
	#define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL    0x2UL
	u8 eee_config_phy_addr;
	#define PORT_PHY_QCFG_RESP_PHY_ADDR_MASK		    0x1fUL
	#define PORT_PHY_QCFG_RESP_PHY_ADDR_SFT		    0
	#define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED	    0x20UL
	#define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE	    0x40UL
	#define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI	    0x80UL
	#define PORT_PHY_QCFG_RESP_EEE_CONFIG_MASK		    0xe0UL
	#define PORT_PHY_QCFG_RESP_EEE_CONFIG_SFT		    5
	u8 parallel_detect;
	#define PORT_PHY_QCFG_RESP_PARALLEL_DETECT		    0x1UL
	#define PORT_PHY_QCFG_RESP_RESERVED_MASK		    0xfeUL
	#define PORT_PHY_QCFG_RESP_RESERVED_SFT		    1
	__le16 link_partner_adv_speeds;
	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MBHD 0x1UL
	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MB   0x2UL
	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GBHD   0x4UL
	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GB     0x8UL
	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2GB     0x10UL
	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2_5GB   0x20UL
	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10GB    0x40UL
	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_20GB    0x80UL
	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_25GB    0x100UL
	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_40GB    0x200UL
	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_50GB    0x400UL
	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100GB   0x800UL
	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MBHD  0x1000UL
	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MB    0x2000UL
	u8 link_partner_adv_auto_mode;
	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_NONE 0x0UL
	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS 0x1UL
	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED 0x2UL
	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW 0x3UL
	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK 0x4UL
	u8 link_partner_adv_pause;
	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_TX       0x1UL
	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_RX       0x2UL
	__le16 adv_eee_link_speed_mask;
	#define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD1   0x1UL
	#define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_100MB   0x2UL
	#define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD2   0x4UL
	#define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_1GB     0x8UL
	#define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD3   0x10UL
	#define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD4   0x20UL
	#define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_10GB    0x40UL
	__le16 link_partner_adv_eee_link_speed_mask;
	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL
	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL
	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL
	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL
	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL
	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL
	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL
	__le32 xcvr_identifier_type_tx_lpi_timer;
	#define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK		    0xffffffUL
	#define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_SFT		    0
	#define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_MASK       0xff000000UL
	#define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFT	    24
	#define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_UNKNOWN   (0x0UL << 24)
	#define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFP       (0x3UL << 24)
	#define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP      (0xcUL << 24)
	#define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFPPLUS  (0xdUL << 24)
	#define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28    (0x11UL << 24)
	__le16 fec_cfg;
	#define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED      0x1UL
	#define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_SUPPORTED   0x2UL
	#define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED     0x4UL
	#define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_SUPPORTED  0x8UL
	#define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED    0x10UL
	#define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_SUPPORTED  0x20UL
	#define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED    0x40UL
	u8 unused_1;
	u8 unused_2;
	char phy_vendor_name[16];
	char phy_vendor_partnumber[16];
	__le32 unused_3;
	u8 unused_4;
	u8 unused_5;
	u8 unused_6;
	u8 valid;
};

/* hwrm_port_mac_cfg */
/* Input (40 bytes) */
struct hwrm_port_mac_cfg_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	__le32 flags;
	#define PORT_MAC_CFG_REQ_FLAGS_MATCH_LINK		    0x1UL
	#define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_ENABLE	    0x2UL
	#define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_ENABLE       0x4UL
	#define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_ENABLE	    0x8UL
	#define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_ENABLE    0x10UL
	#define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_DISABLE   0x20UL
	#define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_ENABLE    0x40UL
	#define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_DISABLE   0x80UL
	#define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_ENABLE		    0x100UL
	#define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_DISABLE		    0x200UL
	#define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_DISABLE	    0x400UL
	#define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_DISABLE      0x800UL
	#define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_DISABLE	    0x1000UL
	__le32 enables;
	#define PORT_MAC_CFG_REQ_ENABLES_IPG			    0x1UL
	#define PORT_MAC_CFG_REQ_ENABLES_LPBK			    0x2UL
	#define PORT_MAC_CFG_REQ_ENABLES_VLAN_PRI2COS_MAP_PRI      0x4UL
	#define PORT_MAC_CFG_REQ_ENABLES_RESERVED1		    0x8UL
	#define PORT_MAC_CFG_REQ_ENABLES_TUNNEL_PRI2COS_MAP_PRI    0x10UL
	#define PORT_MAC_CFG_REQ_ENABLES_DSCP2COS_MAP_PRI	    0x20UL
	#define PORT_MAC_CFG_REQ_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE 0x40UL
	#define PORT_MAC_CFG_REQ_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE 0x80UL
	#define PORT_MAC_CFG_REQ_ENABLES_COS_FIELD_CFG		    0x100UL
	__le16 port_id;
	u8 ipg;
	u8 lpbk;
	#define PORT_MAC_CFG_REQ_LPBK_NONE			   0x0UL
	#define PORT_MAC_CFG_REQ_LPBK_LOCAL			   0x1UL
	#define PORT_MAC_CFG_REQ_LPBK_REMOTE			   0x2UL
	u8 vlan_pri2cos_map_pri;
	u8 reserved1;
	u8 tunnel_pri2cos_map_pri;
	u8 dscp2pri_map_pri;
	__le16 rx_ts_capture_ptp_msg_type;
	__le16 tx_ts_capture_ptp_msg_type;
	u8 cos_field_cfg;
	#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_RSVD1		    0x1UL
	#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_MASK   0x6UL
	#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_SFT    1
	#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST (0x0UL << 1)
	#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER (0x1UL << 1)
	#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST (0x2UL << 1)
	#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED (0x3UL << 1)
	#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_LAST    PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED
	#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK 0x18UL
	#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT  3
	#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST (0x0UL << 3)
	#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER (0x1UL << 3)
	#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST (0x2UL << 3)
	#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED (0x3UL << 3)
	#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST    PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED
	#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_MASK    0xe0UL
	#define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_SFT     5
	u8 unused_0[3];
};

/* Output (16 bytes) */
struct hwrm_port_mac_cfg_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le16 mru;
	__le16 mtu;
	u8 ipg;
	u8 lpbk;
	#define PORT_MAC_CFG_RESP_LPBK_NONE			   0x0UL
	#define PORT_MAC_CFG_RESP_LPBK_LOCAL			   0x1UL
	#define PORT_MAC_CFG_RESP_LPBK_REMOTE			   0x2UL
	u8 unused_0;
	u8 valid;
};

/* hwrm_port_qstats */
/* Input (40 bytes) */
struct hwrm_port_qstats_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	__le16 port_id;
	u8 unused_0;
	u8 unused_1;
	u8 unused_2[3];
	u8 unused_3;
	__le64 tx_stat_host_addr;
	__le64 rx_stat_host_addr;
};

/* Output (16 bytes) */
struct hwrm_port_qstats_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le16 tx_stat_size;
	__le16 rx_stat_size;
	u8 unused_0;
	u8 unused_1;
	u8 unused_2;
	u8 valid;
};

/* hwrm_port_lpbk_qstats */
/* Input (16 bytes) */
struct hwrm_port_lpbk_qstats_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
};

/* Output (96 bytes) */
struct hwrm_port_lpbk_qstats_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le64 lpbk_ucast_frames;
	__le64 lpbk_mcast_frames;
	__le64 lpbk_bcast_frames;
	__le64 lpbk_ucast_bytes;
	__le64 lpbk_mcast_bytes;
	__le64 lpbk_bcast_bytes;
	__le64 tx_stat_discard;
	__le64 tx_stat_error;
	__le64 rx_stat_discard;
	__le64 rx_stat_error;
	__le32 unused_0;
	u8 unused_1;
	u8 unused_2;
	u8 unused_3;
	u8 valid;
};

/* hwrm_port_clr_stats */
/* Input (24 bytes) */
struct hwrm_port_clr_stats_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	__le16 port_id;
	__le16 unused_0[3];
};

/* Output (16 bytes) */
struct hwrm_port_clr_stats_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le32 unused_0;
	u8 unused_1;
	u8 unused_2;
	u8 unused_3;
	u8 valid;
};

/* hwrm_port_lpbk_clr_stats */
/* Input (16 bytes) */
struct hwrm_port_lpbk_clr_stats_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
};

/* Output (16 bytes) */
struct hwrm_port_lpbk_clr_stats_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le32 unused_0;
	u8 unused_1;
	u8 unused_2;
	u8 unused_3;
	u8 valid;
};

/* hwrm_port_blink_led */
/* Input (24 bytes) */
struct hwrm_port_blink_led_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	__le32 num_blinks;
	__le32 unused_0;
};

/* Output (16 bytes) */
struct hwrm_port_blink_led_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le32 unused_0;
	u8 unused_1;
	u8 unused_2;
	u8 unused_3;
	u8 valid;
};

/* hwrm_port_phy_qcaps */
/* Input (24 bytes) */
struct hwrm_port_phy_qcaps_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	__le16 port_id;
	__le16 unused_0[3];
};

/* Output (24 bytes) */
struct hwrm_port_phy_qcaps_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	u8 eee_supported;
	#define PORT_PHY_QCAPS_RESP_EEE_SUPPORTED		    0x1UL
	#define PORT_PHY_QCAPS_RESP_RSVD1_MASK			    0xfeUL
	#define PORT_PHY_QCAPS_RESP_RSVD1_SFT			    1
	u8 unused_0;
	__le16 supported_speeds_force_mode;
	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MBHD 0x1UL
	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MB 0x2UL
	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GBHD 0x4UL
	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GB 0x8UL
	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2GB 0x10UL
	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2_5GB 0x20UL
	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10GB 0x40UL
	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_20GB 0x80UL
	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_25GB 0x100UL
	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_40GB 0x200UL
	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_50GB 0x400UL
	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100GB 0x800UL
	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MBHD 0x1000UL
	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MB 0x2000UL
	__le16 supported_speeds_auto_mode;
	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MBHD 0x1UL
	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MB 0x2UL
	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GBHD 0x4UL
	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GB 0x8UL
	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2GB 0x10UL
	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2_5GB 0x20UL
	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10GB 0x40UL
	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_20GB 0x80UL
	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_25GB 0x100UL
	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_40GB 0x200UL
	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_50GB 0x400UL
	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100GB 0x800UL
	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MBHD 0x1000UL
	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MB 0x2000UL
	__le16 supported_speeds_eee_mode;
	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD1 0x1UL
	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_100MB 0x2UL
	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD2 0x4UL
	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_1GB  0x8UL
	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD3 0x10UL
	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD4 0x20UL
	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_10GB 0x40UL
	__le32 tx_lpi_timer_low;
	#define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK	    0xffffffUL
	#define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_SFT	    0
	#define PORT_PHY_QCAPS_RESP_RSVD2_MASK			    0xff000000UL
	#define PORT_PHY_QCAPS_RESP_RSVD2_SFT			    24
	__le32 valid_tx_lpi_timer_high;
	#define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK	    0xffffffUL
	#define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_SFT	    0
	#define PORT_PHY_QCAPS_RESP_VALID_MASK			    0xff000000UL
	#define PORT_PHY_QCAPS_RESP_VALID_SFT			    24
};

/* hwrm_port_phy_i2c_read */
/* Input (40 bytes) */
struct hwrm_port_phy_i2c_read_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	__le32 flags;
	__le32 enables;
	#define PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET	    0x1UL
	__le16 port_id;
	u8 i2c_slave_addr;
	u8 unused_0;
	__le16 page_number;
	__le16 page_offset;
	u8 data_length;
	u8 unused_1[7];
};

/* Output (80 bytes) */
struct hwrm_port_phy_i2c_read_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le32 data[16];
	__le32 unused_0;
	u8 unused_1;
	u8 unused_2;
	u8 unused_3;
	u8 valid;
};

/* hwrm_queue_qportcfg */
/* Input (24 bytes) */
struct hwrm_queue_qportcfg_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	__le32 flags;
	#define QUEUE_QPORTCFG_REQ_FLAGS_PATH			    0x1UL
	#define QUEUE_QPORTCFG_REQ_FLAGS_PATH_TX		   0x0UL
	#define QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX		   0x1UL
	#define QUEUE_QPORTCFG_REQ_FLAGS_PATH_LAST    QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX
	__le16 port_id;
	__le16 unused_0;
};

/* Output (32 bytes) */
struct hwrm_queue_qportcfg_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	u8 max_configurable_queues;
	u8 max_configurable_lossless_queues;
	u8 queue_cfg_allowed;
	u8 queue_cfg_info;
	#define QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG	    0x1UL
	u8 queue_pfcenable_cfg_allowed;
	u8 queue_pri2cos_cfg_allowed;
	u8 queue_cos2bw_cfg_allowed;
	u8 queue_id0;
	u8 queue_id0_service_profile;
	#define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY 0x0UL
	#define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS 0x1UL
	#define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN 0xffUL
	u8 queue_id1;
	u8 queue_id1_service_profile;
	#define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY 0x0UL
	#define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS 0x1UL
	#define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN 0xffUL
	u8 queue_id2;
	u8 queue_id2_service_profile;
	#define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY 0x0UL
	#define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS 0x1UL
	#define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN 0xffUL
	u8 queue_id3;
	u8 queue_id3_service_profile;
	#define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY 0x0UL
	#define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS 0x1UL
	#define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN 0xffUL
	u8 queue_id4;
	u8 queue_id4_service_profile;
	#define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY 0x0UL
	#define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS 0x1UL
	#define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN 0xffUL
	u8 queue_id5;
	u8 queue_id5_service_profile;
	#define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY 0x0UL
	#define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS 0x1UL
	#define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN 0xffUL
	u8 queue_id6;
	u8 queue_id6_service_profile;
	#define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY 0x0UL
	#define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS 0x1UL
	#define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN 0xffUL
	u8 queue_id7;
	u8 queue_id7_service_profile;
	#define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY 0x0UL
	#define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS 0x1UL
	#define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN 0xffUL
	u8 valid;
};

/* hwrm_queue_cfg */
/* Input (40 bytes) */
struct hwrm_queue_cfg_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	__le32 flags;
	#define QUEUE_CFG_REQ_FLAGS_PATH_MASK			    0x3UL
	#define QUEUE_CFG_REQ_FLAGS_PATH_SFT			    0
	#define QUEUE_CFG_REQ_FLAGS_PATH_TX			   0x0UL
	#define QUEUE_CFG_REQ_FLAGS_PATH_RX			   0x1UL
	#define QUEUE_CFG_REQ_FLAGS_PATH_BIDIR			   0x2UL
	#define QUEUE_CFG_REQ_FLAGS_PATH_LAST    QUEUE_CFG_REQ_FLAGS_PATH_BIDIR
	__le32 enables;
	#define QUEUE_CFG_REQ_ENABLES_DFLT_LEN			    0x1UL
	#define QUEUE_CFG_REQ_ENABLES_SERVICE_PROFILE		    0x2UL
	__le32 queue_id;
	__le32 dflt_len;
	u8 service_profile;
	#define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSY		   0x0UL
	#define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSLESS		   0x1UL
	#define QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN		   0xffUL
	u8 unused_0[7];
};

/* Output (16 bytes) */
struct hwrm_queue_cfg_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le32 unused_0;
	u8 unused_1;
	u8 unused_2;
	u8 unused_3;
	u8 valid;
};

/* hwrm_queue_pfcenable_cfg */
/* Input (24 bytes) */
struct hwrm_queue_pfcenable_cfg_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	__le32 flags;
	#define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI0_PFC_ENABLED     0x1UL
	#define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI1_PFC_ENABLED     0x2UL
	#define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI2_PFC_ENABLED     0x4UL
	#define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI3_PFC_ENABLED     0x8UL
	#define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI4_PFC_ENABLED     0x10UL
	#define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI5_PFC_ENABLED     0x20UL
	#define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI6_PFC_ENABLED     0x40UL
	#define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI7_PFC_ENABLED     0x80UL
	__le16 port_id;
	__le16 unused_0;
};

/* Output (16 bytes) */
struct hwrm_queue_pfcenable_cfg_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le32 unused_0;
	u8 unused_1;
	u8 unused_2;
	u8 unused_3;
	u8 valid;
};

/* hwrm_queue_pri2cos_cfg */
/* Input (40 bytes) */
struct hwrm_queue_pri2cos_cfg_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	__le32 flags;
	#define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_MASK		    0x3UL
	#define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_SFT		    0
	#define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_TX		   (0x0UL << 0)
	#define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_RX		   (0x1UL << 0)
	#define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR		   (0x2UL << 0)
	#define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_LAST    QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR
	#define QUEUE_PRI2COS_CFG_REQ_FLAGS_IVLAN		    0x4UL
	__le32 enables;
	#define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI0_COS_QUEUE_ID    0x1UL
	#define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI1_COS_QUEUE_ID    0x2UL
	#define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI2_COS_QUEUE_ID    0x4UL
	#define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI3_COS_QUEUE_ID    0x8UL
	#define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI4_COS_QUEUE_ID    0x10UL
	#define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI5_COS_QUEUE_ID    0x20UL
	#define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI6_COS_QUEUE_ID    0x40UL
	#define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI7_COS_QUEUE_ID    0x80UL
	u8 port_id;
	u8 pri0_cos_queue_id;
	u8 pri1_cos_queue_id;
	u8 pri2_cos_queue_id;
	u8 pri3_cos_queue_id;
	u8 pri4_cos_queue_id;
	u8 pri5_cos_queue_id;
	u8 pri6_cos_queue_id;
	u8 pri7_cos_queue_id;
	u8 unused_0[7];
};

/* Output (16 bytes) */
struct hwrm_queue_pri2cos_cfg_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le32 unused_0;
	u8 unused_1;
	u8 unused_2;
	u8 unused_3;
	u8 valid;
};

/* hwrm_queue_cos2bw_cfg */
/* Input (128 bytes) */
struct hwrm_queue_cos2bw_cfg_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	__le32 flags;
	__le32 enables;
	#define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID0_VALID   0x1UL
	#define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID1_VALID   0x2UL
	#define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID2_VALID   0x4UL
	#define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID3_VALID   0x8UL
	#define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID4_VALID   0x10UL
	#define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID5_VALID   0x20UL
	#define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID6_VALID   0x40UL
	#define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID7_VALID   0x80UL
	__le16 port_id;
	u8 queue_id0;
	u8 unused_0;
	__le32 queue_id0_min_bw;
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_MASK 0xfffffffUL
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_SFT 0
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_RSVD	    0x10000000UL
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT 29
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MBPS (0x0UL << 29)
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST    QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID
	__le32 queue_id0_max_bw;
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_MASK 0xfffffffUL
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_SFT 0
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_RSVD	    0x10000000UL
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT 29
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MBPS (0x0UL << 29)
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST    QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID
	u8 queue_id0_tsa_assign;
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_SP      0x0UL
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_ETS     0x1UL
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST 0xffUL
	u8 queue_id0_pri_lvl;
	u8 queue_id0_bw_weight;
	u8 queue_id1;
	__le32 queue_id1_min_bw;
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_MASK 0xfffffffUL
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_SFT 0
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_RSVD	    0x10000000UL
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT 29
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MBPS (0x0UL << 29)
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST    QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID
	__le32 queue_id1_max_bw;
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_MASK 0xfffffffUL
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_SFT 0
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_RSVD	    0x10000000UL
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT 29
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MBPS (0x0UL << 29)
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST    QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID
	u8 queue_id1_tsa_assign;
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_SP      0x0UL
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_ETS     0x1UL
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST 0x2UL
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST 0xffUL
	u8 queue_id1_pri_lvl;
	u8 queue_id1_bw_weight;
	u8 queue_id2;
	__le32 queue_id2_min_bw;
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_MASK 0xfffffffUL
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_SFT 0
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_RSVD	    0x10000000UL
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT 29
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MBPS (0x0UL << 29)
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST    QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID
	__le32 queue_id2_max_bw;
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_MASK 0xfffffffUL
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_SFT 0
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_RSVD	    0x10000000UL
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT 29
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MBPS (0x0UL << 29)
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST    QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID
	u8 queue_id2_tsa_assign;
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_SP      0x0UL
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_ETS     0x1UL
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST 0x2UL
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST 0xffUL
	u8 queue_id2_pri_lvl;
	u8 queue_id2_bw_weight;
	u8 queue_id3;
	__le32 queue_id3_min_bw;
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_MASK 0xfffffffUL
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_SFT 0
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_RSVD	    0x10000000UL
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT 29
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MBPS (0x0UL << 29)
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST    QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID
	__le32 queue_id3_max_bw;
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_MASK 0xfffffffUL
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_SFT 0
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_RSVD	    0x10000000UL
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT 29
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MBPS (0x0UL << 29)
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST    QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID
	u8 queue_id3_tsa_assign;
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_SP      0x0UL
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_ETS     0x1UL
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST 0x2UL
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST 0xffUL
	u8 queue_id3_pri_lvl;
	u8 queue_id3_bw_weight;
	u8 queue_id4;
	__le32 queue_id4_min_bw;
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_MASK 0xfffffffUL
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_SFT 0
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_RSVD	    0x10000000UL
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT 29
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MBPS (0x0UL << 29)
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST    QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID
	__le32 queue_id4_max_bw;
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_MASK 0xfffffffUL
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_SFT 0
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_RSVD	    0x10000000UL
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT 29
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MBPS (0x0UL << 29)
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST    QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID
	u8 queue_id4_tsa_assign;
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_SP      0x0UL
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_ETS     0x1UL
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST 0x2UL
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST 0xffUL
	u8 queue_id4_pri_lvl;
	u8 queue_id4_bw_weight;
	u8 queue_id5;
	__le32 queue_id5_min_bw;
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_MASK 0xfffffffUL
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_SFT 0
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_RSVD	    0x10000000UL
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT 29
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MBPS (0x0UL << 29)
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST    QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID
	__le32 queue_id5_max_bw;
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_MASK 0xfffffffUL
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_SFT 0
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_RSVD	    0x10000000UL
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT 29
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MBPS (0x0UL << 29)
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST    QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID
	u8 queue_id5_tsa_assign;
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_SP      0x0UL
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_ETS     0x1UL
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST 0x2UL
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST 0xffUL
	u8 queue_id5_pri_lvl;
	u8 queue_id5_bw_weight;
	u8 queue_id6;
	__le32 queue_id6_min_bw;
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_MASK 0xfffffffUL
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_SFT 0
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_RSVD	    0x10000000UL
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT 29
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MBPS (0x0UL << 29)
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST    QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID
	__le32 queue_id6_max_bw;
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_MASK 0xfffffffUL
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_SFT 0
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_RSVD	    0x10000000UL
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT 29
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MBPS (0x0UL << 29)
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST    QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID
	u8 queue_id6_tsa_assign;
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_SP      0x0UL
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_ETS     0x1UL
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST 0x2UL
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST 0xffUL
	u8 queue_id6_pri_lvl;
	u8 queue_id6_bw_weight;
	u8 queue_id7;
	__le32 queue_id7_min_bw;
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_MASK 0xfffffffUL
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_SFT 0
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_RSVD	    0x10000000UL
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT 29
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MBPS (0x0UL << 29)
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST    QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID
	__le32 queue_id7_max_bw;
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_MASK 0xfffffffUL
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_SFT 0
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_RSVD	    0x10000000UL
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT 29
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MBPS (0x0UL << 29)
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST    QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID
	u8 queue_id7_tsa_assign;
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_SP      0x0UL
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_ETS     0x1UL
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST 0x2UL
	#define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST 0xffUL
	u8 queue_id7_pri_lvl;
	u8 queue_id7_bw_weight;
	u8 unused_1[5];
};

/* Output (16 bytes) */
struct hwrm_queue_cos2bw_cfg_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le32 unused_0;
	u8 unused_1;
	u8 unused_2;
	u8 unused_3;
	u8 valid;
};

/* hwrm_vnic_alloc */
/* Input (24 bytes) */
struct hwrm_vnic_alloc_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	__le32 flags;
	#define VNIC_ALLOC_REQ_FLAGS_DEFAULT			    0x1UL
	__le32 unused_0;
};

/* Output (16 bytes) */
struct hwrm_vnic_alloc_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le32 vnic_id;
	u8 unused_0;
	u8 unused_1;
	u8 unused_2;
	u8 valid;
};

/* hwrm_vnic_free */
/* Input (24 bytes) */
struct hwrm_vnic_free_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	__le32 vnic_id;
	__le32 unused_0;
};

/* Output (16 bytes) */
struct hwrm_vnic_free_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le32 unused_0;
	u8 unused_1;
	u8 unused_2;
	u8 unused_3;
	u8 valid;
};

/* hwrm_vnic_cfg */
/* Input (40 bytes) */
struct hwrm_vnic_cfg_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	__le32 flags;
	#define VNIC_CFG_REQ_FLAGS_DEFAULT			    0x1UL
	#define VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE		    0x2UL
	#define VNIC_CFG_REQ_FLAGS_BD_STALL_MODE		    0x4UL
	#define VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE		    0x8UL
	#define VNIC_CFG_REQ_FLAGS_ROCE_ONLY_VNIC_MODE		    0x10UL
	#define VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE		    0x20UL
	__le32 enables;
	#define VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP		    0x1UL
	#define VNIC_CFG_REQ_ENABLES_RSS_RULE			    0x2UL
	#define VNIC_CFG_REQ_ENABLES_COS_RULE			    0x4UL
	#define VNIC_CFG_REQ_ENABLES_LB_RULE			    0x8UL
	#define VNIC_CFG_REQ_ENABLES_MRU			    0x10UL
	__le16 vnic_id;
	__le16 dflt_ring_grp;
	__le16 rss_rule;
	__le16 cos_rule;
	__le16 lb_rule;
	__le16 mru;
	__le32 unused_0;
};

/* Output (16 bytes) */
struct hwrm_vnic_cfg_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le32 unused_0;
	u8 unused_1;
	u8 unused_2;
	u8 unused_3;
	u8 valid;
};

/* hwrm_vnic_tpa_cfg */
/* Input (40 bytes) */
struct hwrm_vnic_tpa_cfg_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	__le32 flags;
	#define VNIC_TPA_CFG_REQ_FLAGS_TPA			    0x1UL
	#define VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA		    0x2UL
	#define VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE		    0x4UL
	#define VNIC_TPA_CFG_REQ_FLAGS_GRO			    0x8UL
	#define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN		    0x10UL
	#define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ       0x20UL
	#define VNIC_TPA_CFG_REQ_FLAGS_GRO_IPID_CHECK		    0x40UL
	#define VNIC_TPA_CFG_REQ_FLAGS_GRO_TTL_CHECK		    0x80UL
	__le32 enables;
	#define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS		    0x1UL
	#define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS		    0x2UL
	#define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_TIMER		    0x4UL
	#define VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN		    0x8UL
	__le16 vnic_id;
	__le16 max_agg_segs;
	#define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_1		   0x0UL
	#define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_2		   0x1UL
	#define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_4		   0x2UL
	#define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_8		   0x3UL
	#define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX		   0x1fUL
	__le16 max_aggs;
	#define VNIC_TPA_CFG_REQ_MAX_AGGS_1			   0x0UL
	#define VNIC_TPA_CFG_REQ_MAX_AGGS_2			   0x1UL
	#define VNIC_TPA_CFG_REQ_MAX_AGGS_4			   0x2UL
	#define VNIC_TPA_CFG_REQ_MAX_AGGS_8			   0x3UL
	#define VNIC_TPA_CFG_REQ_MAX_AGGS_16			   0x4UL
	#define VNIC_TPA_CFG_REQ_MAX_AGGS_MAX			   0x7UL
	u8 unused_0;
	u8 unused_1;
	__le32 max_agg_timer;
	__le32 min_agg_len;
};

/* Output (16 bytes) */
struct hwrm_vnic_tpa_cfg_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le32 unused_0;
	u8 unused_1;
	u8 unused_2;
	u8 unused_3;
	u8 valid;
};

/* hwrm_vnic_rss_cfg */
/* Input (48 bytes) */
struct hwrm_vnic_rss_cfg_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	__le32 hash_type;
	#define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4		    0x1UL
	#define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4		    0x2UL
	#define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4		    0x4UL
	#define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6		    0x8UL
	#define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6		    0x10UL
	#define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6		    0x20UL
	__le32 unused_0;
	__le64 ring_grp_tbl_addr;
	__le64 hash_key_tbl_addr;
	__le16 rss_ctx_idx;
	__le16 unused_1[3];
};

/* Output (16 bytes) */
struct hwrm_vnic_rss_cfg_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le32 unused_0;
	u8 unused_1;
	u8 unused_2;
	u8 unused_3;
	u8 valid;
};

/* hwrm_vnic_plcmodes_cfg */
/* Input (40 bytes) */
struct hwrm_vnic_plcmodes_cfg_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	__le32 flags;
	#define VNIC_PLCMODES_CFG_REQ_FLAGS_REGULAR_PLACEMENT      0x1UL
	#define VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT	    0x2UL
	#define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4		    0x4UL
	#define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6		    0x8UL
	#define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_FCOE		    0x10UL
	#define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_ROCE		    0x20UL
	__le32 enables;
	#define VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID   0x1UL
	#define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_OFFSET_VALID     0x2UL
	#define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID  0x4UL
	__le32 vnic_id;
	__le16 jumbo_thresh;
	__le16 hds_offset;
	__le16 hds_threshold;
	__le16 unused_0[3];
};

/* Output (16 bytes) */
struct hwrm_vnic_plcmodes_cfg_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le32 unused_0;
	u8 unused_1;
	u8 unused_2;
	u8 unused_3;
	u8 valid;
};

/* hwrm_vnic_rss_cos_lb_ctx_alloc */
/* Input (16 bytes) */
struct hwrm_vnic_rss_cos_lb_ctx_alloc_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
};

/* Output (16 bytes) */
struct hwrm_vnic_rss_cos_lb_ctx_alloc_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le16 rss_cos_lb_ctx_id;
	u8 unused_0;
	u8 unused_1;
	u8 unused_2;
	u8 unused_3;
	u8 unused_4;
	u8 valid;
};

/* hwrm_vnic_rss_cos_lb_ctx_free */
/* Input (24 bytes) */
struct hwrm_vnic_rss_cos_lb_ctx_free_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	__le16 rss_cos_lb_ctx_id;
	__le16 unused_0[3];
};

/* Output (16 bytes) */
struct hwrm_vnic_rss_cos_lb_ctx_free_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le32 unused_0;
	u8 unused_1;
	u8 unused_2;
	u8 unused_3;
	u8 valid;
};

/* hwrm_ring_alloc */
/* Input (80 bytes) */
struct hwrm_ring_alloc_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	__le32 enables;
	#define RING_ALLOC_REQ_ENABLES_RESERVED1		    0x1UL
	#define RING_ALLOC_REQ_ENABLES_RING_ARB_CFG		    0x2UL
	#define RING_ALLOC_REQ_ENABLES_RESERVED3		    0x4UL
	#define RING_ALLOC_REQ_ENABLES_STAT_CTX_ID_VALID	    0x8UL
	#define RING_ALLOC_REQ_ENABLES_RESERVED4		    0x10UL
	#define RING_ALLOC_REQ_ENABLES_MAX_BW_VALID		    0x20UL
	u8 ring_type;
	#define RING_ALLOC_REQ_RING_TYPE_CMPL			   0x0UL
	#define RING_ALLOC_REQ_RING_TYPE_TX			   0x1UL
	#define RING_ALLOC_REQ_RING_TYPE_RX			   0x2UL
	u8 unused_0;
	__le16 unused_1;
	__le64 page_tbl_addr;
	__le32 fbo;
	u8 page_size;
	u8 page_tbl_depth;
	u8 unused_2;
	u8 unused_3;
	__le32 length;
	__le16 logical_id;
	__le16 cmpl_ring_id;
	__le16 queue_id;
	u8 unused_4;
	u8 unused_5;
	__le32 reserved1;
	__le16 ring_arb_cfg;
	#define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_MASK	    0xfUL
	#define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SFT	    0
	#define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SP	   (0x1UL << 0)
	#define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ	   (0x2UL << 0)
	#define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_LAST    RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ
	#define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_MASK		    0xf0UL
	#define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_SFT		    4
	#define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_MASK  0xff00UL
	#define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_SFT   8
	u8 unused_6;
	u8 unused_7;
	__le32 reserved3;
	__le32 stat_ctx_id;
	__le32 reserved4;
	__le32 max_bw;
	#define RING_ALLOC_REQ_MAX_BW_BW_VALUE_MASK		    0xfffffffUL
	#define RING_ALLOC_REQ_MAX_BW_BW_VALUE_SFT		    0
	#define RING_ALLOC_REQ_MAX_BW_RSVD			    0x10000000UL
	#define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MASK	    0xe0000000UL
	#define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_SFT	    29
	#define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MBPS	   (0x0UL << 29)
	#define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
	#define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
	#define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_LAST    RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID
	u8 int_mode;
	#define RING_ALLOC_REQ_INT_MODE_LEGACY			   0x0UL
	#define RING_ALLOC_REQ_INT_MODE_RSVD			   0x1UL
	#define RING_ALLOC_REQ_INT_MODE_MSIX			   0x2UL
	#define RING_ALLOC_REQ_INT_MODE_POLL			   0x3UL
	u8 unused_8[3];
};

/* Output (16 bytes) */
struct hwrm_ring_alloc_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le16 ring_id;
	__le16 logical_ring_id;
	u8 unused_0;
	u8 unused_1;
	u8 unused_2;
	u8 valid;
};

/* hwrm_ring_free */
/* Input (24 bytes) */
struct hwrm_ring_free_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	u8 ring_type;
	#define RING_FREE_REQ_RING_TYPE_CMPL			   0x0UL
	#define RING_FREE_REQ_RING_TYPE_TX			   0x1UL
	#define RING_FREE_REQ_RING_TYPE_RX			   0x2UL
	u8 unused_0;
	__le16 ring_id;
	__le32 unused_1;
};

/* Output (16 bytes) */
struct hwrm_ring_free_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le32 unused_0;
	u8 unused_1;
	u8 unused_2;
	u8 unused_3;
	u8 valid;
};

/* hwrm_ring_cmpl_ring_qaggint_params */
/* Input (24 bytes) */
struct hwrm_ring_cmpl_ring_qaggint_params_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	__le16 ring_id;
	__le16 unused_0[3];
};

/* Output (32 bytes) */
struct hwrm_ring_cmpl_ring_qaggint_params_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le16 flags;
	#define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_TIMER_RESET 0x1UL
	#define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_RING_IDLE 0x2UL
	__le16 num_cmpl_dma_aggr;
	__le16 num_cmpl_dma_aggr_during_int;
	__le16 cmpl_aggr_dma_tmr;
	__le16 cmpl_aggr_dma_tmr_during_int;
	__le16 int_lat_tmr_min;
	__le16 int_lat_tmr_max;
	__le16 num_cmpl_aggr_int;
	__le32 unused_0;
	u8 unused_1;
	u8 unused_2;
	u8 unused_3;
	u8 valid;
};

/* hwrm_ring_cmpl_ring_cfg_aggint_params */
/* Input (40 bytes) */
struct hwrm_ring_cmpl_ring_cfg_aggint_params_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	__le16 ring_id;
	__le16 flags;
	#define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET 0x1UL
	#define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE 0x2UL
	__le16 num_cmpl_dma_aggr;
	__le16 num_cmpl_dma_aggr_during_int;
	__le16 cmpl_aggr_dma_tmr;
	__le16 cmpl_aggr_dma_tmr_during_int;
	__le16 int_lat_tmr_min;
	__le16 int_lat_tmr_max;
	__le16 num_cmpl_aggr_int;
	__le16 unused_0[3];
};

/* Output (16 bytes) */
struct hwrm_ring_cmpl_ring_cfg_aggint_params_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le32 unused_0;
	u8 unused_1;
	u8 unused_2;
	u8 unused_3;
	u8 valid;
};

/* hwrm_ring_reset */
/* Input (24 bytes) */
struct hwrm_ring_reset_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	u8 ring_type;
	#define RING_RESET_REQ_RING_TYPE_CMPL			   0x0UL
	#define RING_RESET_REQ_RING_TYPE_TX			   0x1UL
	#define RING_RESET_REQ_RING_TYPE_RX			   0x2UL
	u8 unused_0;
	__le16 ring_id;
	__le32 unused_1;
};

/* Output (16 bytes) */
struct hwrm_ring_reset_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le32 unused_0;
	u8 unused_1;
	u8 unused_2;
	u8 unused_3;
	u8 valid;
};

/* hwrm_ring_grp_alloc */
/* Input (24 bytes) */
struct hwrm_ring_grp_alloc_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	__le16 cr;
	__le16 rr;
	__le16 ar;
	__le16 sc;
};

/* Output (16 bytes) */
struct hwrm_ring_grp_alloc_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le32 ring_group_id;
	u8 unused_0;
	u8 unused_1;
	u8 unused_2;
	u8 valid;
};

/* hwrm_ring_grp_free */
/* Input (24 bytes) */
struct hwrm_ring_grp_free_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	__le32 ring_group_id;
	__le32 unused_0;
};

/* Output (16 bytes) */
struct hwrm_ring_grp_free_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le32 unused_0;
	u8 unused_1;
	u8 unused_2;
	u8 unused_3;
	u8 valid;
};

/* hwrm_cfa_l2_filter_alloc */
/* Input (96 bytes) */
struct hwrm_cfa_l2_filter_alloc_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	__le32 flags;
	#define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH		    0x1UL
	#define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_TX		   (0x0UL << 0)
	#define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX		   (0x1UL << 0)
	#define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_LAST    CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX
	#define CFA_L2_FILTER_ALLOC_REQ_FLAGS_LOOPBACK		    0x2UL
	#define CFA_L2_FILTER_ALLOC_REQ_FLAGS_DROP		    0x4UL
	#define CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST	    0x8UL
	__le32 enables;
	#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR	    0x1UL
	#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK       0x2UL
	#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN	    0x4UL
	#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN_MASK      0x8UL
	#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN	    0x10UL
	#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN_MASK      0x20UL
	#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR	    0x40UL
	#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR_MASK     0x80UL
	#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN	    0x100UL
	#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN_MASK    0x200UL
	#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN	    0x400UL
	#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN_MASK    0x800UL
	#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_TYPE	    0x1000UL
	#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_ID		    0x2000UL
	#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE	    0x4000UL
	#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID		    0x8000UL
	#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID     0x10000UL
	u8 l2_addr[6];
	u8 unused_0;
	u8 unused_1;
	u8 l2_addr_mask[6];
	__le16 l2_ovlan;
	__le16 l2_ovlan_mask;
	__le16 l2_ivlan;
	__le16 l2_ivlan_mask;
	u8 unused_2;
	u8 unused_3;
	u8 t_l2_addr[6];
	u8 unused_4;
	u8 unused_5;
	u8 t_l2_addr_mask[6];
	__le16 t_l2_ovlan;
	__le16 t_l2_ovlan_mask;
	__le16 t_l2_ivlan;
	__le16 t_l2_ivlan_mask;
	u8 src_type;
	#define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_NPORT		   0x0UL
	#define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_PF		   0x1UL
	#define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VF		   0x2UL
	#define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VNIC		   0x3UL
	#define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_KONG		   0x4UL
	#define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_APE		   0x5UL
	#define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_BONO		   0x6UL
	#define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG		   0x7UL
	u8 unused_6;
	__le32 src_id;
	u8 tunnel_type;
	#define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL     0x0UL
	#define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN	   0x1UL
	#define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE	   0x2UL
	#define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE	   0x3UL
	#define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP	   0x4UL
	#define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE	   0x5UL
	#define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS	   0x6UL
	#define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT	   0x7UL
	#define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE	   0x8UL
	#define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL     0xffUL
	u8 unused_7;
	__le16 dst_id;
	__le16 mirror_vnic_id;
	u8 pri_hint;
	#define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER	   0x0UL
	#define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_ABOVE_FILTER     0x1UL
	#define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_BELOW_FILTER     0x2UL
	#define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MAX		   0x3UL
	#define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN		   0x4UL
	u8 unused_8;
	__le32 unused_9;
	__le64 l2_filter_id_hint;
};

/* Output (24 bytes) */
struct hwrm_cfa_l2_filter_alloc_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le64 l2_filter_id;
	__le32 flow_id;
	u8 unused_0;
	u8 unused_1;
	u8 unused_2;
	u8 valid;
};

/* hwrm_cfa_l2_filter_free */
/* Input (24 bytes) */
struct hwrm_cfa_l2_filter_free_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	__le64 l2_filter_id;
};

/* Output (16 bytes) */
struct hwrm_cfa_l2_filter_free_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le32 unused_0;
	u8 unused_1;
	u8 unused_2;
	u8 unused_3;
	u8 valid;
};

/* hwrm_cfa_l2_filter_cfg */
/* Input (40 bytes) */
struct hwrm_cfa_l2_filter_cfg_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	__le32 flags;
	#define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH		    0x1UL
	#define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_TX		   (0x0UL << 0)
	#define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX		   (0x1UL << 0)
	#define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_LAST    CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX
	#define CFA_L2_FILTER_CFG_REQ_FLAGS_DROP		    0x2UL
	__le32 enables;
	#define CFA_L2_FILTER_CFG_REQ_ENABLES_DST_ID		    0x1UL
	#define CFA_L2_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID   0x2UL
	__le64 l2_filter_id;
	__le32 dst_id;
	__le32 new_mirror_vnic_id;
};

/* Output (16 bytes) */
struct hwrm_cfa_l2_filter_cfg_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le32 unused_0;
	u8 unused_1;
	u8 unused_2;
	u8 unused_3;
	u8 valid;
};

/* hwrm_cfa_l2_set_rx_mask */
/* Input (56 bytes) */
struct hwrm_cfa_l2_set_rx_mask_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	__le32 vnic_id;
	__le32 mask;
	#define CFA_L2_SET_RX_MASK_REQ_MASK_RESERVED		    0x1UL
	#define CFA_L2_SET_RX_MASK_REQ_MASK_MCAST		    0x2UL
	#define CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST		    0x4UL
	#define CFA_L2_SET_RX_MASK_REQ_MASK_BCAST		    0x8UL
	#define CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS	    0x10UL
	#define CFA_L2_SET_RX_MASK_REQ_MASK_OUTERMOST		    0x20UL
	#define CFA_L2_SET_RX_MASK_REQ_MASK_VLANONLY		    0x40UL
	#define CFA_L2_SET_RX_MASK_REQ_MASK_VLAN_NONVLAN	    0x80UL
	#define CFA_L2_SET_RX_MASK_REQ_MASK_ANYVLAN_NONVLAN	    0x100UL
	__le64 mc_tbl_addr;
	__le32 num_mc_entries;
	__le32 unused_0;
	__le64 vlan_tag_tbl_addr;
	__le32 num_vlan_tags;
	__le32 unused_1;
};

/* Output (16 bytes) */
struct hwrm_cfa_l2_set_rx_mask_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le32 unused_0;
	u8 unused_1;
	u8 unused_2;
	u8 unused_3;
	u8 valid;
};

/* hwrm_cfa_tunnel_filter_alloc */
/* Input (88 bytes) */
struct hwrm_cfa_tunnel_filter_alloc_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	__le32 flags;
	#define CFA_TUNNEL_FILTER_ALLOC_REQ_FLAGS_LOOPBACK	    0x1UL
	__le32 enables;
	#define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID   0x1UL
	#define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_ADDR	    0x2UL
	#define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN       0x4UL
	#define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR	    0x8UL
	#define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR_TYPE   0x10UL
	#define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR_TYPE 0x20UL
	#define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR      0x40UL
	#define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE    0x80UL
	#define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_VNI	    0x100UL
	#define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_DST_VNIC_ID    0x200UL
	#define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x400UL
	__le64 l2_filter_id;
	u8 l2_addr[6];
	__le16 l2_ivlan;
	__le32 l3_addr[4];
	__le32 t_l3_addr[4];
	u8 l3_addr_type;
	u8 t_l3_addr_type;
	u8 tunnel_type;
	#define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL
	#define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN     0x1UL
	#define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE     0x2UL
	#define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE     0x3UL
	#define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP      0x4UL
	#define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE    0x5UL
	#define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS      0x6UL
	#define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT       0x7UL
	#define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE     0x8UL
	#define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL
	u8 unused_0;
	__le32 vni;
	__le32 dst_vnic_id;
	__le32 mirror_vnic_id;
};

/* Output (24 bytes) */
struct hwrm_cfa_tunnel_filter_alloc_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le64 tunnel_filter_id;
	__le32 flow_id;
	u8 unused_0;
	u8 unused_1;
	u8 unused_2;
	u8 valid;
};

/* hwrm_cfa_tunnel_filter_free */
/* Input (24 bytes) */
struct hwrm_cfa_tunnel_filter_free_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	__le64 tunnel_filter_id;
};

/* Output (16 bytes) */
struct hwrm_cfa_tunnel_filter_free_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le32 unused_0;
	u8 unused_1;
	u8 unused_2;
	u8 unused_3;
	u8 valid;
};

/* hwrm_cfa_encap_record_alloc */
/* Input (32 bytes) */
struct hwrm_cfa_encap_record_alloc_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	__le32 flags;
	#define CFA_ENCAP_RECORD_ALLOC_REQ_FLAGS_LOOPBACK	    0x1UL
	u8 encap_type;
	#define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN       0x1UL
	#define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_NVGRE       0x2UL
	#define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2GRE       0x3UL
	#define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPIP	   0x4UL
	#define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_GENEVE      0x5UL
	#define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_MPLS	   0x6UL
	#define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VLAN	   0x7UL
	#define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE       0x8UL
	u8 unused_0;
	__le16 unused_1;
	__le32 encap_data[16];
};

/* Output (16 bytes) */
struct hwrm_cfa_encap_record_alloc_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le32 encap_record_id;
	u8 unused_0;
	u8 unused_1;
	u8 unused_2;
	u8 valid;
};

/* hwrm_cfa_encap_record_free */
/* Input (24 bytes) */
struct hwrm_cfa_encap_record_free_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	__le32 encap_record_id;
	__le32 unused_0;
};

/* Output (16 bytes) */
struct hwrm_cfa_encap_record_free_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le32 unused_0;
	u8 unused_1;
	u8 unused_2;
	u8 unused_3;
	u8 valid;
};

/* hwrm_cfa_ntuple_filter_alloc */
/* Input (128 bytes) */
struct hwrm_cfa_ntuple_filter_alloc_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	__le32 flags;
	#define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_LOOPBACK	    0x1UL
	#define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DROP		    0x2UL
	__le32 enables;
	#define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID   0x1UL
	#define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE      0x2UL
	#define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE    0x4UL
	#define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR    0x8UL
	#define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE    0x10UL
	#define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR     0x20UL
	#define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK 0x40UL
	#define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR     0x80UL
	#define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK 0x100UL
	#define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL    0x200UL
	#define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT       0x400UL
	#define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK  0x800UL
	#define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT       0x1000UL
	#define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK  0x2000UL
	#define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_PRI_HINT       0x4000UL
	#define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_NTUPLE_FILTER_ID 0x8000UL
	#define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID	    0x10000UL
	#define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x20000UL
	#define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR    0x40000UL
	__le64 l2_filter_id;
	u8 src_macaddr[6];
	__be16 ethertype;
	u8 ip_addr_type;
	#define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN  0x0UL
	#define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4     0x4UL
	#define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6     0x6UL
	u8 ip_protocol;
	#define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN   0x0UL
	#define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP       0x6UL
	#define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP       0x11UL
	__le16 dst_id;
	__le16 mirror_vnic_id;
	u8 tunnel_type;
	#define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL
	#define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN     0x1UL
	#define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE     0x2UL
	#define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE     0x3UL
	#define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP      0x4UL
	#define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE    0x5UL
	#define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS      0x6UL
	#define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT       0x7UL
	#define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE     0x8UL
	#define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL
	u8 pri_hint;
	#define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER    0x0UL
	#define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_ABOVE	   0x1UL
	#define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_BELOW	   0x2UL
	#define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_HIGHEST      0x3UL
	#define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LOWEST       0x4UL
	__be32 src_ipaddr[4];
	__be32 src_ipaddr_mask[4];
	__be32 dst_ipaddr[4];
	__be32 dst_ipaddr_mask[4];
	__be16 src_port;
	__be16 src_port_mask;
	__be16 dst_port;
	__be16 dst_port_mask;
	__le64 ntuple_filter_id_hint;
};

/* Output (24 bytes) */
struct hwrm_cfa_ntuple_filter_alloc_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le64 ntuple_filter_id;
	__le32 flow_id;
	u8 unused_0;
	u8 unused_1;
	u8 unused_2;
	u8 valid;
};

/* hwrm_cfa_ntuple_filter_free */
/* Input (24 bytes) */
struct hwrm_cfa_ntuple_filter_free_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	__le64 ntuple_filter_id;
};

/* Output (16 bytes) */
struct hwrm_cfa_ntuple_filter_free_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le32 unused_0;
	u8 unused_1;
	u8 unused_2;
	u8 unused_3;
	u8 valid;
};

/* hwrm_cfa_ntuple_filter_cfg */
/* Input (40 bytes) */
struct hwrm_cfa_ntuple_filter_cfg_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	__le32 enables;
	#define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_DST_ID       0x1UL
	#define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL
	__le32 unused_0;
	__le64 ntuple_filter_id;
	__le32 new_dst_id;
	__le32 new_mirror_vnic_id;
};

/* Output (16 bytes) */
struct hwrm_cfa_ntuple_filter_cfg_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le32 unused_0;
	u8 unused_1;
	u8 unused_2;
	u8 unused_3;
	u8 valid;
};

/* hwrm_tunnel_dst_port_query */
/* Input (24 bytes) */
struct hwrm_tunnel_dst_port_query_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	u8 tunnel_type;
	#define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN       0x1UL
	#define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_GENEVE      0x5UL
	u8 unused_0[7];
};

/* Output (16 bytes) */
struct hwrm_tunnel_dst_port_query_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le16 tunnel_dst_port_id;
	__be16 tunnel_dst_port_val;
	u8 unused_0;
	u8 unused_1;
	u8 unused_2;
	u8 valid;
};

/* hwrm_tunnel_dst_port_alloc */
/* Input (24 bytes) */
struct hwrm_tunnel_dst_port_alloc_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	u8 tunnel_type;
	#define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN       0x1UL
	#define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE      0x5UL
	u8 unused_0;
	__be16 tunnel_dst_port_val;
	__le32 unused_1;
};

/* Output (16 bytes) */
struct hwrm_tunnel_dst_port_alloc_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le16 tunnel_dst_port_id;
	u8 unused_0;
	u8 unused_1;
	u8 unused_2;
	u8 unused_3;
	u8 unused_4;
	u8 valid;
};

/* hwrm_tunnel_dst_port_free */
/* Input (24 bytes) */
struct hwrm_tunnel_dst_port_free_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	u8 tunnel_type;
	#define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN	   0x1UL
	#define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE       0x5UL
	u8 unused_0;
	__le16 tunnel_dst_port_id;
	__le32 unused_1;
};

/* Output (16 bytes) */
struct hwrm_tunnel_dst_port_free_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le32 unused_0;
	u8 unused_1;
	u8 unused_2;
	u8 unused_3;
	u8 valid;
};

/* hwrm_stat_ctx_alloc */
/* Input (32 bytes) */
struct hwrm_stat_ctx_alloc_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	__le64 stats_dma_addr;
	__le32 update_period_ms;
	__le32 unused_0;
};

/* Output (16 bytes) */
struct hwrm_stat_ctx_alloc_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le32 stat_ctx_id;
	u8 unused_0;
	u8 unused_1;
	u8 unused_2;
	u8 valid;
};

/* hwrm_stat_ctx_free */
/* Input (24 bytes) */
struct hwrm_stat_ctx_free_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	__le32 stat_ctx_id;
	__le32 unused_0;
};

/* Output (16 bytes) */
struct hwrm_stat_ctx_free_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le32 stat_ctx_id;
	u8 unused_0;
	u8 unused_1;
	u8 unused_2;
	u8 valid;
};

/* hwrm_stat_ctx_query */
/* Input (24 bytes) */
struct hwrm_stat_ctx_query_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	__le32 stat_ctx_id;
	__le32 unused_0;
};

/* Output (176 bytes) */
struct hwrm_stat_ctx_query_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le64 tx_ucast_pkts;
	__le64 tx_mcast_pkts;
	__le64 tx_bcast_pkts;
	__le64 tx_err_pkts;
	__le64 tx_drop_pkts;
	__le64 tx_ucast_bytes;
	__le64 tx_mcast_bytes;
	__le64 tx_bcast_bytes;
	__le64 rx_ucast_pkts;
	__le64 rx_mcast_pkts;
	__le64 rx_bcast_pkts;
	__le64 rx_err_pkts;
	__le64 rx_drop_pkts;
	__le64 rx_ucast_bytes;
	__le64 rx_mcast_bytes;
	__le64 rx_bcast_bytes;
	__le64 rx_agg_pkts;
	__le64 rx_agg_bytes;
	__le64 rx_agg_events;
	__le64 rx_agg_aborts;
	__le32 unused_0;
	u8 unused_1;
	u8 unused_2;
	u8 unused_3;
	u8 valid;
};

/* hwrm_stat_ctx_clr_stats */
/* Input (24 bytes) */
struct hwrm_stat_ctx_clr_stats_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	__le32 stat_ctx_id;
	__le32 unused_0;
};

/* Output (16 bytes) */
struct hwrm_stat_ctx_clr_stats_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le32 unused_0;
	u8 unused_1;
	u8 unused_2;
	u8 unused_3;
	u8 valid;
};

/* hwrm_fw_reset */
/* Input (24 bytes) */
struct hwrm_fw_reset_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	u8 embedded_proc_type;
	#define FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT		   0x0UL
	#define FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT		   0x1UL
	#define FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL	   0x2UL
	#define FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE		   0x3UL
	#define FW_RESET_REQ_EMBEDDED_PROC_TYPE_RSVD		   0x4UL
	u8 selfrst_status;
	#define FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE	   0x0UL
	#define FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP	   0x1UL
	#define FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST	   0x2UL
	__le16 unused_0[3];
};

/* Output (16 bytes) */
struct hwrm_fw_reset_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	u8 selfrst_status;
	#define FW_RESET_RESP_SELFRST_STATUS_SELFRSTNONE	   0x0UL
	#define FW_RESET_RESP_SELFRST_STATUS_SELFRSTASAP	   0x1UL
	#define FW_RESET_RESP_SELFRST_STATUS_SELFRSTPCIERST       0x2UL
	u8 unused_0;
	__le16 unused_1;
	u8 unused_2;
	u8 unused_3;
	u8 unused_4;
	u8 valid;
};

/* hwrm_fw_qstatus */
/* Input (24 bytes) */
struct hwrm_fw_qstatus_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	u8 embedded_proc_type;
	#define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_BOOT		   0x0UL
	#define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_MGMT		   0x1UL
	#define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_NETCTRL	   0x2UL
	#define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_ROCE		   0x3UL
	#define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_RSVD		   0x4UL
	u8 unused_0[7];
};

/* Output (16 bytes) */
struct hwrm_fw_qstatus_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	u8 selfrst_status;
	#define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTNONE	   0x0UL
	#define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTASAP	   0x1UL
	#define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPCIERST     0x2UL
	u8 unused_0;
	__le16 unused_1;
	u8 unused_2;
	u8 unused_3;
	u8 unused_4;
	u8 valid;
};

/* hwrm_fw_set_time */
/* Input (32 bytes) */
struct hwrm_fw_set_time_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	__le16 year;
	#define FW_SET_TIME_REQ_YEAR_UNKNOWN			   0x0UL
	u8 month;
	u8 day;
	u8 hour;
	u8 minute;
	u8 second;
	u8 unused_0;
	__le16 millisecond;
	__le16 zone;
	#define FW_SET_TIME_REQ_ZONE_UTC			   0x0UL
	#define FW_SET_TIME_REQ_ZONE_UNKNOWN			   0xffffUL
	__le32 unused_1;
};

/* Output (16 bytes) */
struct hwrm_fw_set_time_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le32 unused_0;
	u8 unused_1;
	u8 unused_2;
	u8 unused_3;
	u8 valid;
};

/* hwrm_exec_fwd_resp */
/* Input (128 bytes) */
struct hwrm_exec_fwd_resp_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	__le32 encap_request[26];
	__le16 encap_resp_target_id;
	__le16 unused_0[3];
};

/* Output (16 bytes) */
struct hwrm_exec_fwd_resp_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le32 unused_0;
	u8 unused_1;
	u8 unused_2;
	u8 unused_3;
	u8 valid;
};

/* hwrm_reject_fwd_resp */
/* Input (128 bytes) */
struct hwrm_reject_fwd_resp_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	__le32 encap_request[26];
	__le16 encap_resp_target_id;
	__le16 unused_0[3];
};

/* Output (16 bytes) */
struct hwrm_reject_fwd_resp_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le32 unused_0;
	u8 unused_1;
	u8 unused_2;
	u8 unused_3;
	u8 valid;
};

/* hwrm_fwd_resp */
/* Input (40 bytes) */
struct hwrm_fwd_resp_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	__le16 encap_resp_target_id;
	__le16 encap_resp_cmpl_ring;
	__le16 encap_resp_len;
	u8 unused_0;
	u8 unused_1;
	__le64 encap_resp_addr;
	__le32 encap_resp[24];
};

/* Output (16 bytes) */
struct hwrm_fwd_resp_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le32 unused_0;
	u8 unused_1;
	u8 unused_2;
	u8 unused_3;
	u8 valid;
};

/* hwrm_fwd_async_event_cmpl */
/* Input (32 bytes) */
struct hwrm_fwd_async_event_cmpl_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	__le16 encap_async_event_target_id;
	u8 unused_0;
	u8 unused_1;
	u8 unused_2[3];
	u8 unused_3;
	__le32 encap_async_event_cmpl[4];
};

/* Output (16 bytes) */
struct hwrm_fwd_async_event_cmpl_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le32 unused_0;
	u8 unused_1;
	u8 unused_2;
	u8 unused_3;
	u8 valid;
};

/* hwrm_temp_monitor_query */
/* Input (16 bytes) */
struct hwrm_temp_monitor_query_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
};

/* Output (16 bytes) */
struct hwrm_temp_monitor_query_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	u8 temp;
	u8 unused_0;
	__le16 unused_1;
	u8 unused_2;
	u8 unused_3;
	u8 unused_4;
	u8 valid;
};

/* hwrm_nvm_read */
/* Input (40 bytes) */
struct hwrm_nvm_read_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	__le64 host_dest_addr;
	__le16 dir_idx;
	u8 unused_0;
	u8 unused_1;
	__le32 offset;
	__le32 len;
	__le32 unused_2;
};

/* Output (16 bytes) */
struct hwrm_nvm_read_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le32 unused_0;
	u8 unused_1;
	u8 unused_2;
	u8 unused_3;
	u8 valid;
};

/* hwrm_nvm_raw_dump */
/* Input (32 bytes) */
struct hwrm_nvm_raw_dump_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	__le64 host_dest_addr;
	__le32 offset;
	__le32 len;
};

/* Output (16 bytes) */
struct hwrm_nvm_raw_dump_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le32 unused_0;
	u8 unused_1;
	u8 unused_2;
	u8 unused_3;
	u8 valid;
};

/* hwrm_nvm_get_dir_entries */
/* Input (24 bytes) */
struct hwrm_nvm_get_dir_entries_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	__le64 host_dest_addr;
};

/* Output (16 bytes) */
struct hwrm_nvm_get_dir_entries_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le32 unused_0;
	u8 unused_1;
	u8 unused_2;
	u8 unused_3;
	u8 valid;
};

/* hwrm_nvm_get_dir_info */
/* Input (16 bytes) */
struct hwrm_nvm_get_dir_info_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
};

/* Output (24 bytes) */
struct hwrm_nvm_get_dir_info_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le32 entries;
	__le32 entry_length;
	__le32 unused_0;
	u8 unused_1;
	u8 unused_2;
	u8 unused_3;
	u8 valid;
};

/* hwrm_nvm_write */
/* Input (48 bytes) */
struct hwrm_nvm_write_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	__le64 host_src_addr;
	__le16 dir_type;
	__le16 dir_ordinal;
	__le16 dir_ext;
	__le16 dir_attr;
	__le32 dir_data_length;
	__le16 option;
	__le16 flags;
	#define NVM_WRITE_REQ_FLAGS_KEEP_ORIG_ACTIVE_IMG	    0x1UL
	__le32 dir_item_length;
	__le32 unused_0;
};

/* Output (16 bytes) */
struct hwrm_nvm_write_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le32 dir_item_length;
	__le16 dir_idx;
	u8 unused_0;
	u8 valid;
};

/* hwrm_nvm_modify */
/* Input (40 bytes) */
struct hwrm_nvm_modify_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	__le64 host_src_addr;
	__le16 dir_idx;
	u8 unused_0;
	u8 unused_1;
	__le32 offset;
	__le32 len;
	__le32 unused_2;
};

/* Output (16 bytes) */
struct hwrm_nvm_modify_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le32 unused_0;
	u8 unused_1;
	u8 unused_2;
	u8 unused_3;
	u8 valid;
};

/* hwrm_nvm_find_dir_entry */
/* Input (32 bytes) */
struct hwrm_nvm_find_dir_entry_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	__le32 enables;
	#define NVM_FIND_DIR_ENTRY_REQ_ENABLES_DIR_IDX_VALID       0x1UL
	__le16 dir_idx;
	__le16 dir_type;
	__le16 dir_ordinal;
	__le16 dir_ext;
	u8 opt_ordinal;
	#define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_MASK	    0x3UL
	#define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_SFT		    0
	#define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_EQ		   0x0UL
	#define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GE		   0x1UL
	#define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT		   0x2UL
	u8 unused_1[3];
};

/* Output (32 bytes) */
struct hwrm_nvm_find_dir_entry_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le32 dir_item_length;
	__le32 dir_data_length;
	__le32 fw_ver;
	__le16 dir_ordinal;
	__le16 dir_idx;
	__le32 unused_0;
	u8 unused_1;
	u8 unused_2;
	u8 unused_3;
	u8 valid;
};

/* hwrm_nvm_erase_dir_entry */
/* Input (24 bytes) */
struct hwrm_nvm_erase_dir_entry_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	__le16 dir_idx;
	__le16 unused_0[3];
};

/* Output (16 bytes) */
struct hwrm_nvm_erase_dir_entry_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le32 unused_0;
	u8 unused_1;
	u8 unused_2;
	u8 unused_3;
	u8 valid;
};

/* hwrm_nvm_get_dev_info */
/* Input (16 bytes) */
struct hwrm_nvm_get_dev_info_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
};

/* Output (32 bytes) */
struct hwrm_nvm_get_dev_info_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le16 manufacturer_id;
	__le16 device_id;
	__le32 sector_size;
	__le32 nvram_size;
	__le32 reserved_size;
	__le32 available_size;
	u8 unused_0;
	u8 unused_1;
	u8 unused_2;
	u8 valid;
};

/* hwrm_nvm_mod_dir_entry */
/* Input (32 bytes) */
struct hwrm_nvm_mod_dir_entry_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	__le32 enables;
	#define NVM_MOD_DIR_ENTRY_REQ_ENABLES_CHECKSUM		    0x1UL
	__le16 dir_idx;
	__le16 dir_ordinal;
	__le16 dir_ext;
	__le16 dir_attr;
	__le32 checksum;
};

/* Output (16 bytes) */
struct hwrm_nvm_mod_dir_entry_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le32 unused_0;
	u8 unused_1;
	u8 unused_2;
	u8 unused_3;
	u8 valid;
};

/* hwrm_nvm_verify_update */
/* Input (24 bytes) */
struct hwrm_nvm_verify_update_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	__le16 dir_type;
	__le16 dir_ordinal;
	__le16 dir_ext;
	__le16 unused_0;
};

/* Output (16 bytes) */
struct hwrm_nvm_verify_update_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le32 unused_0;
	u8 unused_1;
	u8 unused_2;
	u8 unused_3;
	u8 valid;
};

/* hwrm_nvm_install_update */
/* Input (24 bytes) */
struct hwrm_nvm_install_update_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	__le32 install_type;
	#define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_NORMAL	   0x0UL
	#define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_ALL	   0xffffffffUL
	__le32 unused_0;
};

/* Output (24 bytes) */
struct hwrm_nvm_install_update_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le64 installed_items;
	u8 result;
	#define NVM_INSTALL_UPDATE_RESP_RESULT_SUCCESS		   0x0UL
	u8 problem_item;
	#define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_NONE	   0x0UL
	#define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_PACKAGE      0xffUL
	u8 reset_required;
	#define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_NONE       0x0UL
	#define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_PCI	   0x1UL
	#define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_POWER      0x2UL
	u8 unused_0;
	u8 unused_1;
	u8 unused_2;
	u8 unused_3;
	u8 valid;
};

#endif