summaryrefslogtreecommitdiff
path: root/drivers/net/wwan/t7xx/t7xx_cldma.c
blob: f0a4783baf1f328ed50e629591244f3a4ccb77eb (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) 2021, MediaTek Inc.
 * Copyright (c) 2021-2022, Intel Corporation.
 *
 * Authors:
 *  Haijun Liu <haijun.liu@mediatek.com>
 *  Moises Veleta <moises.veleta@intel.com>
 *  Ricardo Martinez <ricardo.martinez@linux.intel.com>
 *
 * Contributors:
 *  Amir Hanania <amir.hanania@intel.com>
 *  Andy Shevchenko <andriy.shevchenko@linux.intel.com>
 *  Eliot Lee <eliot.lee@intel.com>
 *  Sreehari Kancharla <sreehari.kancharla@intel.com>
 */

#include <linux/bits.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/io-64-nonatomic-lo-hi.h>
#include <linux/types.h>

#include "t7xx_cldma.h"

#define ADDR_SIZE	8

void t7xx_cldma_clear_ip_busy(struct t7xx_cldma_hw *hw_info)
{
	u32 val;

	val = ioread32(hw_info->ap_pdn_base + REG_CLDMA_IP_BUSY);
	val |= IP_BUSY_WAKEUP;
	iowrite32(val, hw_info->ap_pdn_base + REG_CLDMA_IP_BUSY);
}

/**
 * t7xx_cldma_hw_restore() - Restore CLDMA HW registers.
 * @hw_info: Pointer to struct t7xx_cldma_hw.
 *
 * Restore HW after resume. Writes uplink configuration for CLDMA HW.
 */
void t7xx_cldma_hw_restore(struct t7xx_cldma_hw *hw_info)
{
	u32 ul_cfg;

	ul_cfg = ioread32(hw_info->ap_pdn_base + REG_CLDMA_UL_CFG);
	ul_cfg &= ~UL_CFG_BIT_MODE_MASK;

	if (hw_info->hw_mode == MODE_BIT_64)
		ul_cfg |= UL_CFG_BIT_MODE_64;
	else if (hw_info->hw_mode == MODE_BIT_40)
		ul_cfg |= UL_CFG_BIT_MODE_40;
	else if (hw_info->hw_mode == MODE_BIT_36)
		ul_cfg |= UL_CFG_BIT_MODE_36;

	iowrite32(ul_cfg, hw_info->ap_pdn_base + REG_CLDMA_UL_CFG);
	/* Disable TX and RX invalid address check */
	iowrite32(UL_MEM_CHECK_DIS, hw_info->ap_pdn_base + REG_CLDMA_UL_MEM);
	iowrite32(DL_MEM_CHECK_DIS, hw_info->ap_pdn_base + REG_CLDMA_DL_MEM);
}

void t7xx_cldma_hw_start_queue(struct t7xx_cldma_hw *hw_info, unsigned int qno,
			       enum mtk_txrx tx_rx)
{
	void __iomem *reg;
	u32 val;

	reg = tx_rx == MTK_RX ? hw_info->ap_pdn_base + REG_CLDMA_DL_START_CMD :
				hw_info->ap_pdn_base + REG_CLDMA_UL_START_CMD;
	val = qno == CLDMA_ALL_Q ? CLDMA_ALL_Q : BIT(qno);
	iowrite32(val, reg);
}

void t7xx_cldma_hw_start(struct t7xx_cldma_hw *hw_info)
{
	/* Enable the TX & RX interrupts */
	iowrite32(TXRX_STATUS_BITMASK, hw_info->ap_pdn_base + REG_CLDMA_L2TIMCR0);
	iowrite32(TXRX_STATUS_BITMASK, hw_info->ap_ao_base + REG_CLDMA_L2RIMCR0);
	/* Enable the empty queue interrupt */
	iowrite32(EMPTY_STATUS_BITMASK, hw_info->ap_pdn_base + REG_CLDMA_L2TIMCR0);
	iowrite32(EMPTY_STATUS_BITMASK, hw_info->ap_ao_base + REG_CLDMA_L2RIMCR0);
}

void t7xx_cldma_hw_reset(void __iomem *ao_base)
{
	u32 val;

	val = ioread32(ao_base + REG_INFRA_RST2_SET);
	val |= RST2_PMIC_SW_RST_SET;
	iowrite32(val, ao_base + REG_INFRA_RST2_SET);
	val = ioread32(ao_base + REG_INFRA_RST4_SET);
	val |= RST4_CLDMA1_SW_RST_SET;
	iowrite32(val, ao_base + REG_INFRA_RST4_SET);
	udelay(1);

	val = ioread32(ao_base + REG_INFRA_RST4_CLR);
	val |= RST4_CLDMA1_SW_RST_CLR;
	iowrite32(val, ao_base + REG_INFRA_RST4_CLR);
	val = ioread32(ao_base + REG_INFRA_RST2_CLR);
	val |= RST2_PMIC_SW_RST_CLR;
	iowrite32(val, ao_base + REG_INFRA_RST2_CLR);
}

bool t7xx_cldma_tx_addr_is_set(struct t7xx_cldma_hw *hw_info, unsigned int qno)
{
	u32 offset = REG_CLDMA_UL_START_ADDRL_0 + qno * ADDR_SIZE;

	return ioread64_lo_hi(hw_info->ap_pdn_base + offset);
}

void t7xx_cldma_hw_set_start_addr(struct t7xx_cldma_hw *hw_info, unsigned int qno, u64 address,
				  enum mtk_txrx tx_rx)
{
	u32 offset = qno * ADDR_SIZE;
	void __iomem *reg;

	reg = tx_rx == MTK_RX ? hw_info->ap_ao_base + REG_CLDMA_DL_START_ADDRL_0 :
				hw_info->ap_pdn_base + REG_CLDMA_UL_START_ADDRL_0;
	iowrite64_lo_hi(address, reg + offset);
}

void t7xx_cldma_hw_resume_queue(struct t7xx_cldma_hw *hw_info, unsigned int qno,
				enum mtk_txrx tx_rx)
{
	void __iomem *base = hw_info->ap_pdn_base;

	if (tx_rx == MTK_RX)
		iowrite32(BIT(qno), base + REG_CLDMA_DL_RESUME_CMD);
	else
		iowrite32(BIT(qno), base + REG_CLDMA_UL_RESUME_CMD);
}

unsigned int t7xx_cldma_hw_queue_status(struct t7xx_cldma_hw *hw_info, unsigned int qno,
					enum mtk_txrx tx_rx)
{
	void __iomem *reg;
	u32 mask, val;

	mask = qno == CLDMA_ALL_Q ? CLDMA_ALL_Q : BIT(qno);
	reg = tx_rx == MTK_RX ? hw_info->ap_ao_base + REG_CLDMA_DL_STATUS :
				hw_info->ap_pdn_base + REG_CLDMA_UL_STATUS;
	val = ioread32(reg);

	return val & mask;
}

void t7xx_cldma_hw_tx_done(struct t7xx_cldma_hw *hw_info, unsigned int bitmask)
{
	unsigned int ch_id;

	ch_id = ioread32(hw_info->ap_pdn_base + REG_CLDMA_L2TISAR0);
	ch_id &= bitmask;
	/* Clear the ch IDs in the TX interrupt status register */
	iowrite32(ch_id, hw_info->ap_pdn_base + REG_CLDMA_L2TISAR0);
	ioread32(hw_info->ap_pdn_base + REG_CLDMA_L2TISAR0);
}

void t7xx_cldma_hw_rx_done(struct t7xx_cldma_hw *hw_info, unsigned int bitmask)
{
	unsigned int ch_id;

	ch_id = ioread32(hw_info->ap_pdn_base + REG_CLDMA_L2RISAR0);
	ch_id &= bitmask;
	/* Clear the ch IDs in the RX interrupt status register */
	iowrite32(ch_id, hw_info->ap_pdn_base + REG_CLDMA_L2RISAR0);
	ioread32(hw_info->ap_pdn_base + REG_CLDMA_L2RISAR0);
}

unsigned int t7xx_cldma_hw_int_status(struct t7xx_cldma_hw *hw_info, unsigned int bitmask,
				      enum mtk_txrx tx_rx)
{
	void __iomem *reg;
	u32 val;

	reg = tx_rx == MTK_RX ? hw_info->ap_pdn_base + REG_CLDMA_L2RISAR0 :
				hw_info->ap_pdn_base + REG_CLDMA_L2TISAR0;
	val = ioread32(reg);
	return val & bitmask;
}

void t7xx_cldma_hw_irq_dis_txrx(struct t7xx_cldma_hw *hw_info, unsigned int qno,
				enum mtk_txrx tx_rx)
{
	void __iomem *reg;
	u32 val;

	reg = tx_rx == MTK_RX ? hw_info->ap_ao_base + REG_CLDMA_L2RIMSR0 :
				hw_info->ap_pdn_base + REG_CLDMA_L2TIMSR0;
	val = qno == CLDMA_ALL_Q ? CLDMA_ALL_Q : BIT(qno);
	iowrite32(val, reg);
}

void t7xx_cldma_hw_irq_dis_eq(struct t7xx_cldma_hw *hw_info, unsigned int qno, enum mtk_txrx tx_rx)
{
	void __iomem *reg;
	u32 val;

	reg = tx_rx == MTK_RX ? hw_info->ap_ao_base + REG_CLDMA_L2RIMSR0 :
				hw_info->ap_pdn_base + REG_CLDMA_L2TIMSR0;
	val = qno == CLDMA_ALL_Q ? CLDMA_ALL_Q : BIT(qno);
	iowrite32(val << EQ_STA_BIT_OFFSET, reg);
}

void t7xx_cldma_hw_irq_en_txrx(struct t7xx_cldma_hw *hw_info, unsigned int qno,
			       enum mtk_txrx tx_rx)
{
	void __iomem *reg;
	u32 val;

	reg = tx_rx == MTK_RX ? hw_info->ap_ao_base + REG_CLDMA_L2RIMCR0 :
				hw_info->ap_pdn_base + REG_CLDMA_L2TIMCR0;
	val = qno == CLDMA_ALL_Q ? CLDMA_ALL_Q : BIT(qno);
	iowrite32(val, reg);
}

void t7xx_cldma_hw_irq_en_eq(struct t7xx_cldma_hw *hw_info, unsigned int qno, enum mtk_txrx tx_rx)
{
	void __iomem *reg;
	u32 val;

	reg = tx_rx == MTK_RX ? hw_info->ap_ao_base + REG_CLDMA_L2RIMCR0 :
				hw_info->ap_pdn_base + REG_CLDMA_L2TIMCR0;
	val = qno == CLDMA_ALL_Q ? CLDMA_ALL_Q : BIT(qno);
	iowrite32(val << EQ_STA_BIT_OFFSET, reg);
}

/**
 * t7xx_cldma_hw_init() - Initialize CLDMA HW.
 * @hw_info: Pointer to struct t7xx_cldma_hw.
 *
 * Write uplink and downlink configuration to CLDMA HW.
 */
void t7xx_cldma_hw_init(struct t7xx_cldma_hw *hw_info)
{
	u32 ul_cfg, dl_cfg;

	ul_cfg = ioread32(hw_info->ap_pdn_base + REG_CLDMA_UL_CFG);
	dl_cfg = ioread32(hw_info->ap_ao_base + REG_CLDMA_DL_CFG);
	/* Configure the DRAM address mode */
	ul_cfg &= ~UL_CFG_BIT_MODE_MASK;
	dl_cfg &= ~DL_CFG_BIT_MODE_MASK;

	if (hw_info->hw_mode == MODE_BIT_64) {
		ul_cfg |= UL_CFG_BIT_MODE_64;
		dl_cfg |= DL_CFG_BIT_MODE_64;
	} else if (hw_info->hw_mode == MODE_BIT_40) {
		ul_cfg |= UL_CFG_BIT_MODE_40;
		dl_cfg |= DL_CFG_BIT_MODE_40;
	} else if (hw_info->hw_mode == MODE_BIT_36) {
		ul_cfg |= UL_CFG_BIT_MODE_36;
		dl_cfg |= DL_CFG_BIT_MODE_36;
	}

	iowrite32(ul_cfg, hw_info->ap_pdn_base + REG_CLDMA_UL_CFG);
	dl_cfg |= DL_CFG_UP_HW_LAST;
	iowrite32(dl_cfg, hw_info->ap_ao_base + REG_CLDMA_DL_CFG);
	iowrite32(0, hw_info->ap_ao_base + REG_CLDMA_INT_MASK);
	iowrite32(BUSY_MASK_MD, hw_info->ap_ao_base + REG_CLDMA_BUSY_MASK);
	iowrite32(UL_MEM_CHECK_DIS, hw_info->ap_pdn_base + REG_CLDMA_UL_MEM);
	iowrite32(DL_MEM_CHECK_DIS, hw_info->ap_pdn_base + REG_CLDMA_DL_MEM);
}

void t7xx_cldma_hw_stop_all_qs(struct t7xx_cldma_hw *hw_info, enum mtk_txrx tx_rx)
{
	void __iomem *reg;

	reg = tx_rx == MTK_RX ? hw_info->ap_pdn_base + REG_CLDMA_DL_STOP_CMD :
				hw_info->ap_pdn_base + REG_CLDMA_UL_STOP_CMD;
	iowrite32(CLDMA_ALL_Q, reg);
}

void t7xx_cldma_hw_stop(struct t7xx_cldma_hw *hw_info, enum mtk_txrx tx_rx)
{
	void __iomem *reg;

	reg = tx_rx == MTK_RX ? hw_info->ap_ao_base + REG_CLDMA_L2RIMSR0 :
				hw_info->ap_pdn_base + REG_CLDMA_L2TIMSR0;
	iowrite32(TXRX_STATUS_BITMASK, reg);
	iowrite32(EMPTY_STATUS_BITMASK, reg);
}