summaryrefslogtreecommitdiff
path: root/drivers/phy/intel/phy-intel-lgm-emmc.c
blob: 703aeb122541ce8c4c7a122282e5f0b831f16463 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
// SPDX-License-Identifier: GPL-2.0
/*
 * Intel eMMC PHY driver
 * Copyright (C) 2019 Intel, Corp.
 */

#include <linux/bits.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>

/* eMMC phy register definitions */
#define EMMC_PHYCTRL0_REG	0xa8
#define DR_TY_MASK		GENMASK(30, 28)
#define DR_TY_SHIFT(x)		(((x) << 28) & DR_TY_MASK)
#define OTAPDLYENA		BIT(14)
#define OTAPDLYSEL_MASK		GENMASK(13, 10)
#define OTAPDLYSEL_SHIFT(x)	(((x) << 10) & OTAPDLYSEL_MASK)

#define EMMC_PHYCTRL1_REG	0xac
#define PDB_MASK		BIT(0)
#define PDB_SHIFT(x)		(((x) << 0) & PDB_MASK)
#define ENDLL_MASK		BIT(7)
#define ENDLL_SHIFT(x)		(((x) << 7) & ENDLL_MASK)

#define EMMC_PHYCTRL2_REG	0xb0
#define FRQSEL_25M		0
#define FRQSEL_50M		1
#define FRQSEL_100M		2
#define FRQSEL_150M		3
#define FRQSEL_MASK		GENMASK(24, 22)
#define FRQSEL_SHIFT(x)		(((x) << 22) & FRQSEL_MASK)

#define EMMC_PHYSTAT_REG	0xbc
#define CALDONE_MASK		BIT(9)
#define DLLRDY_MASK		BIT(8)
#define IS_CALDONE(x)	((x) & CALDONE_MASK)
#define IS_DLLRDY(x)	((x) & DLLRDY_MASK)

struct intel_emmc_phy {
	struct regmap *syscfg;
	struct clk *emmcclk;
};

static int intel_emmc_phy_power(struct phy *phy, bool on_off)
{
	struct intel_emmc_phy *priv = phy_get_drvdata(phy);
	unsigned int caldone;
	unsigned int dllrdy;
	unsigned int freqsel;
	unsigned long rate;
	int ret, quot;

	/*
	 * Keep phyctrl_pdb and phyctrl_endll low to allow
	 * initialization of CALIO state M/C DFFs
	 */
	ret = regmap_update_bits(priv->syscfg, EMMC_PHYCTRL1_REG, PDB_MASK,
				 PDB_SHIFT(0));
	if (ret) {
		dev_err(&phy->dev, "CALIO power down bar failed: %d\n", ret);
		return ret;
	}

	/* Already finish power_off above */
	if (!on_off)
		return 0;

	rate = clk_get_rate(priv->emmcclk);
	quot = DIV_ROUND_CLOSEST(rate, 50000000);
	if (quot > FRQSEL_150M)
		dev_warn(&phy->dev, "Unsupported rate: %lu\n", rate);
	freqsel = clamp_t(int, quot, FRQSEL_25M, FRQSEL_150M);

	/*
	 * According to the user manual, calpad calibration
	 * cycle takes more than 2us without the minimal recommended
	 * value, so we may need a little margin here
	 */
	udelay(5);

	ret = regmap_update_bits(priv->syscfg, EMMC_PHYCTRL1_REG, PDB_MASK,
				 PDB_SHIFT(1));
	if (ret) {
		dev_err(&phy->dev, "CALIO power down bar failed: %d\n", ret);
		return ret;
	}

	/*
	 * According to the user manual, it asks driver to wait 5us for
	 * calpad busy trimming. However it is documented that this value is
	 * PVT(A.K.A process,voltage and temperature) relevant, so some
	 * failure cases are found which indicates we should be more tolerant
	 * to calpad busy trimming.
	 */
	ret = regmap_read_poll_timeout(priv->syscfg, EMMC_PHYSTAT_REG,
				       caldone, IS_CALDONE(caldone),
				       0, 50);
	if (ret) {
		dev_err(&phy->dev, "caldone failed, ret=%d\n", ret);
		return ret;
	}

	/* Set the frequency of the DLL operation */
	ret = regmap_update_bits(priv->syscfg, EMMC_PHYCTRL2_REG, FRQSEL_MASK,
				 FRQSEL_SHIFT(freqsel));
	if (ret) {
		dev_err(&phy->dev, "set the frequency of dll failed:%d\n", ret);
		return ret;
	}

	/* Turn on the DLL */
	ret = regmap_update_bits(priv->syscfg, EMMC_PHYCTRL1_REG, ENDLL_MASK,
				 ENDLL_SHIFT(1));
	if (ret) {
		dev_err(&phy->dev, "turn on the dll failed: %d\n", ret);
		return ret;
	}

	/*
	 * After enabling analog DLL circuits docs say that we need 10.2 us if
	 * our source clock is at 50 MHz and that lock time scales linearly
	 * with clock speed.  If we are powering on the PHY and the card clock
	 * is super slow (like 100 kHZ) this could take as long as 5.1 ms as
	 * per the math: 10.2 us * (50000000 Hz / 100000 Hz) => 5.1 ms
	 * Hopefully we won't be running at 100 kHz, but we should still make
	 * sure we wait long enough.
	 *
	 * NOTE: There appear to be corner cases where the DLL seems to take
	 * extra long to lock for reasons that aren't understood.  In some
	 * extreme cases we've seen it take up to over 10ms (!).  We'll be
	 * generous and give it 50ms.
	 */
	ret = regmap_read_poll_timeout(priv->syscfg,
				       EMMC_PHYSTAT_REG,
				       dllrdy, IS_DLLRDY(dllrdy),
				       0, 50 * USEC_PER_MSEC);
	if (ret) {
		dev_err(&phy->dev, "dllrdy failed. ret=%d\n", ret);
		return ret;
	}

	return 0;
}

static int intel_emmc_phy_init(struct phy *phy)
{
	struct intel_emmc_phy *priv = phy_get_drvdata(phy);

	/*
	 * We purposely get the clock here and not in probe to avoid the
	 * circular dependency problem. We expect:
	 * - PHY driver to probe
	 * - SDHCI driver to start probe
	 * - SDHCI driver to register it's clock
	 * - SDHCI driver to get the PHY
	 * - SDHCI driver to init the PHY
	 *
	 * The clock is optional, so upon any error just return it like
	 * any other error to user.
	 *
	 */
	priv->emmcclk = clk_get_optional(&phy->dev, "emmcclk");
	if (IS_ERR(priv->emmcclk)) {
		dev_err(&phy->dev, "ERROR: getting emmcclk\n");
		return PTR_ERR(priv->emmcclk);
	}

	return 0;
}

static int intel_emmc_phy_exit(struct phy *phy)
{
	struct intel_emmc_phy *priv = phy_get_drvdata(phy);

	clk_put(priv->emmcclk);

	return 0;
}

static int intel_emmc_phy_power_on(struct phy *phy)
{
	struct intel_emmc_phy *priv = phy_get_drvdata(phy);
	int ret;

	/* Drive impedance: 50 Ohm */
	ret = regmap_update_bits(priv->syscfg, EMMC_PHYCTRL0_REG, DR_TY_MASK,
				 DR_TY_SHIFT(6));
	if (ret) {
		dev_err(&phy->dev, "ERROR set drive-impednce-50ohm: %d\n", ret);
		return ret;
	}

	/* Output tap delay: disable */
	ret = regmap_update_bits(priv->syscfg, EMMC_PHYCTRL0_REG, OTAPDLYENA,
				 0);
	if (ret) {
		dev_err(&phy->dev, "ERROR Set output tap delay : %d\n", ret);
		return ret;
	}

	/* Output tap delay */
	ret = regmap_update_bits(priv->syscfg, EMMC_PHYCTRL0_REG,
				 OTAPDLYSEL_MASK, OTAPDLYSEL_SHIFT(4));
	if (ret) {
		dev_err(&phy->dev, "ERROR: output tap dly select: %d\n", ret);
		return ret;
	}

	/* Power up eMMC phy analog blocks */
	return intel_emmc_phy_power(phy, true);
}

static int intel_emmc_phy_power_off(struct phy *phy)
{
	/* Power down eMMC phy analog blocks */
	return intel_emmc_phy_power(phy, false);
}

static const struct phy_ops ops = {
	.init		= intel_emmc_phy_init,
	.exit		= intel_emmc_phy_exit,
	.power_on	= intel_emmc_phy_power_on,
	.power_off	= intel_emmc_phy_power_off,
	.owner		= THIS_MODULE,
};

static int intel_emmc_phy_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct device_node *np = dev->of_node;
	struct intel_emmc_phy *priv;
	struct phy *generic_phy;
	struct phy_provider *phy_provider;

	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;

	/* Get eMMC phy (accessed via chiptop) regmap */
	priv->syscfg = syscon_regmap_lookup_by_phandle(np, "intel,syscon");
	if (IS_ERR(priv->syscfg)) {
		dev_err(dev, "failed to find syscon\n");
		return PTR_ERR(priv->syscfg);
	}

	generic_phy = devm_phy_create(dev, np, &ops);
	if (IS_ERR(generic_phy)) {
		dev_err(dev, "failed to create PHY\n");
		return PTR_ERR(generic_phy);
	}

	phy_set_drvdata(generic_phy, priv);
	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);

	return PTR_ERR_OR_ZERO(phy_provider);
}

static const struct of_device_id intel_emmc_phy_dt_ids[] = {
	{ .compatible = "intel,lgm-emmc-phy" },
	{}
};

MODULE_DEVICE_TABLE(of, intel_emmc_phy_dt_ids);

static struct platform_driver intel_emmc_driver = {
	.probe		= intel_emmc_phy_probe,
	.driver		= {
		.name	= "intel-emmc-phy",
		.of_match_table = intel_emmc_phy_dt_ids,
	},
};

module_platform_driver(intel_emmc_driver);

MODULE_AUTHOR("Peter Harliman Liem <peter.harliman.liem@intel.com>");
MODULE_DESCRIPTION("Intel eMMC PHY driver");
MODULE_LICENSE("GPL v2");