summaryrefslogtreecommitdiff
path: root/drivers/platform/mellanox/nvsw-sn2201.c
blob: 75b699676ca6d77d4cdc6ec0c14297737571f289 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
// SPDX-License-Identifier: GPL-2.0+
/*
 * Nvidia sn2201 driver
 *
 * Copyright (C) 2022 Nvidia Technologies Ltd.
 */

#include <linux/device.h>
#include <linux/i2c.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/gpio.h>
#include <linux/module.h>
#include <linux/platform_data/mlxcpld.h>
#include <linux/platform_data/mlxreg.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>

/* SN2201 CPLD register offset. */
#define NVSW_SN2201_CPLD_LPC_I2C_BASE_ADRR          0x2000
#define NVSW_SN2201_CPLD_LPC_IO_RANGE               0x100
#define NVSW_SN2201_HW_VER_ID_OFFSET                0x00
#define NVSW_SN2201_BOARD_ID_OFFSET                 0x01
#define NVSW_SN2201_CPLD_VER_OFFSET                 0x02
#define NVSW_SN2201_CPLD_MVER_OFFSET                0x03
#define NVSW_SN2201_CPLD_ID_OFFSET                  0x04
#define NVSW_SN2201_CPLD_PN_OFFSET                  0x05
#define NVSW_SN2201_CPLD_PN1_OFFSET                 0x06
#define NVSW_SN2201_PSU_CTRL_OFFSET                 0x0a
#define NVSW_SN2201_QSFP28_STATUS_OFFSET            0x0b
#define NVSW_SN2201_QSFP28_INT_STATUS_OFFSET        0x0c
#define NVSW_SN2201_QSFP28_LP_STATUS_OFFSET         0x0d
#define NVSW_SN2201_QSFP28_RST_STATUS_OFFSET        0x0e
#define NVSW_SN2201_SYS_STATUS_OFFSET               0x0f
#define NVSW_SN2201_FRONT_SYS_LED_CTRL_OFFSET       0x10
#define NVSW_SN2201_FRONT_PSU_LED_CTRL_OFFSET       0x12
#define NVSW_SN2201_FRONT_UID_LED_CTRL_OFFSET       0x13
#define NVSW_SN2201_QSFP28_LED_TEST_STATUS_OFFSET   0x14
#define NVSW_SN2201_SYS_RST_STATUS_OFFSET           0x15
#define NVSW_SN2201_SYS_INT_STATUS_OFFSET           0x21
#define NVSW_SN2201_SYS_INT_MASK_OFFSET             0x22
#define NVSW_SN2201_ASIC_STATUS_OFFSET              0x24
#define NVSW_SN2201_ASIC_EVENT_OFFSET               0x25
#define NVSW_SN2201_ASIC_MAKS_OFFSET                0x26
#define NVSW_SN2201_THML_STATUS_OFFSET              0x27
#define NVSW_SN2201_THML_EVENT_OFFSET               0x28
#define NVSW_SN2201_THML_MASK_OFFSET                0x29
#define NVSW_SN2201_PS_ALT_STATUS_OFFSET            0x2a
#define NVSW_SN2201_PS_ALT_EVENT_OFFSET             0x2b
#define NVSW_SN2201_PS_ALT_MASK_OFFSET              0x2c
#define NVSW_SN2201_PS_PRSNT_STATUS_OFFSET          0x30
#define NVSW_SN2201_PS_PRSNT_EVENT_OFFSET           0x31
#define NVSW_SN2201_PS_PRSNT_MASK_OFFSET            0x32
#define NVSW_SN2201_PS_DC_OK_STATUS_OFFSET          0x33
#define NVSW_SN2201_PS_DC_OK_EVENT_OFFSET           0x34
#define NVSW_SN2201_PS_DC_OK_MASK_OFFSET            0x35
#define NVSW_SN2201_RST_CAUSE1_OFFSET               0x36
#define NVSW_SN2201_RST_CAUSE2_OFFSET               0x37
#define NVSW_SN2201_RST_SW_CTRL_OFFSET              0x38
#define NVSW_SN2201_FAN_PRSNT_STATUS_OFFSET         0x3a
#define NVSW_SN2201_FAN_PRSNT_EVENT_OFFSET          0x3b
#define NVSW_SN2201_FAN_PRSNT_MASK_OFFSET           0x3c
#define NVSW_SN2201_WD_TMR_OFFSET_LSB               0x40
#define NVSW_SN2201_WD_TMR_OFFSET_MSB               0x41
#define NVSW_SN2201_WD_ACT_OFFSET                   0x42
#define NVSW_SN2201_FAN_LED1_CTRL_OFFSET            0x50
#define NVSW_SN2201_FAN_LED2_CTRL_OFFSET            0x51
#define NVSW_SN2201_REG_MAX                         0x52

/* Number of physical I2C busses. */
#define NVSW_SN2201_PHY_I2C_BUS_NUM		2
/* Number of main mux channels. */
#define NVSW_SN2201_MAIN_MUX_CHNL_NUM		8

#define NVSW_SN2201_MAIN_NR			0
#define NVSW_SN2201_MAIN_MUX_NR			1
#define NVSW_SN2201_MAIN_MUX_DEFER_NR		(NVSW_SN2201_PHY_I2C_BUS_NUM + \
						 NVSW_SN2201_MAIN_MUX_CHNL_NUM - 1)

#define NVSW_SN2201_MAIN_MUX_CH0_NR	NVSW_SN2201_PHY_I2C_BUS_NUM
#define NVSW_SN2201_MAIN_MUX_CH1_NR	(NVSW_SN2201_MAIN_MUX_CH0_NR + 1)
#define NVSW_SN2201_MAIN_MUX_CH2_NR	(NVSW_SN2201_MAIN_MUX_CH0_NR + 2)
#define NVSW_SN2201_MAIN_MUX_CH3_NR	(NVSW_SN2201_MAIN_MUX_CH0_NR + 3)
#define NVSW_SN2201_MAIN_MUX_CH5_NR	(NVSW_SN2201_MAIN_MUX_CH0_NR + 5)
#define NVSW_SN2201_MAIN_MUX_CH6_NR	(NVSW_SN2201_MAIN_MUX_CH0_NR + 6)
#define NVSW_SN2201_MAIN_MUX_CH7_NR	(NVSW_SN2201_MAIN_MUX_CH0_NR + 7)
#define NVSW_SN2201_2ND_MUX_CH0_NR	(NVSW_SN2201_MAIN_MUX_CH7_NR + 1)
#define NVSW_SN2201_2ND_MUX_CH1_NR	(NVSW_SN2201_MAIN_MUX_CH7_NR + 2)
#define NVSW_SN2201_2ND_MUX_CH2_NR	(NVSW_SN2201_MAIN_MUX_CH7_NR + 3)
#define NVSW_SN2201_2ND_MUX_CH3_NR	(NVSW_SN2201_MAIN_MUX_CH7_NR + 4)

#define NVSW_SN2201_CPLD_NR		NVSW_SN2201_MAIN_MUX_CH0_NR
#define NVSW_SN2201_NR_NONE		-1

/* Masks for aggregation, PSU presence and power, ASIC events
 * in CPLD related registers.
 */
#define NVSW_SN2201_CPLD_AGGR_ASIC_MASK_DEF	0xe0
#define NVSW_SN2201_CPLD_AGGR_PSU_MASK_DEF	0x04
#define NVSW_SN2201_CPLD_AGGR_PWR_MASK_DEF	0x02
#define NVSW_SN2201_CPLD_AGGR_FAN_MASK_DEF	0x10
#define NVSW_SN2201_CPLD_AGGR_MASK_DEF      \
	(NVSW_SN2201_CPLD_AGGR_ASIC_MASK_DEF \
	| NVSW_SN2201_CPLD_AGGR_PSU_MASK_DEF \
	| NVSW_SN2201_CPLD_AGGR_PWR_MASK_DEF \
	| NVSW_SN2201_CPLD_AGGR_FAN_MASK_DEF)

#define NVSW_SN2201_CPLD_ASIC_MASK		GENMASK(3, 1)
#define NVSW_SN2201_CPLD_PSU_MASK		GENMASK(1, 0)
#define NVSW_SN2201_CPLD_PWR_MASK		GENMASK(1, 0)
#define NVSW_SN2201_CPLD_FAN_MASK		GENMASK(3, 0)

#define NVSW_SN2201_CPLD_SYSIRQ			26
#define NVSW_SN2201_LPC_SYSIRQ			28
#define NVSW_SN2201_CPLD_I2CADDR		0x41

#define NVSW_SN2201_WD_DFLT_TIMEOUT		600

/* nvsw_sn2201 - device private data
 * @dev: platform device;
 * @io_data: register access platform data;
 * @led_data: LED platform data;
 * @hotplug_data: hotplug platform data;
 * @i2c_data: I2C controller platform data;
 * @led: LED device;
 * @io_regs: register access device;
 * @pdev_hotplug: hotplug device;
 * @sn2201_devs: I2C devices for sn2201 devices;
 * @sn2201_devs_num: number of I2C devices for sn2201 device;
 * @main_mux_devs: I2C devices for main mux;
 * @main_mux_devs_num: number of I2C devices for main mux;
 * @cpld_devs: I2C devices for cpld;
 * @cpld_devs_num: number of I2C devices for cpld;
 * @main_mux_deferred_nr: I2C adapter number must be exist prior creating devices execution;
 */
struct nvsw_sn2201 {
	struct device *dev;
	struct mlxreg_core_platform_data *io_data;
	struct mlxreg_core_platform_data *led_data;
	struct mlxreg_core_platform_data *wd_data;
	struct mlxreg_core_hotplug_platform_data *hotplug_data;
	struct mlxreg_core_hotplug_platform_data *i2c_data;
	struct platform_device *led;
	struct platform_device *wd;
	struct platform_device *io_regs;
	struct platform_device *pdev_hotplug;
	struct platform_device *pdev_i2c;
	struct mlxreg_hotplug_device *sn2201_devs;
	int sn2201_devs_num;
	struct mlxreg_hotplug_device *main_mux_devs;
	int main_mux_devs_num;
	struct mlxreg_hotplug_device *cpld_devs;
	int cpld_devs_num;
	int main_mux_deferred_nr;
};

static bool nvsw_sn2201_writeable_reg(struct device *dev, unsigned int reg)
{
	switch (reg) {
	case NVSW_SN2201_PSU_CTRL_OFFSET:
	case NVSW_SN2201_QSFP28_LP_STATUS_OFFSET:
	case NVSW_SN2201_QSFP28_RST_STATUS_OFFSET:
	case NVSW_SN2201_FRONT_SYS_LED_CTRL_OFFSET:
	case NVSW_SN2201_FRONT_PSU_LED_CTRL_OFFSET:
	case NVSW_SN2201_FRONT_UID_LED_CTRL_OFFSET:
	case NVSW_SN2201_QSFP28_LED_TEST_STATUS_OFFSET:
	case NVSW_SN2201_SYS_RST_STATUS_OFFSET:
	case NVSW_SN2201_SYS_INT_MASK_OFFSET:
	case NVSW_SN2201_ASIC_EVENT_OFFSET:
	case NVSW_SN2201_ASIC_MAKS_OFFSET:
	case NVSW_SN2201_THML_EVENT_OFFSET:
	case NVSW_SN2201_THML_MASK_OFFSET:
	case NVSW_SN2201_PS_ALT_EVENT_OFFSET:
	case NVSW_SN2201_PS_ALT_MASK_OFFSET:
	case NVSW_SN2201_PS_PRSNT_EVENT_OFFSET:
	case NVSW_SN2201_PS_PRSNT_MASK_OFFSET:
	case NVSW_SN2201_PS_DC_OK_EVENT_OFFSET:
	case NVSW_SN2201_PS_DC_OK_MASK_OFFSET:
	case NVSW_SN2201_RST_SW_CTRL_OFFSET:
	case NVSW_SN2201_FAN_PRSNT_EVENT_OFFSET:
	case NVSW_SN2201_FAN_PRSNT_MASK_OFFSET:
	case NVSW_SN2201_WD_TMR_OFFSET_LSB:
	case NVSW_SN2201_WD_TMR_OFFSET_MSB:
	case NVSW_SN2201_WD_ACT_OFFSET:
	case NVSW_SN2201_FAN_LED1_CTRL_OFFSET:
	case NVSW_SN2201_FAN_LED2_CTRL_OFFSET:
		return true;
	}
	return false;
}

static bool nvsw_sn2201_readable_reg(struct device *dev, unsigned int reg)
{
	switch (reg) {
	case NVSW_SN2201_HW_VER_ID_OFFSET:
	case NVSW_SN2201_BOARD_ID_OFFSET:
	case NVSW_SN2201_CPLD_VER_OFFSET:
	case NVSW_SN2201_CPLD_MVER_OFFSET:
	case NVSW_SN2201_CPLD_ID_OFFSET:
	case NVSW_SN2201_CPLD_PN_OFFSET:
	case NVSW_SN2201_CPLD_PN1_OFFSET:
	case NVSW_SN2201_PSU_CTRL_OFFSET:
	case NVSW_SN2201_QSFP28_STATUS_OFFSET:
	case NVSW_SN2201_QSFP28_INT_STATUS_OFFSET:
	case NVSW_SN2201_QSFP28_LP_STATUS_OFFSET:
	case NVSW_SN2201_QSFP28_RST_STATUS_OFFSET:
	case NVSW_SN2201_SYS_STATUS_OFFSET:
	case NVSW_SN2201_FRONT_SYS_LED_CTRL_OFFSET:
	case NVSW_SN2201_FRONT_PSU_LED_CTRL_OFFSET:
	case NVSW_SN2201_FRONT_UID_LED_CTRL_OFFSET:
	case NVSW_SN2201_QSFP28_LED_TEST_STATUS_OFFSET:
	case NVSW_SN2201_SYS_RST_STATUS_OFFSET:
	case NVSW_SN2201_RST_CAUSE1_OFFSET:
	case NVSW_SN2201_RST_CAUSE2_OFFSET:
	case NVSW_SN2201_SYS_INT_STATUS_OFFSET:
	case NVSW_SN2201_SYS_INT_MASK_OFFSET:
	case NVSW_SN2201_ASIC_STATUS_OFFSET:
	case NVSW_SN2201_ASIC_EVENT_OFFSET:
	case NVSW_SN2201_ASIC_MAKS_OFFSET:
	case NVSW_SN2201_THML_STATUS_OFFSET:
	case NVSW_SN2201_THML_EVENT_OFFSET:
	case NVSW_SN2201_THML_MASK_OFFSET:
	case NVSW_SN2201_PS_ALT_STATUS_OFFSET:
	case NVSW_SN2201_PS_ALT_EVENT_OFFSET:
	case NVSW_SN2201_PS_ALT_MASK_OFFSET:
	case NVSW_SN2201_PS_PRSNT_STATUS_OFFSET:
	case NVSW_SN2201_PS_PRSNT_EVENT_OFFSET:
	case NVSW_SN2201_PS_PRSNT_MASK_OFFSET:
	case NVSW_SN2201_PS_DC_OK_STATUS_OFFSET:
	case NVSW_SN2201_PS_DC_OK_EVENT_OFFSET:
	case NVSW_SN2201_PS_DC_OK_MASK_OFFSET:
	case NVSW_SN2201_RST_SW_CTRL_OFFSET:
	case NVSW_SN2201_FAN_PRSNT_STATUS_OFFSET:
	case NVSW_SN2201_FAN_PRSNT_EVENT_OFFSET:
	case NVSW_SN2201_FAN_PRSNT_MASK_OFFSET:
	case NVSW_SN2201_WD_TMR_OFFSET_LSB:
	case NVSW_SN2201_WD_TMR_OFFSET_MSB:
	case NVSW_SN2201_WD_ACT_OFFSET:
	case NVSW_SN2201_FAN_LED1_CTRL_OFFSET:
	case NVSW_SN2201_FAN_LED2_CTRL_OFFSET:
		return true;
	}
	return false;
}

static bool nvsw_sn2201_volatile_reg(struct device *dev, unsigned int reg)
{
	switch (reg) {
	case NVSW_SN2201_HW_VER_ID_OFFSET:
	case NVSW_SN2201_BOARD_ID_OFFSET:
	case NVSW_SN2201_CPLD_VER_OFFSET:
	case NVSW_SN2201_CPLD_MVER_OFFSET:
	case NVSW_SN2201_CPLD_ID_OFFSET:
	case NVSW_SN2201_CPLD_PN_OFFSET:
	case NVSW_SN2201_CPLD_PN1_OFFSET:
	case NVSW_SN2201_PSU_CTRL_OFFSET:
	case NVSW_SN2201_QSFP28_STATUS_OFFSET:
	case NVSW_SN2201_QSFP28_INT_STATUS_OFFSET:
	case NVSW_SN2201_QSFP28_LP_STATUS_OFFSET:
	case NVSW_SN2201_QSFP28_RST_STATUS_OFFSET:
	case NVSW_SN2201_SYS_STATUS_OFFSET:
	case NVSW_SN2201_FRONT_SYS_LED_CTRL_OFFSET:
	case NVSW_SN2201_FRONT_PSU_LED_CTRL_OFFSET:
	case NVSW_SN2201_FRONT_UID_LED_CTRL_OFFSET:
	case NVSW_SN2201_QSFP28_LED_TEST_STATUS_OFFSET:
	case NVSW_SN2201_SYS_RST_STATUS_OFFSET:
	case NVSW_SN2201_RST_CAUSE1_OFFSET:
	case NVSW_SN2201_RST_CAUSE2_OFFSET:
	case NVSW_SN2201_SYS_INT_STATUS_OFFSET:
	case NVSW_SN2201_SYS_INT_MASK_OFFSET:
	case NVSW_SN2201_ASIC_STATUS_OFFSET:
	case NVSW_SN2201_ASIC_EVENT_OFFSET:
	case NVSW_SN2201_ASIC_MAKS_OFFSET:
	case NVSW_SN2201_THML_STATUS_OFFSET:
	case NVSW_SN2201_THML_EVENT_OFFSET:
	case NVSW_SN2201_THML_MASK_OFFSET:
	case NVSW_SN2201_PS_ALT_STATUS_OFFSET:
	case NVSW_SN2201_PS_ALT_EVENT_OFFSET:
	case NVSW_SN2201_PS_ALT_MASK_OFFSET:
	case NVSW_SN2201_PS_PRSNT_STATUS_OFFSET:
	case NVSW_SN2201_PS_PRSNT_EVENT_OFFSET:
	case NVSW_SN2201_PS_PRSNT_MASK_OFFSET:
	case NVSW_SN2201_PS_DC_OK_STATUS_OFFSET:
	case NVSW_SN2201_PS_DC_OK_EVENT_OFFSET:
	case NVSW_SN2201_PS_DC_OK_MASK_OFFSET:
	case NVSW_SN2201_RST_SW_CTRL_OFFSET:
	case NVSW_SN2201_FAN_PRSNT_STATUS_OFFSET:
	case NVSW_SN2201_FAN_PRSNT_EVENT_OFFSET:
	case NVSW_SN2201_FAN_PRSNT_MASK_OFFSET:
	case NVSW_SN2201_WD_TMR_OFFSET_LSB:
	case NVSW_SN2201_WD_TMR_OFFSET_MSB:
	case NVSW_SN2201_FAN_LED1_CTRL_OFFSET:
	case NVSW_SN2201_FAN_LED2_CTRL_OFFSET:
		return true;
	}
	return false;
}

static const struct reg_default nvsw_sn2201_regmap_default[] = {
	{ NVSW_SN2201_QSFP28_LED_TEST_STATUS_OFFSET, 0x00 },
	{ NVSW_SN2201_WD_ACT_OFFSET, 0x00 },
};

/* Configuration for the register map of a device with 1 bytes address space. */
static const struct regmap_config nvsw_sn2201_regmap_conf = {
	.reg_bits = 8,
	.val_bits = 8,
	.max_register = NVSW_SN2201_REG_MAX,
	.cache_type = REGCACHE_FLAT,
	.writeable_reg = nvsw_sn2201_writeable_reg,
	.readable_reg = nvsw_sn2201_readable_reg,
	.volatile_reg = nvsw_sn2201_volatile_reg,
	.reg_defaults = nvsw_sn2201_regmap_default,
	.num_reg_defaults = ARRAY_SIZE(nvsw_sn2201_regmap_default),
};

/* Regions for LPC I2C controller and LPC base register space. */
static const struct resource nvsw_sn2201_lpc_io_resources[] = {
	[0] = DEFINE_RES_NAMED(NVSW_SN2201_CPLD_LPC_I2C_BASE_ADRR,
			       NVSW_SN2201_CPLD_LPC_IO_RANGE,
			       "mlxplat_cpld_lpc_i2c_ctrl", IORESOURCE_IO),
};

static struct resource nvsw_sn2201_cpld_res[] = {
	[0] = DEFINE_RES_IRQ_NAMED(NVSW_SN2201_CPLD_SYSIRQ, "mlxreg-hotplug"),
};

static struct resource nvsw_sn2201_lpc_res[] = {
	[0] = DEFINE_RES_IRQ_NAMED(NVSW_SN2201_LPC_SYSIRQ, "i2c-mlxcpld"),
};

/* SN2201 I2C platform data. */
static struct mlxreg_core_hotplug_platform_data nvsw_sn2201_i2c_data = {
	.irq = NVSW_SN2201_CPLD_SYSIRQ,
};

/* SN2201 CPLD device. */
static struct i2c_board_info nvsw_sn2201_cpld_devices[] = {
	{
		I2C_BOARD_INFO("nvsw-sn2201", 0x41),
	},
};

/* SN2201 CPLD board info. */
static struct mlxreg_hotplug_device nvsw_sn2201_cpld_brdinfo[] = {
	{
		.brdinfo = &nvsw_sn2201_cpld_devices[0],
		.nr = NVSW_SN2201_CPLD_NR,
	},
};

/* SN2201 main mux device. */
static struct i2c_board_info nvsw_sn2201_main_mux_devices[] = {
	{
		I2C_BOARD_INFO("pca9548", 0x70),
	},
};

/* SN2201 main mux board info. */
static struct mlxreg_hotplug_device nvsw_sn2201_main_mux_brdinfo[] = {
	{
		.brdinfo = &nvsw_sn2201_main_mux_devices[0],
		.nr = NVSW_SN2201_MAIN_MUX_NR,
	},
};

/* SN2201 power devices. */
static struct i2c_board_info nvsw_sn2201_pwr_devices[] = {
	{
		I2C_BOARD_INFO("pmbus", 0x58),
	},
	{
		I2C_BOARD_INFO("pmbus", 0x58),
	},
};

/* SN2201 fan devices. */
static struct i2c_board_info nvsw_sn2201_fan_devices[] = {
	{
		I2C_BOARD_INFO("24c02", 0x50),
	},
	{
		I2C_BOARD_INFO("24c02", 0x51),
	},
	{
		I2C_BOARD_INFO("24c02", 0x52),
	},
	{
		I2C_BOARD_INFO("24c02", 0x53),
	},
};

/* SN2201 hotplug default data. */
static struct mlxreg_core_data nvsw_sn2201_psu_items_data[] = {
	{
		.label = "psu1",
		.reg = NVSW_SN2201_PS_PRSNT_STATUS_OFFSET,
		.mask = BIT(0),
		.hpdev.nr = NVSW_SN2201_NR_NONE,
	},
	{
		.label = "psu2",
		.reg = NVSW_SN2201_PS_PRSNT_STATUS_OFFSET,
		.mask = BIT(1),
		.hpdev.nr = NVSW_SN2201_NR_NONE,
	},
};

static struct mlxreg_core_data nvsw_sn2201_pwr_items_data[] = {
	{
		.label = "pwr1",
		.reg = NVSW_SN2201_PS_DC_OK_STATUS_OFFSET,
		.mask = BIT(0),
		.hpdev.brdinfo = &nvsw_sn2201_pwr_devices[0],
		.hpdev.nr = NVSW_SN2201_MAIN_MUX_CH1_NR,
	},
	{
		.label = "pwr2",
		.reg = NVSW_SN2201_PS_DC_OK_STATUS_OFFSET,
		.mask = BIT(1),
		.hpdev.brdinfo = &nvsw_sn2201_pwr_devices[1],
		.hpdev.nr = NVSW_SN2201_MAIN_MUX_CH2_NR,
	},
};

static struct mlxreg_core_data nvsw_sn2201_fan_items_data[] = {
	{
		.label = "fan1",
		.reg = NVSW_SN2201_FAN_PRSNT_STATUS_OFFSET,
		.mask = BIT(0),
		.hpdev.brdinfo = &nvsw_sn2201_fan_devices[0],
		.hpdev.nr = NVSW_SN2201_2ND_MUX_CH0_NR,
	},
	{
		.label = "fan2",
		.reg = NVSW_SN2201_FAN_PRSNT_STATUS_OFFSET,
		.mask = BIT(1),
		.hpdev.brdinfo = &nvsw_sn2201_fan_devices[1],
		.hpdev.nr = NVSW_SN2201_2ND_MUX_CH1_NR,
	},
	{
		.label = "fan3",
		.reg = NVSW_SN2201_FAN_PRSNT_STATUS_OFFSET,
		.mask = BIT(2),
		.hpdev.brdinfo = &nvsw_sn2201_fan_devices[2],
		.hpdev.nr = NVSW_SN2201_2ND_MUX_CH2_NR,
	},
	{
		.label = "fan4",
		.reg = NVSW_SN2201_FAN_PRSNT_STATUS_OFFSET,
		.mask = BIT(3),
		.hpdev.brdinfo = &nvsw_sn2201_fan_devices[3],
		.hpdev.nr = NVSW_SN2201_2ND_MUX_CH3_NR,
	},
};

static struct mlxreg_core_data nvsw_sn2201_sys_items_data[] = {
	{
		.label = "nic_smb_alert",
		.reg = NVSW_SN2201_ASIC_STATUS_OFFSET,
		.mask = BIT(1),
		.hpdev.nr = NVSW_SN2201_NR_NONE,
	},
	{
		.label = "cpu_sd",
		.reg = NVSW_SN2201_ASIC_STATUS_OFFSET,
		.mask = BIT(2),
		.hpdev.nr = NVSW_SN2201_NR_NONE,
	},
	{
		.label = "mac_health",
		.reg = NVSW_SN2201_ASIC_STATUS_OFFSET,
		.mask = BIT(3),
		.hpdev.nr = NVSW_SN2201_NR_NONE,
	},
};

static struct mlxreg_core_item nvsw_sn2201_items[] = {
	{
		.data = nvsw_sn2201_psu_items_data,
		.aggr_mask = NVSW_SN2201_CPLD_AGGR_PSU_MASK_DEF,
		.reg = NVSW_SN2201_PS_PRSNT_STATUS_OFFSET,
		.mask = NVSW_SN2201_CPLD_PSU_MASK,
		.count = ARRAY_SIZE(nvsw_sn2201_psu_items_data),
		.inversed = 1,
		.health = false,
	},
	{
		.data = nvsw_sn2201_pwr_items_data,
		.aggr_mask = NVSW_SN2201_CPLD_AGGR_PWR_MASK_DEF,
		.reg = NVSW_SN2201_PS_DC_OK_STATUS_OFFSET,
		.mask = NVSW_SN2201_CPLD_PWR_MASK,
		.count = ARRAY_SIZE(nvsw_sn2201_pwr_items_data),
		.inversed = 0,
		.health = false,
	},
	{
		.data = nvsw_sn2201_fan_items_data,
		.aggr_mask = NVSW_SN2201_CPLD_AGGR_FAN_MASK_DEF,
		.reg = NVSW_SN2201_FAN_PRSNT_STATUS_OFFSET,
		.mask = NVSW_SN2201_CPLD_FAN_MASK,
		.count = ARRAY_SIZE(nvsw_sn2201_fan_items_data),
		.inversed = 1,
		.health = false,
	},
	{
		.data = nvsw_sn2201_sys_items_data,
		.aggr_mask = NVSW_SN2201_CPLD_AGGR_ASIC_MASK_DEF,
		.reg = NVSW_SN2201_ASIC_STATUS_OFFSET,
		.mask = NVSW_SN2201_CPLD_ASIC_MASK,
		.count = ARRAY_SIZE(nvsw_sn2201_sys_items_data),
		.inversed = 1,
		.health = false,
	},
};

static
struct mlxreg_core_hotplug_platform_data nvsw_sn2201_hotplug = {
	.items = nvsw_sn2201_items,
	.counter = ARRAY_SIZE(nvsw_sn2201_items),
	.cell = NVSW_SN2201_SYS_INT_STATUS_OFFSET,
	.mask = NVSW_SN2201_CPLD_AGGR_MASK_DEF,
};

/* SN2201 static devices. */
static struct i2c_board_info nvsw_sn2201_static_devices[] = {
	{
		I2C_BOARD_INFO("24c02", 0x57),
	},
	{
		I2C_BOARD_INFO("lm75", 0x4b),
	},
	{
		I2C_BOARD_INFO("24c64", 0x56),
	},
	{
		I2C_BOARD_INFO("ads1015", 0x49),
	},
	{
		I2C_BOARD_INFO("pca9546", 0x71),
	},
	{
		I2C_BOARD_INFO("emc2305", 0x4d),
	},
	{
		I2C_BOARD_INFO("lm75", 0x49),
	},
	{
		I2C_BOARD_INFO("pca9555", 0x27),
	},
	{
		I2C_BOARD_INFO("powr1014", 0x37),
	},
	{
		I2C_BOARD_INFO("lm75", 0x4f),
	},
	{
		I2C_BOARD_INFO("pmbus", 0x40),
	},
};

/* SN2201 default static board info. */
static struct mlxreg_hotplug_device nvsw_sn2201_static_brdinfo[] = {
	{
		.brdinfo = &nvsw_sn2201_static_devices[0],
		.nr = NVSW_SN2201_MAIN_NR,
	},
	{
		.brdinfo = &nvsw_sn2201_static_devices[1],
		.nr = NVSW_SN2201_MAIN_MUX_CH0_NR,
	},
	{
		.brdinfo = &nvsw_sn2201_static_devices[2],
		.nr = NVSW_SN2201_MAIN_MUX_CH0_NR,
	},
	{
		.brdinfo = &nvsw_sn2201_static_devices[3],
		.nr = NVSW_SN2201_MAIN_MUX_CH0_NR,
	},
	{
		.brdinfo = &nvsw_sn2201_static_devices[4],
		.nr = NVSW_SN2201_MAIN_MUX_CH3_NR,
	},
	{
		.brdinfo = &nvsw_sn2201_static_devices[5],
		.nr = NVSW_SN2201_MAIN_MUX_CH5_NR,
	},
	{
		.brdinfo = &nvsw_sn2201_static_devices[6],
		.nr = NVSW_SN2201_MAIN_MUX_CH5_NR,
	},
	{
		.brdinfo = &nvsw_sn2201_static_devices[7],
		.nr = NVSW_SN2201_MAIN_MUX_CH5_NR,
	},
	{
		.brdinfo = &nvsw_sn2201_static_devices[8],
		.nr = NVSW_SN2201_MAIN_MUX_CH6_NR,
	},
	{
		.brdinfo = &nvsw_sn2201_static_devices[9],
		.nr = NVSW_SN2201_MAIN_MUX_CH6_NR,
	},
	{
		.brdinfo = &nvsw_sn2201_static_devices[10],
		.nr = NVSW_SN2201_MAIN_MUX_CH7_NR,
	},
};

/* LED default data. */
static struct mlxreg_core_data nvsw_sn2201_led_data[] = {
	{
		.label = "status:green",
		.reg = NVSW_SN2201_FRONT_SYS_LED_CTRL_OFFSET,
		.mask = GENMASK(7, 4),
	},
	{
		.label = "status:orange",
		.reg = NVSW_SN2201_FRONT_SYS_LED_CTRL_OFFSET,
		.mask = GENMASK(7, 4),
	},
	{
		.label = "psu:green",
		.reg = NVSW_SN2201_FRONT_PSU_LED_CTRL_OFFSET,
		.mask = GENMASK(7, 4),
	},
	{
		.label = "psu:orange",
		.reg = NVSW_SN2201_FRONT_PSU_LED_CTRL_OFFSET,
		.mask = GENMASK(7, 4),
	},
	{
		.label = "uid:blue",
		.reg = NVSW_SN2201_FRONT_UID_LED_CTRL_OFFSET,
		.mask = GENMASK(7, 4),
	},
	{
		.label = "fan1:green",
		.reg = NVSW_SN2201_FAN_LED1_CTRL_OFFSET,
		.mask = GENMASK(7, 4),
	},
	{
		.label = "fan1:orange",
		.reg = NVSW_SN2201_FAN_LED1_CTRL_OFFSET,
		.mask = GENMASK(7, 4),
	},
	{
		.label = "fan2:green",
		.reg = NVSW_SN2201_FAN_LED1_CTRL_OFFSET,
		.mask = GENMASK(3, 0),
	},
	{
		.label = "fan2:orange",
		.reg = NVSW_SN2201_FAN_LED1_CTRL_OFFSET,
		.mask = GENMASK(3, 0),
	},
	{
		.label = "fan3:green",
		.reg = NVSW_SN2201_FAN_LED2_CTRL_OFFSET,
		.mask = GENMASK(7, 4),
	},
	{
		.label = "fan3:orange",
		.reg = NVSW_SN2201_FAN_LED2_CTRL_OFFSET,
		.mask = GENMASK(7, 4),
	},
	{
		.label = "fan4:green",
		.reg = NVSW_SN2201_FAN_LED2_CTRL_OFFSET,
		.mask = GENMASK(3, 0),
	},
	{
		.label = "fan4:orange",
		.reg = NVSW_SN2201_FAN_LED2_CTRL_OFFSET,
		.mask = GENMASK(3, 0),
	},
};

static struct mlxreg_core_platform_data nvsw_sn2201_led = {
	.data = nvsw_sn2201_led_data,
	.counter = ARRAY_SIZE(nvsw_sn2201_led_data),
};

/* Default register access data. */
static struct mlxreg_core_data nvsw_sn2201_io_data[] = {
	{
		.label = "cpld1_version",
		.reg = NVSW_SN2201_CPLD_VER_OFFSET,
		.bit = GENMASK(7, 0),
		.mode = 0444,
	},
	{
		.label = "cpld1_version_min",
		.reg = NVSW_SN2201_CPLD_MVER_OFFSET,
		.bit = GENMASK(7, 0),
		.mode = 0444,
	},
	{
		.label = "cpld1_pn",
		.reg = NVSW_SN2201_CPLD_PN_OFFSET,
		.bit = GENMASK(15, 0),
		.mode = 0444,
		.regnum = 2,
	},
	{
		.label = "psu1_on",
		.reg = NVSW_SN2201_PSU_CTRL_OFFSET,
		.mask = GENMASK(7, 0) & ~BIT(0),
		.mode = 0644,
	},
	{
		.label = "psu2_on",
		.reg = NVSW_SN2201_PSU_CTRL_OFFSET,
		.mask = GENMASK(7, 0) & ~BIT(1),
		.mode = 0644,
	},
	{
		.label = "pwr_cycle",
		.reg = NVSW_SN2201_PSU_CTRL_OFFSET,
		.mask = GENMASK(7, 0) & ~BIT(2),
		.mode = 0644,
	},
	{
		.label = "asic_health",
		.reg = NVSW_SN2201_SYS_STATUS_OFFSET,
		.mask = GENMASK(4, 3),
		.bit = 4,
		.mode = 0444,
	},
	{
		.label = "qsfp_pwr_good",
		.reg = NVSW_SN2201_SYS_STATUS_OFFSET,
		.mask = GENMASK(7, 0) & ~BIT(0),
		.mode = 0444,
	},
	{
		.label = "phy_reset",
		.reg = NVSW_SN2201_SYS_RST_STATUS_OFFSET,
		.mask = GENMASK(7, 0) & ~BIT(3),
		.mode = 0644,
	},
	{
		.label = "mac_reset",
		.reg = NVSW_SN2201_SYS_RST_STATUS_OFFSET,
		.mask = GENMASK(7, 0) & ~BIT(2),
		.mode = 0644,
	},
	{
		.label = "pwr_down",
		.reg = NVSW_SN2201_RST_SW_CTRL_OFFSET,
		.mask = GENMASK(7, 0) & ~BIT(0),
		.mode = 0644,
	},
	{
		.label = "reset_long_pb",
		.reg = NVSW_SN2201_RST_CAUSE1_OFFSET,
		.mask = GENMASK(7, 0) & ~BIT(0),
		.mode = 0444,
	},
	{
		.label = "reset_short_pb",
		.reg = NVSW_SN2201_RST_CAUSE1_OFFSET,
		.mask = GENMASK(7, 0) & ~BIT(1),
		.mode = 0444,
	},
	{
		.label = "reset_aux_pwr_or_fu",
		.reg = NVSW_SN2201_RST_CAUSE1_OFFSET,
		.mask = GENMASK(7, 0) & ~BIT(2),
		.mode = 0444,
	},
	{
		.label = "reset_swb_dc_dc_pwr_fail",
		.reg = NVSW_SN2201_RST_CAUSE1_OFFSET,
		.mask = GENMASK(7, 0) & ~BIT(3),
		.mode = 0444,
	},
	{
		.label = "reset_sw_reset",
		.reg = NVSW_SN2201_RST_CAUSE1_OFFSET,
		.mask = GENMASK(7, 0) & ~BIT(4),
		.mode = 0444,
	},
	{
		.label = "reset_fw_reset",
		.reg = NVSW_SN2201_RST_CAUSE1_OFFSET,
		.mask = GENMASK(7, 0) & ~BIT(5),
		.mode = 0444,
	},
	{
		.label = "reset_swb_wd",
		.reg = NVSW_SN2201_RST_CAUSE1_OFFSET,
		.mask = GENMASK(7, 0) & ~BIT(6),
		.mode = 0444,
	},
	{
		.label = "reset_asic_thermal",
		.reg = NVSW_SN2201_RST_CAUSE1_OFFSET,
		.mask = GENMASK(7, 0) & ~BIT(7),
		.mode = 0444,
	},
	{
		.label = "reset_system",
		.reg = NVSW_SN2201_RST_CAUSE2_OFFSET,
		.mask = GENMASK(7, 0) & ~BIT(1),
		.mode = 0444,
	},
	{
		.label = "reset_sw_pwr_off",
		.reg = NVSW_SN2201_RST_CAUSE2_OFFSET,
		.mask = GENMASK(7, 0) & ~BIT(2),
		.mode = 0444,
	},
	{
		.label = "reset_cpu_pwr_fail_thermal",
		.reg = NVSW_SN2201_RST_CAUSE2_OFFSET,
		.mask = GENMASK(7, 0) & ~BIT(4),
		.mode = 0444,
	},
	{
		.label = "reset_reload_bios",
		.reg = NVSW_SN2201_RST_CAUSE2_OFFSET,
		.mask = GENMASK(7, 0) & ~BIT(5),
		.mode = 0444,
	},
	{
		.label = "reset_ac_pwr_fail",
		.reg = NVSW_SN2201_RST_CAUSE2_OFFSET,
		.mask = GENMASK(7, 0) & ~BIT(6),
		.mode = 0444,
	},
	{
		.label = "psu1",
		.reg = NVSW_SN2201_PS_PRSNT_STATUS_OFFSET,
		.mask = GENMASK(7, 0) & ~BIT(0),
		.mode = 0444,
	},
	{
		.label = "psu2",
		.reg = NVSW_SN2201_PS_PRSNT_STATUS_OFFSET,
		.mask = GENMASK(7, 0) & ~BIT(1),
		.mode = 0444,
	},
};

static struct mlxreg_core_platform_data nvsw_sn2201_regs_io = {
	.data = nvsw_sn2201_io_data,
	.counter = ARRAY_SIZE(nvsw_sn2201_io_data),
};

/* Default watchdog data. */
static struct mlxreg_core_data nvsw_sn2201_wd_data[] = {
	{
		.label = "action",
		.reg = NVSW_SN2201_WD_ACT_OFFSET,
		.mask = GENMASK(7, 1),
		.bit = 0,
	},
	{
		.label = "timeout",
		.reg = NVSW_SN2201_WD_TMR_OFFSET_LSB,
		.mask = 0,
		.health_cntr = NVSW_SN2201_WD_DFLT_TIMEOUT,
	},
	{
		.label = "timeleft",
		.reg = NVSW_SN2201_WD_TMR_OFFSET_LSB,
		.mask = 0,
	},
	{
		.label = "ping",
		.reg = NVSW_SN2201_WD_ACT_OFFSET,
		.mask = GENMASK(7, 1),
		.bit = 0,
	},
	{
		.label = "reset",
		.reg = NVSW_SN2201_RST_CAUSE1_OFFSET,
		.mask = GENMASK(7, 0) & ~BIT(6),
		.bit = 6,
	},
};

static struct mlxreg_core_platform_data nvsw_sn2201_wd = {
	.data = nvsw_sn2201_wd_data,
	.counter = ARRAY_SIZE(nvsw_sn2201_wd_data),
	.version = MLX_WDT_TYPE3,
	.identity = "mlx-wdt-main",
};

static int
nvsw_sn2201_create_static_devices(struct nvsw_sn2201 *nvsw_sn2201,
				  struct mlxreg_hotplug_device *devs,
				  int size)
{
	struct mlxreg_hotplug_device *dev = devs;
	int ret;
	int i;

	/* Create I2C static devices. */
	for (i = 0; i < size; i++, dev++) {
		dev->client = i2c_new_client_device(dev->adapter, dev->brdinfo);
		if (IS_ERR(dev->client)) {
			dev_err(nvsw_sn2201->dev, "Failed to create client %s at bus %d at addr 0x%02x\n",
				dev->brdinfo->type,
				dev->nr, dev->brdinfo->addr);

			dev->adapter = NULL;
			ret = PTR_ERR(dev->client);
			goto fail_create_static_devices;
		}
	}

	return 0;

fail_create_static_devices:
	while (--i >= 0) {
		dev = devs + i;
		i2c_unregister_device(dev->client);
		dev->client = NULL;
		dev->adapter = NULL;
	}
	return ret;
}

static void nvsw_sn2201_destroy_static_devices(struct nvsw_sn2201 *nvsw_sn2201,
					       struct mlxreg_hotplug_device *devs, int size)
{
	struct mlxreg_hotplug_device *dev = devs;
	int i;

	/* Destroy static I2C device for SN2201 static devices. */
	for (i = 0; i < size; i++, dev++) {
		if (dev->client) {
			i2c_unregister_device(dev->client);
			dev->client = NULL;
			i2c_put_adapter(dev->adapter);
			dev->adapter = NULL;
		}
	}
}

static int nvsw_sn2201_config_post_init(struct nvsw_sn2201 *nvsw_sn2201)
{
	struct mlxreg_hotplug_device *sn2201_dev;
	struct i2c_adapter *adap;
	struct device *dev;
	int i, err;

	dev = nvsw_sn2201->dev;
	adap = i2c_get_adapter(nvsw_sn2201->main_mux_deferred_nr);
	if (!adap) {
		dev_err(dev, "Failed to get adapter for bus %d\n",
			nvsw_sn2201->main_mux_deferred_nr);
		return -ENODEV;
	}
	i2c_put_adapter(adap);

	/* Update board info. */
	sn2201_dev = nvsw_sn2201->sn2201_devs;
	for (i = 0; i < nvsw_sn2201->sn2201_devs_num; i++, sn2201_dev++) {
		sn2201_dev->adapter = i2c_get_adapter(sn2201_dev->nr);
		if (!sn2201_dev->adapter)
			return -ENODEV;
		i2c_put_adapter(sn2201_dev->adapter);
	}

	err = nvsw_sn2201_create_static_devices(nvsw_sn2201, nvsw_sn2201->sn2201_devs,
						nvsw_sn2201->sn2201_devs_num);
	if (err)
		dev_err(dev, "Failed to create static devices\n");

	return err;
}

static int nvsw_sn2201_config_init(struct nvsw_sn2201 *nvsw_sn2201, void *regmap)
{
	struct device *dev = nvsw_sn2201->dev;
	int err;

	nvsw_sn2201->io_data = &nvsw_sn2201_regs_io;
	nvsw_sn2201->led_data = &nvsw_sn2201_led;
	nvsw_sn2201->wd_data = &nvsw_sn2201_wd;
	nvsw_sn2201->hotplug_data = &nvsw_sn2201_hotplug;

	/* Register IO access driver. */
	if (nvsw_sn2201->io_data) {
		nvsw_sn2201->io_data->regmap = regmap;
		nvsw_sn2201->io_regs =
		platform_device_register_resndata(dev, "mlxreg-io", PLATFORM_DEVID_NONE, NULL, 0,
						  nvsw_sn2201->io_data,
						  sizeof(*nvsw_sn2201->io_data));
		if (IS_ERR(nvsw_sn2201->io_regs)) {
			err = PTR_ERR(nvsw_sn2201->io_regs);
			goto fail_register_io;
		}
	}

	/* Register LED driver. */
	if (nvsw_sn2201->led_data) {
		nvsw_sn2201->led_data->regmap = regmap;
		nvsw_sn2201->led =
		platform_device_register_resndata(dev, "leds-mlxreg", PLATFORM_DEVID_NONE, NULL, 0,
						  nvsw_sn2201->led_data,
						  sizeof(*nvsw_sn2201->led_data));
		if (IS_ERR(nvsw_sn2201->led)) {
			err = PTR_ERR(nvsw_sn2201->led);
			goto fail_register_led;
		}
	}

	/* Register WD driver. */
	if (nvsw_sn2201->wd_data) {
		nvsw_sn2201->wd_data->regmap = regmap;
		nvsw_sn2201->wd =
		platform_device_register_resndata(dev, "mlx-wdt", PLATFORM_DEVID_NONE, NULL, 0,
						  nvsw_sn2201->wd_data,
						  sizeof(*nvsw_sn2201->wd_data));
		if (IS_ERR(nvsw_sn2201->wd)) {
			err = PTR_ERR(nvsw_sn2201->wd);
			goto fail_register_wd;
		}
	}

	/* Register hotplug driver. */
	if (nvsw_sn2201->hotplug_data) {
		nvsw_sn2201->hotplug_data->regmap = regmap;
		nvsw_sn2201->pdev_hotplug =
		platform_device_register_resndata(dev, "mlxreg-hotplug", PLATFORM_DEVID_NONE,
						  nvsw_sn2201_cpld_res,
						  ARRAY_SIZE(nvsw_sn2201_cpld_res),
						  nvsw_sn2201->hotplug_data,
						  sizeof(*nvsw_sn2201->hotplug_data));
		if (IS_ERR(nvsw_sn2201->pdev_hotplug)) {
			err = PTR_ERR(nvsw_sn2201->pdev_hotplug);
			goto fail_register_hotplug;
		}
	}

	return nvsw_sn2201_config_post_init(nvsw_sn2201);

fail_register_hotplug:
	if (nvsw_sn2201->wd)
		platform_device_unregister(nvsw_sn2201->wd);
fail_register_wd:
	if (nvsw_sn2201->led)
		platform_device_unregister(nvsw_sn2201->led);
fail_register_led:
	if (nvsw_sn2201->io_regs)
		platform_device_unregister(nvsw_sn2201->io_regs);
fail_register_io:

	return err;
}

static void nvsw_sn2201_config_exit(struct nvsw_sn2201 *nvsw_sn2201)
{
	/* Unregister hotplug driver. */
	if (nvsw_sn2201->pdev_hotplug)
		platform_device_unregister(nvsw_sn2201->pdev_hotplug);
	/* Unregister WD driver. */
	if (nvsw_sn2201->wd)
		platform_device_unregister(nvsw_sn2201->wd);
	/* Unregister LED driver. */
	if (nvsw_sn2201->led)
		platform_device_unregister(nvsw_sn2201->led);
	/* Unregister IO access driver. */
	if (nvsw_sn2201->io_regs)
		platform_device_unregister(nvsw_sn2201->io_regs);
}

/*
 * Initialization is divided into two parts:
 * - I2C main bus init.
 * - Mux creation and attaching devices to the mux,
 *   which assumes that the main bus is already created.
 * This separation is required for synchronization between these two parts.
 * Completion notify callback is used to make this flow synchronized.
 */
static int nvsw_sn2201_i2c_completion_notify(void *handle, int id)
{
	struct nvsw_sn2201 *nvsw_sn2201 = handle;
	void *regmap;
	int i, err;

	/* Create main mux. */
	nvsw_sn2201->main_mux_devs->adapter = i2c_get_adapter(nvsw_sn2201->main_mux_devs->nr);
	if (!nvsw_sn2201->main_mux_devs->adapter) {
		err = -ENODEV;
		dev_err(nvsw_sn2201->dev, "Failed to get adapter for bus %d\n",
			nvsw_sn2201->cpld_devs->nr);
		goto i2c_get_adapter_main_fail;
	}

	nvsw_sn2201->main_mux_devs_num = ARRAY_SIZE(nvsw_sn2201_main_mux_brdinfo);
	err = nvsw_sn2201_create_static_devices(nvsw_sn2201, nvsw_sn2201->main_mux_devs,
						nvsw_sn2201->main_mux_devs_num);
	if (err) {
		dev_err(nvsw_sn2201->dev, "Failed to create main mux devices\n");
		goto nvsw_sn2201_create_static_devices_fail;
	}

	nvsw_sn2201->cpld_devs->adapter = i2c_get_adapter(nvsw_sn2201->cpld_devs->nr);
	if (!nvsw_sn2201->cpld_devs->adapter) {
		err = -ENODEV;
		dev_err(nvsw_sn2201->dev, "Failed to get adapter for bus %d\n",
			nvsw_sn2201->cpld_devs->nr);
		goto i2c_get_adapter_fail;
	}

	/* Create CPLD device. */
	nvsw_sn2201->cpld_devs->client = i2c_new_dummy_device(nvsw_sn2201->cpld_devs->adapter,
							      NVSW_SN2201_CPLD_I2CADDR);
	if (IS_ERR(nvsw_sn2201->cpld_devs->client)) {
		err = PTR_ERR(nvsw_sn2201->cpld_devs->client);
		dev_err(nvsw_sn2201->dev, "Failed to create %s cpld device at bus %d at addr 0x%02x\n",
			nvsw_sn2201->cpld_devs->brdinfo->type, nvsw_sn2201->cpld_devs->nr,
			nvsw_sn2201->cpld_devs->brdinfo->addr);
		goto i2c_new_dummy_fail;
	}

	regmap = devm_regmap_init_i2c(nvsw_sn2201->cpld_devs->client, &nvsw_sn2201_regmap_conf);
	if (IS_ERR(regmap)) {
		err = PTR_ERR(regmap);
		dev_err(nvsw_sn2201->dev, "Failed to initialise managed register map\n");
		goto devm_regmap_init_i2c_fail;
	}

	/* Set default registers. */
	for (i = 0; i < nvsw_sn2201_regmap_conf.num_reg_defaults; i++) {
		err = regmap_write(regmap, nvsw_sn2201_regmap_default[i].reg,
				   nvsw_sn2201_regmap_default[i].def);
		if (err) {
			dev_err(nvsw_sn2201->dev, "Failed to set register at offset 0x%02x to default value: 0x%02x\n",
				nvsw_sn2201_regmap_default[i].reg,
				nvsw_sn2201_regmap_default[i].def);
			goto regmap_write_fail;
		}
	}

	/* Sync registers with hardware. */
	regcache_mark_dirty(regmap);
	err = regcache_sync(regmap);
	if (err) {
		dev_err(nvsw_sn2201->dev, "Failed to Sync registers with hardware\n");
		goto regcache_sync_fail;
	}

	/* Configure SN2201 board. */
	err = nvsw_sn2201_config_init(nvsw_sn2201, regmap);
	if (err) {
		dev_err(nvsw_sn2201->dev, "Failed to configure board\n");
		goto nvsw_sn2201_config_init_fail;
	}

	return 0;

nvsw_sn2201_config_init_fail:
	nvsw_sn2201_config_exit(nvsw_sn2201);
regcache_sync_fail:
regmap_write_fail:
devm_regmap_init_i2c_fail:
i2c_new_dummy_fail:
	i2c_put_adapter(nvsw_sn2201->cpld_devs->adapter);
	nvsw_sn2201->cpld_devs->adapter = NULL;
i2c_get_adapter_fail:
	/* Destroy SN2201 static I2C devices. */
	nvsw_sn2201_destroy_static_devices(nvsw_sn2201, nvsw_sn2201->sn2201_devs,
					   nvsw_sn2201->sn2201_devs_num);
	/* Destroy main mux device. */
	nvsw_sn2201_destroy_static_devices(nvsw_sn2201, nvsw_sn2201->main_mux_devs,
					   nvsw_sn2201->main_mux_devs_num);
nvsw_sn2201_create_static_devices_fail:
	i2c_put_adapter(nvsw_sn2201->main_mux_devs->adapter);
i2c_get_adapter_main_fail:
	return err;
}

static int nvsw_sn2201_config_pre_init(struct nvsw_sn2201 *nvsw_sn2201)
{
	nvsw_sn2201->i2c_data = &nvsw_sn2201_i2c_data;

	/* Register I2C controller. */
	nvsw_sn2201->i2c_data->handle = nvsw_sn2201;
	nvsw_sn2201->i2c_data->completion_notify = nvsw_sn2201_i2c_completion_notify;
	nvsw_sn2201->pdev_i2c = platform_device_register_resndata(nvsw_sn2201->dev, "i2c_mlxcpld",
								  NVSW_SN2201_MAIN_MUX_NR,
								  nvsw_sn2201_lpc_res,
								  ARRAY_SIZE(nvsw_sn2201_lpc_res),
								  nvsw_sn2201->i2c_data,
								  sizeof(*nvsw_sn2201->i2c_data));
	if (IS_ERR(nvsw_sn2201->pdev_i2c))
		return PTR_ERR(nvsw_sn2201->pdev_i2c);

	return 0;
}

static int nvsw_sn2201_probe(struct platform_device *pdev)
{
	struct nvsw_sn2201 *nvsw_sn2201;

	nvsw_sn2201 = devm_kzalloc(&pdev->dev, sizeof(*nvsw_sn2201), GFP_KERNEL);
	if (!nvsw_sn2201)
		return -ENOMEM;

	nvsw_sn2201->dev = &pdev->dev;
	platform_set_drvdata(pdev, nvsw_sn2201);
	platform_device_add_resources(pdev, nvsw_sn2201_lpc_io_resources,
				      ARRAY_SIZE(nvsw_sn2201_lpc_io_resources));

	nvsw_sn2201->main_mux_deferred_nr = NVSW_SN2201_MAIN_MUX_DEFER_NR;
	nvsw_sn2201->main_mux_devs = nvsw_sn2201_main_mux_brdinfo;
	nvsw_sn2201->cpld_devs = nvsw_sn2201_cpld_brdinfo;
	nvsw_sn2201->sn2201_devs = nvsw_sn2201_static_brdinfo;
	nvsw_sn2201->sn2201_devs_num = ARRAY_SIZE(nvsw_sn2201_static_brdinfo);

	return nvsw_sn2201_config_pre_init(nvsw_sn2201);
}

static int nvsw_sn2201_remove(struct platform_device *pdev)
{
	struct nvsw_sn2201 *nvsw_sn2201 = platform_get_drvdata(pdev);

	/* Unregister underlying drivers. */
	nvsw_sn2201_config_exit(nvsw_sn2201);

	/* Destroy SN2201 static I2C devices. */
	nvsw_sn2201_destroy_static_devices(nvsw_sn2201,
					   nvsw_sn2201->sn2201_devs,
					   nvsw_sn2201->sn2201_devs_num);

	i2c_put_adapter(nvsw_sn2201->cpld_devs->adapter);
	nvsw_sn2201->cpld_devs->adapter = NULL;
	/* Destroy main mux device. */
	nvsw_sn2201_destroy_static_devices(nvsw_sn2201,
					   nvsw_sn2201->main_mux_devs,
					   nvsw_sn2201->main_mux_devs_num);

	/* Unregister I2C controller. */
	if (nvsw_sn2201->pdev_i2c)
		platform_device_unregister(nvsw_sn2201->pdev_i2c);

	return 0;
}

static const struct acpi_device_id nvsw_sn2201_acpi_ids[] = {
	{"NVSN2201", 0},
	{}
};

MODULE_DEVICE_TABLE(acpi, nvsw_sn2201_acpi_ids);

static struct platform_driver nvsw_sn2201_driver = {
	.probe = nvsw_sn2201_probe,
	.remove = nvsw_sn2201_remove,
	.driver = {
		.name = "nvsw-sn2201",
	.acpi_match_table = nvsw_sn2201_acpi_ids,
	},
};

module_platform_driver(nvsw_sn2201_driver);

MODULE_AUTHOR("Nvidia");
MODULE_DESCRIPTION("Nvidia sn2201 platform driver");
MODULE_LICENSE("Dual BSD/GPL");
MODULE_ALIAS("platform:nvsw-sn2201");