summaryrefslogtreecommitdiff
path: root/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
blob: feda9b54b4434fafcee1ba0fe95d8e03e76067d3 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730
1731
1732
1733
1734
1735
1736
1737
1738
1739
1740
1741
1742
1743
1744
1745
1746
1747
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759
1760
1761
1762
1763
1764
1765
1766
1767
1768
1769
1770
1771
1772
1773
1774
1775
1776
1777
1778
1779
1780
1781
1782
1783
1784
1785
1786
1787
1788
1789
1790
1791
1792
1793
1794
1795
1796
1797
1798
1799
1800
1801
1802
1803
1804
1805
1806
1807
1808
1809
1810
1811
1812
1813
1814
1815
1816
1817
1818
1819
1820
1821
1822
1823
1824
1825
1826
1827
1828
1829
1830
1831
1832
1833
1834
1835
1836
1837
1838
1839
1840
1841
1842
1843
1844
1845
1846
1847
1848
1849
1850
1851
1852
1853
1854
1855
1856
1857
1858
1859
1860
1861
1862
1863
1864
1865
1866
1867
1868
1869
1870
1871
1872
1873
1874
1875
1876
1877
1878
1879
1880
1881
1882
1883
1884
1885
1886
1887
1888
1889
1890
1891
1892
1893
1894
1895
1896
1897
1898
1899
1900
1901
1902
1903
1904
1905
1906
1907
1908
1909
1910
1911
1912
1913
1914
1915
1916
1917
1918
1919
1920
1921
1922
1923
1924
1925
1926
1927
1928
1929
1930
1931
1932
1933
1934
1935
1936
1937
1938
1939
1940
1941
1942
1943
1944
1945
1946
1947
1948
1949
1950
1951
1952
1953
1954
1955
1956
1957
1958
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
1976
1977
1978
1979
1980
1981
1982
1983
1984
1985
1986
1987
1988
1989
1990
1991
1992
1993
1994
1995
1996
1997
1998
1999
2000
2001
2002
2003
2004
2005
2006
2007
2008
2009
2010
2011
2012
2013
2014
2015
2016
2017
2018
2019
2020
2021
2022
2023
2024
2025
2026
2027
2028
2029
2030
2031
2032
2033
2034
2035
2036
2037
2038
2039
2040
2041
2042
2043
2044
2045
2046
2047
2048
2049
2050
2051
2052
2053
2054
2055
2056
2057
2058
2059
2060
2061
2062
2063
2064
2065
2066
2067
2068
2069
2070
2071
2072
2073
2074
2075
2076
2077
2078
2079
2080
2081
2082
2083
2084
2085
2086
2087
2088
2089
2090
2091
2092
2093
2094
2095
2096
2097
2098
2099
2100
2101
2102
2103
2104
2105
2106
2107
2108
2109
2110
2111
2112
2113
2114
2115
2116
2117
2118
2119
2120
2121
2122
2123
2124
2125
2126
2127
2128
2129
2130
2131
2132
2133
2134
2135
2136
2137
2138
2139
2140
2141
2142
2143
2144
2145
2146
2147
2148
2149
2150
2151
2152
2153
2154
2155
2156
2157
2158
2159
2160
2161
2162
2163
2164
2165
2166
2167
2168
2169
2170
2171
2172
2173
2174
2175
2176
2177
2178
2179
2180
2181
2182
2183
2184
2185
2186
2187
2188
2189
2190
2191
2192
2193
2194
2195
2196
2197
2198
2199
2200
2201
2202
2203
2204
2205
2206
2207
2208
2209
2210
2211
2212
2213
2214
2215
2216
2217
2218
2219
2220
2221
2222
2223
2224
2225
2226
2227
2228
2229
2230
2231
2232
2233
2234
2235
2236
2237
2238
2239
2240
2241
2242
2243
2244
2245
2246
2247
2248
2249
2250
2251
2252
2253
2254
2255
2256
2257
2258
2259
2260
2261
2262
2263
2264
2265
2266
2267
2268
2269
2270
2271
2272
2273
2274
2275
2276
2277
2278
2279
2280
2281
2282
2283
2284
2285
2286
2287
2288
2289
2290
2291
2292
2293
2294
2295
2296
2297
2298
2299
2300
2301
2302
2303
2304
2305
2306
2307
2308
2309
2310
2311
2312
2313
2314
2315
2316
2317
2318
2319
2320
2321
2322
2323
2324
2325
2326
2327
2328
2329
2330
2331
2332
2333
2334
2335
2336
2337
2338
2339
2340
2341
2342
2343
2344
2345
2346
2347
2348
2349
2350
2351
2352
2353
2354
2355
2356
2357
2358
2359
2360
2361
2362
2363
2364
2365
2366
2367
2368
2369
2370
2371
2372
2373
2374
2375
2376
2377
2378
2379
2380
2381
2382
2383
2384
2385
2386
2387
2388
2389
2390
2391
2392
2393
2394
2395
2396
2397
2398
2399
2400
2401
2402
2403
2404
2405
2406
2407
2408
2409
2410
2411
2412
2413
2414
2415
2416
2417
2418
2419
2420
2421
2422
2423
2424
2425
2426
2427
2428
2429
2430
2431
2432
2433
2434
2435
2436
2437
2438
2439
2440
2441
2442
2443
2444
2445
2446
2447
2448
2449
2450
2451
2452
2453
2454
2455
2456
2457
2458
2459
2460
2461
2462
2463
2464
2465
2466
2467
2468
2469
2470
2471
2472
2473
2474
2475
2476
2477
2478
2479
2480
2481
2482
2483
2484
2485
2486
2487
2488
2489
2490
2491
2492
2493
2494
2495
2496
2497
2498
2499
2500
2501
2502
2503
2504
2505
2506
2507
2508
2509
2510
2511
2512
2513
2514
2515
2516
2517
2518
2519
2520
2521
2522
2523
2524
2525
2526
2527
2528
2529
2530
2531
2532
2533
2534
2535
2536
2537
2538
2539
2540
2541
2542
2543
2544
2545
2546
2547
2548
2549
2550
2551
2552
2553
2554
2555
2556
2557
2558
2559
2560
2561
2562
2563
2564
2565
2566
2567
2568
2569
2570
2571
2572
2573
2574
2575
2576
2577
2578
2579
2580
2581
2582
2583
2584
2585
2586
2587
2588
2589
2590
2591
2592
2593
2594
2595
2596
2597
2598
2599
2600
2601
2602
2603
2604
2605
2606
2607
2608
2609
2610
2611
2612
2613
2614
2615
2616
2617
2618
2619
2620
2621
2622
2623
2624
2625
2626
2627
2628
2629
2630
2631
2632
2633
2634
2635
2636
2637
2638
2639
2640
2641
2642
2643
2644
2645
2646
2647
2648
2649
2650
2651
2652
2653
2654
2655
2656
2657
2658
2659
2660
2661
2662
2663
2664
2665
2666
2667
2668
2669
2670
2671
2672
2673
2674
2675
2676
2677
2678
2679
2680
2681
2682
2683
2684
2685
2686
2687
2688
2689
2690
2691
2692
2693
2694
2695
2696
2697
2698
2699
2700
2701
2702
2703
2704
2705
2706
2707
2708
2709
2710
2711
2712
2713
2714
2715
2716
2717
2718
2719
2720
2721
2722
2723
2724
2725
2726
2727
2728
2729
2730
2731
2732
2733
2734
2735
2736
2737
2738
2739
2740
2741
2742
2743
2744
2745
2746
2747
2748
2749
2750
2751
2752
2753
2754
2755
2756
2757
2758
2759
2760
2761
2762
2763
2764
2765
2766
2767
2768
2769
2770
2771
2772
2773
2774
2775
2776
2777
2778
2779
2780
2781
2782
2783
2784
2785
2786
2787
2788
2789
2790
2791
2792
2793
2794
2795
2796
2797
2798
2799
2800
2801
2802
2803
2804
2805
2806
2807
2808
2809
2810
2811
2812
2813
2814
2815
2816
2817
2818
2819
2820
2821
2822
2823
2824
2825
2826
2827
2828
2829
2830
2831
2832
2833
2834
2835
2836
2837
2838
2839
2840
2841
2842
2843
2844
2845
2846
2847
2848
2849
2850
2851
2852
2853
2854
2855
2856
2857
2858
2859
2860
2861
2862
2863
2864
2865
2866
2867
2868
2869
2870
2871
2872
2873
2874
2875
2876
2877
2878
2879
2880
2881
2882
2883
2884
2885
2886
2887
2888
2889
2890
2891
2892
2893
2894
2895
2896
2897
2898
2899
2900
2901
2902
2903
2904
2905
2906
2907
2908
2909
2910
2911
2912
2913
2914
2915
2916
2917
2918
2919
2920
2921
2922
2923
2924
2925
2926
2927
2928
2929
2930
2931
2932
2933
2934
2935
2936
2937
2938
2939
2940
2941
2942
2943
2944
2945
2946
2947
2948
2949
2950
2951
2952
2953
2954
2955
2956
2957
2958
2959
2960
2961
2962
2963
2964
2965
2966
2967
2968
2969
2970
2971
2972
2973
2974
2975
2976
2977
2978
2979
2980
2981
2982
2983
2984
2985
2986
2987
2988
2989
2990
2991
2992
2993
2994
2995
2996
2997
2998
2999
3000
3001
3002
3003
3004
3005
3006
3007
3008
3009
3010
3011
3012
3013
3014
3015
3016
3017
3018
3019
3020
3021
3022
3023
3024
3025
3026
3027
3028
3029
3030
3031
3032
3033
3034
3035
3036
3037
3038
3039
3040
3041
3042
3043
3044
3045
3046
3047
3048
3049
3050
3051
3052
3053
3054
3055
3056
3057
3058
3059
3060
3061
3062
3063
3064
3065
3066
3067
3068
3069
3070
3071
3072
3073
3074
3075
3076
3077
3078
3079
3080
3081
3082
3083
3084
3085
3086
3087
3088
3089
3090
3091
3092
3093
3094
3095
3096
3097
3098
3099
3100
3101
3102
3103
3104
3105
3106
3107
3108
3109
3110
3111
3112
3113
3114
3115
3116
3117
3118
3119
3120
3121
3122
3123
3124
3125
3126
3127
3128
3129
3130
3131
3132
3133
3134
3135
3136
3137
3138
3139
3140
3141
3142
3143
3144
3145
3146
3147
3148
3149
3150
3151
3152
3153
3154
3155
3156
3157
3158
3159
3160
3161
3162
3163
3164
3165
3166
3167
3168
3169
3170
3171
3172
3173
3174
3175
3176
3177
3178
3179
3180
3181
3182
3183
3184
3185
3186
3187
3188
3189
3190
3191
3192
3193
3194
3195
3196
3197
3198
3199
3200
3201
3202
3203
3204
3205
3206
3207
3208
3209
3210
3211
3212
3213
3214
3215
3216
3217
3218
3219
3220
3221
3222
3223
3224
3225
3226
3227
3228
3229
3230
3231
3232
3233
3234
3235
3236
3237
3238
3239
3240
3241
3242
3243
3244
3245
3246
3247
3248
3249
3250
3251
3252
3253
3254
3255
3256
3257
3258
3259
3260
3261
3262
3263
3264
3265
3266
3267
3268
3269
3270
3271
3272
3273
3274
3275
3276
3277
3278
3279
3280
3281
3282
3283
3284
3285
3286
3287
3288
3289
3290
3291
3292
3293
3294
3295
3296
3297
3298
3299
3300
3301
3302
3303
3304
3305
3306
3307
3308
3309
3310
3311
3312
3313
3314
3315
3316
3317
3318
3319
3320
3321
3322
3323
3324
3325
3326
3327
3328
3329
3330
3331
3332
3333
3334
3335
3336
3337
3338
3339
3340
3341
3342
3343
3344
3345
3346
3347
3348
3349
3350
3351
3352
3353
3354
3355
3356
3357
3358
3359
3360
3361
3362
3363
3364
3365
3366
3367
3368
3369
3370
3371
3372
3373
3374
3375
3376
3377
3378
3379
3380
3381
3382
3383
3384
3385
3386
3387
3388
3389
3390
3391
3392
3393
3394
3395
3396
3397
3398
3399
3400
3401
3402
3403
3404
3405
3406
3407
3408
3409
3410
3411
3412
3413
3414
3415
3416
3417
3418
3419
3420
3421
3422
3423
3424
3425
3426
3427
3428
3429
3430
3431
3432
3433
3434
3435
3436
3437
3438
3439
3440
3441
3442
3443
3444
3445
3446
3447
3448
3449
3450
3451
3452
3453
3454
3455
3456
3457
3458
3459
3460
3461
3462
3463
3464
3465
3466
3467
3468
3469
3470
3471
3472
3473
3474
3475
3476
3477
3478
3479
3480
3481
3482
3483
3484
3485
3486
3487
3488
3489
3490
3491
3492
3493
3494
3495
3496
3497
3498
3499
3500
3501
3502
3503
3504
3505
3506
3507
3508
3509
3510
3511
3512
3513
3514
3515
3516
3517
3518
3519
3520
3521
3522
3523
3524
3525
3526
3527
3528
3529
3530
3531
3532
3533
3534
3535
3536
3537
3538
3539
3540
3541
3542
3543
3544
3545
3546
3547
3548
3549
3550
3551
3552
3553
3554
3555
3556
3557
3558
3559
3560
3561
3562
3563
3564
3565
3566
3567
3568
3569
3570
3571
3572
3573
3574
3575
3576
3577
3578
3579
3580
3581
3582
3583
3584
3585
3586
3587
3588
3589
3590
3591
3592
3593
3594
3595
3596
3597
3598
3599
3600
3601
3602
3603
3604
3605
3606
3607
3608
3609
3610
3611
3612
3613
3614
3615
3616
3617
3618
3619
3620
3621
3622
3623
3624
3625
3626
3627
3628
3629
3630
3631
3632
3633
3634
3635
3636
3637
3638
3639
3640
3641
3642
3643
3644
3645
3646
3647
3648
3649
3650
3651
3652
3653
3654
3655
3656
3657
3658
3659
3660
3661
3662
3663
3664
3665
3666
3667
3668
3669
3670
3671
3672
3673
3674
3675
3676
3677
3678
3679
3680
3681
3682
3683
3684
3685
3686
3687
3688
3689
3690
3691
3692
3693
3694
3695
3696
3697
3698
3699
3700
3701
3702
3703
3704
3705
3706
3707
3708
3709
3710
3711
3712
3713
3714
3715
3716
3717
3718
3719
3720
3721
3722
3723
3724
3725
3726
3727
3728
3729
3730
3731
3732
3733
3734
3735
3736
3737
3738
3739
3740
3741
3742
3743
3744
3745
3746
3747
3748
3749
3750
3751
3752
3753
3754
3755
3756
3757
3758
3759
3760
3761
3762
3763
3764
3765
3766
3767
3768
3769
3770
3771
3772
3773
3774
3775
3776
3777
3778
3779
3780
3781
3782
3783
3784
3785
3786
3787
3788
3789
3790
3791
3792
3793
3794
3795
3796
3797
3798
3799
3800
3801
3802
3803
3804
3805
3806
3807
3808
3809
3810
3811
3812
3813
3814
3815
3816
3817
3818
3819
3820
3821
3822
3823
3824
3825
3826
3827
3828
3829
3830
3831
3832
3833
3834
3835
3836
3837
3838
3839
3840
3841
3842
3843
3844
3845
3846
3847
3848
3849
3850
3851
3852
3853
3854
3855
3856
3857
3858
3859
3860
3861
3862
3863
3864
3865
3866
3867
3868
3869
3870
3871
3872
3873
3874
3875
3876
3877
3878
3879
3880
3881
3882
3883
3884
3885
3886
3887
3888
3889
3890
3891
3892
3893
3894
3895
3896
3897
3898
3899
3900
3901
3902
3903
3904
3905
3906
3907
3908
3909
3910
3911
3912
3913
3914
3915
3916
3917
3918
3919
3920
3921
3922
3923
3924
3925
3926
3927
3928
3929
3930
3931
3932
3933
3934
3935
3936
3937
3938
3939
3940
3941
3942
3943
3944
3945
3946
3947
3948
3949
3950
3951
3952
3953
3954
3955
3956
3957
3958
3959
3960
3961
3962
3963
3964
3965
3966
3967
3968
3969
3970
3971
3972
3973
3974
3975
3976
3977
3978
3979
3980
3981
3982
3983
3984
3985
3986
3987
3988
3989
3990
3991
3992
3993
3994
3995
3996
3997
3998
3999
4000
4001
4002
4003
4004
4005
4006
4007
4008
4009
4010
4011
4012
4013
4014
4015
4016
4017
4018
4019
4020
4021
4022
4023
4024
4025
4026
4027
4028
4029
4030
4031
4032
4033
4034
4035
4036
4037
4038
4039
4040
4041
4042
4043
4044
4045
4046
4047
4048
4049
4050
4051
4052
4053
4054
4055
4056
4057
4058
4059
4060
4061
4062
4063
4064
4065
4066
4067
4068
4069
4070
4071
4072
4073
4074
4075
4076
4077
4078
4079
4080
4081
4082
4083
4084
4085
4086
4087
4088
4089
4090
4091
4092
4093
4094
4095
4096
4097
4098
4099
4100
4101
4102
4103
4104
4105
4106
4107
4108
4109
4110
4111
4112
4113
4114
4115
4116
4117
4118
4119
4120
4121
4122
4123
4124
4125
4126
4127
4128
4129
4130
4131
4132
4133
4134
4135
4136
4137
4138
4139
4140
4141
4142
4143
4144
4145
4146
4147
4148
4149
4150
4151
4152
4153
4154
4155
4156
4157
4158
4159
4160
4161
4162
4163
4164
4165
4166
4167
4168
4169
4170
4171
4172
4173
4174
4175
4176
4177
4178
4179
4180
4181
4182
4183
4184
4185
4186
4187
4188
4189
4190
4191
4192
4193
4194
4195
4196
4197
4198
4199
4200
4201
4202
4203
4204
4205
4206
4207
4208
4209
4210
4211
4212
4213
4214
4215
4216
4217
4218
4219
4220
4221
4222
4223
4224
4225
4226
4227
4228
4229
4230
4231
4232
4233
4234
4235
4236
4237
4238
4239
4240
4241
4242
4243
4244
4245
4246
4247
4248
4249
4250
4251
4252
4253
4254
4255
4256
4257
4258
4259
4260
4261
4262
4263
4264
4265
4266
4267
4268
4269
4270
4271
4272
4273
4274
4275
4276
4277
4278
4279
4280
4281
4282
4283
4284
4285
4286
4287
4288
4289
4290
4291
4292
4293
4294
4295
4296
4297
4298
4299
4300
4301
4302
4303
4304
4305
4306
4307
4308
4309
4310
4311
4312
4313
4314
4315
4316
4317
4318
4319
4320
4321
4322
4323
4324
4325
4326
4327
4328
4329
4330
4331
4332
4333
4334
4335
4336
4337
4338
4339
4340
4341
4342
4343
4344
4345
4346
4347
4348
4349
4350
4351
4352
4353
4354
4355
4356
4357
4358
4359
4360
4361
4362
4363
4364
4365
4366
4367
4368
4369
4370
4371
4372
4373
4374
4375
4376
4377
4378
4379
4380
4381
4382
4383
4384
4385
4386
4387
4388
4389
4390
4391
4392
4393
4394
4395
4396
4397
4398
4399
4400
4401
4402
4403
4404
4405
4406
4407
4408
4409
4410
4411
4412
4413
4414
4415
4416
4417
4418
4419
4420
4421
4422
4423
4424
4425
4426
4427
4428
4429
4430
4431
4432
4433
4434
4435
4436
4437
4438
4439
4440
4441
4442
4443
4444
4445
4446
4447
4448
4449
4450
4451
4452
4453
4454
4455
4456
4457
4458
4459
4460
4461
4462
4463
4464
4465
4466
4467
4468
4469
4470
4471
4472
4473
4474
4475
4476
4477
4478
4479
4480
4481
4482
4483
4484
4485
4486
4487
4488
4489
4490
4491
4492
4493
4494
4495
4496
4497
4498
4499
4500
4501
4502
4503
4504
4505
4506
4507
4508
4509
4510
4511
4512
4513
4514
4515
4516
4517
4518
4519
4520
4521
4522
4523
4524
4525
4526
4527
4528
4529
4530
4531
4532
4533
4534
4535
4536
4537
4538
4539
4540
4541
4542
4543
4544
4545
4546
4547
4548
4549
4550
4551
4552
4553
4554
4555
4556
4557
4558
4559
4560
4561
4562
4563
4564
4565
4566
4567
4568
4569
4570
4571
4572
4573
4574
4575
4576
4577
4578
4579
4580
4581
4582
4583
4584
4585
4586
4587
4588
4589
4590
4591
4592
4593
4594
4595
4596
4597
4598
4599
4600
4601
4602
4603
4604
4605
4606
4607
4608
4609
4610
4611
4612
4613
4614
4615
4616
4617
4618
4619
4620
4621
4622
4623
4624
4625
4626
4627
4628
4629
4630
4631
4632
4633
4634
4635
4636
4637
4638
4639
4640
4641
4642
4643
4644
4645
4646
4647
4648
4649
4650
4651
4652
4653
4654
4655
4656
4657
4658
4659
4660
4661
4662
4663
4664
4665
4666
4667
4668
4669
4670
4671
4672
4673
4674
4675
4676
4677
4678
4679
4680
4681
4682
4683
4684
4685
4686
4687
4688
4689
4690
4691
4692
4693
4694
4695
4696
4697
4698
4699
4700
4701
4702
4703
4704
4705
4706
4707
4708
4709
4710
4711
4712
4713
4714
4715
4716
4717
4718
4719
4720
4721
4722
4723
4724
4725
4726
4727
4728
4729
4730
4731
4732
4733
4734
4735
4736
4737
4738
4739
4740
4741
4742
4743
4744
4745
4746
4747
4748
4749
4750
4751
4752
4753
4754
4755
4756
4757
4758
4759
4760
4761
4762
4763
4764
4765
4766
4767
4768
4769
4770
4771
4772
4773
4774
4775
4776
4777
4778
4779
4780
4781
4782
4783
4784
4785
4786
4787
4788
4789
4790
4791
4792
4793
4794
4795
4796
4797
4798
4799
4800
4801
4802
4803
4804
4805
4806
4807
4808
4809
4810
4811
4812
4813
4814
4815
4816
4817
4818
4819
4820
4821
4822
4823
4824
4825
4826
4827
4828
4829
4830
4831
4832
4833
4834
4835
4836
4837
4838
4839
4840
4841
4842
4843
4844
4845
4846
4847
4848
4849
4850
4851
4852
4853
4854
4855
4856
4857
4858
4859
4860
4861
4862
4863
4864
4865
4866
4867
4868
4869
4870
4871
4872
4873
4874
4875
4876
4877
4878
4879
4880
4881
4882
4883
4884
4885
4886
4887
4888
4889
4890
4891
4892
4893
4894
4895
4896
4897
4898
4899
4900
4901
4902
4903
4904
4905
4906
4907
4908
4909
4910
4911
4912
4913
4914
4915
4916
4917
4918
4919
4920
4921
4922
4923
4924
4925
4926
4927
4928
4929
4930
4931
4932
4933
4934
4935
4936
4937
4938
4939
4940
4941
4942
4943
4944
4945
4946
4947
4948
4949
4950
4951
4952
4953
4954
4955
4956
4957
4958
4959
4960
4961
4962
4963
4964
4965
4966
4967
4968
4969
4970
4971
4972
4973
4974
4975
4976
4977
4978
4979
4980
4981
4982
4983
4984
4985
4986
4987
4988
4989
4990
4991
4992
4993
4994
4995
4996
4997
4998
4999
5000
5001
5002
5003
5004
5005
5006
5007
5008
5009
5010
5011
5012
5013
5014
5015
5016
5017
5018
5019
5020
5021
5022
5023
5024
5025
5026
5027
5028
5029
5030
5031
5032
5033
5034
5035
5036
5037
5038
5039
5040
5041
5042
5043
5044
5045
5046
5047
5048
5049
5050
5051
5052
5053
5054
5055
5056
5057
5058
5059
5060
5061
5062
5063
5064
5065
5066
5067
5068
5069
5070
5071
5072
5073
5074
5075
5076
5077
5078
5079
5080
5081
5082
5083
5084
5085
5086
5087
5088
5089
5090
5091
5092
5093
5094
5095
5096
5097
5098
5099
5100
5101
5102
5103
5104
5105
5106
5107
5108
5109
5110
5111
5112
5113
5114
5115
5116
5117
5118
5119
5120
5121
5122
5123
5124
5125
5126
5127
5128
5129
5130
5131
5132
5133
5134
5135
5136
5137
5138
5139
5140
5141
5142
5143
5144
5145
5146
5147
5148
5149
5150
5151
5152
5153
5154
5155
5156
5157
5158
5159
5160
5161
5162
5163
5164
5165
5166
5167
5168
5169
// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Copyright (c) 2017 Hisilicon Limited.
 */

#include <linux/sched/clock.h>
#include "hisi_sas.h"
#define DRV_NAME "hisi_sas_v3_hw"

/* global registers need init */
#define DLVRY_QUEUE_ENABLE		0x0
#define IOST_BASE_ADDR_LO		0x8
#define IOST_BASE_ADDR_HI		0xc
#define ITCT_BASE_ADDR_LO		0x10
#define ITCT_BASE_ADDR_HI		0x14
#define IO_BROKEN_MSG_ADDR_LO		0x18
#define IO_BROKEN_MSG_ADDR_HI		0x1c
#define PHY_CONTEXT			0x20
#define PHY_STATE			0x24
#define PHY_PORT_NUM_MA			0x28
#define PHY_CONN_RATE			0x30
#define ITCT_CLR			0x44
#define ITCT_CLR_EN_OFF			16
#define ITCT_CLR_EN_MSK			(0x1 << ITCT_CLR_EN_OFF)
#define ITCT_DEV_OFF			0
#define ITCT_DEV_MSK			(0x7ff << ITCT_DEV_OFF)
#define SAS_AXI_USER3			0x50
#define IO_SATA_BROKEN_MSG_ADDR_LO	0x58
#define IO_SATA_BROKEN_MSG_ADDR_HI	0x5c
#define SATA_INITI_D2H_STORE_ADDR_LO	0x60
#define SATA_INITI_D2H_STORE_ADDR_HI	0x64
#define CFG_MAX_TAG			0x68
#define TRANS_LOCK_ICT_TIME		0X70
#define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL	0x84
#define HGC_SAS_TXFAIL_RETRY_CTRL	0x88
#define HGC_GET_ITV_TIME		0x90
#define DEVICE_MSG_WORK_MODE		0x94
#define OPENA_WT_CONTI_TIME		0x9c
#define I_T_NEXUS_LOSS_TIME		0xa0
#define MAX_CON_TIME_LIMIT_TIME		0xa4
#define BUS_INACTIVE_LIMIT_TIME		0xa8
#define REJECT_TO_OPEN_LIMIT_TIME	0xac
#define CQ_INT_CONVERGE_EN		0xb0
#define CFG_AGING_TIME			0xbc
#define HGC_DFX_CFG2			0xc0
#define CFG_ABT_SET_QUERY_IPTT	0xd4
#define CFG_SET_ABORTED_IPTT_OFF	0
#define CFG_SET_ABORTED_IPTT_MSK	(0xfff << CFG_SET_ABORTED_IPTT_OFF)
#define CFG_SET_ABORTED_EN_OFF	12
#define CFG_ABT_SET_IPTT_DONE	0xd8
#define CFG_ABT_SET_IPTT_DONE_OFF	0
#define HGC_IOMB_PROC1_STATUS	0x104
#define HGC_LM_DFX_STATUS2		0x128
#define HGC_LM_DFX_STATUS2_IOSTLIST_OFF		0
#define HGC_LM_DFX_STATUS2_IOSTLIST_MSK	(0xfff << \
					 HGC_LM_DFX_STATUS2_IOSTLIST_OFF)
#define HGC_LM_DFX_STATUS2_ITCTLIST_OFF		12
#define HGC_LM_DFX_STATUS2_ITCTLIST_MSK	(0x7ff << \
					 HGC_LM_DFX_STATUS2_ITCTLIST_OFF)
#define HGC_CQE_ECC_ADDR		0x13c
#define HGC_CQE_ECC_1B_ADDR_OFF	0
#define HGC_CQE_ECC_1B_ADDR_MSK	(0x3f << HGC_CQE_ECC_1B_ADDR_OFF)
#define HGC_CQE_ECC_MB_ADDR_OFF	8
#define HGC_CQE_ECC_MB_ADDR_MSK (0x3f << HGC_CQE_ECC_MB_ADDR_OFF)
#define HGC_IOST_ECC_ADDR		0x140
#define HGC_IOST_ECC_1B_ADDR_OFF	0
#define HGC_IOST_ECC_1B_ADDR_MSK	(0x3ff << HGC_IOST_ECC_1B_ADDR_OFF)
#define HGC_IOST_ECC_MB_ADDR_OFF	16
#define HGC_IOST_ECC_MB_ADDR_MSK	(0x3ff << HGC_IOST_ECC_MB_ADDR_OFF)
#define HGC_DQE_ECC_ADDR		0x144
#define HGC_DQE_ECC_1B_ADDR_OFF	0
#define HGC_DQE_ECC_1B_ADDR_MSK	(0xfff << HGC_DQE_ECC_1B_ADDR_OFF)
#define HGC_DQE_ECC_MB_ADDR_OFF	16
#define HGC_DQE_ECC_MB_ADDR_MSK (0xfff << HGC_DQE_ECC_MB_ADDR_OFF)
#define CHNL_INT_STATUS			0x148
#define TAB_DFX				0x14c
#define HGC_ITCT_ECC_ADDR		0x150
#define HGC_ITCT_ECC_1B_ADDR_OFF		0
#define HGC_ITCT_ECC_1B_ADDR_MSK		(0x3ff << \
						 HGC_ITCT_ECC_1B_ADDR_OFF)
#define HGC_ITCT_ECC_MB_ADDR_OFF		16
#define HGC_ITCT_ECC_MB_ADDR_MSK		(0x3ff << \
						 HGC_ITCT_ECC_MB_ADDR_OFF)
#define HGC_AXI_FIFO_ERR_INFO  0x154
#define AXI_ERR_INFO_OFF               0
#define AXI_ERR_INFO_MSK               (0xff << AXI_ERR_INFO_OFF)
#define FIFO_ERR_INFO_OFF              8
#define FIFO_ERR_INFO_MSK              (0xff << FIFO_ERR_INFO_OFF)
#define TAB_RD_TYPE			0x15c
#define INT_COAL_EN			0x19c
#define OQ_INT_COAL_TIME		0x1a0
#define OQ_INT_COAL_CNT			0x1a4
#define ENT_INT_COAL_TIME		0x1a8
#define ENT_INT_COAL_CNT		0x1ac
#define OQ_INT_SRC			0x1b0
#define OQ_INT_SRC_MSK			0x1b4
#define ENT_INT_SRC1			0x1b8
#define ENT_INT_SRC1_D2H_FIS_CH0_OFF	0
#define ENT_INT_SRC1_D2H_FIS_CH0_MSK	(0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF)
#define ENT_INT_SRC1_D2H_FIS_CH1_OFF	8
#define ENT_INT_SRC1_D2H_FIS_CH1_MSK	(0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF)
#define ENT_INT_SRC2			0x1bc
#define ENT_INT_SRC3			0x1c0
#define ENT_INT_SRC3_WP_DEPTH_OFF		8
#define ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF	9
#define ENT_INT_SRC3_RP_DEPTH_OFF		10
#define ENT_INT_SRC3_AXI_OFF			11
#define ENT_INT_SRC3_FIFO_OFF			12
#define ENT_INT_SRC3_LM_OFF				14
#define ENT_INT_SRC3_ITC_INT_OFF	15
#define ENT_INT_SRC3_ITC_INT_MSK	(0x1 << ENT_INT_SRC3_ITC_INT_OFF)
#define ENT_INT_SRC3_ABT_OFF		16
#define ENT_INT_SRC3_DQE_POISON_OFF	18
#define ENT_INT_SRC3_IOST_POISON_OFF	19
#define ENT_INT_SRC3_ITCT_POISON_OFF	20
#define ENT_INT_SRC3_ITCT_NCQ_POISON_OFF	21
#define ENT_INT_SRC_MSK1		0x1c4
#define ENT_INT_SRC_MSK2		0x1c8
#define ENT_INT_SRC_MSK3		0x1cc
#define ENT_INT_SRC_MSK3_ENT95_MSK_OFF	31
#define CHNL_PHYUPDOWN_INT_MSK		0x1d0
#define CHNL_ENT_INT_MSK			0x1d4
#define HGC_COM_INT_MSK				0x1d8
#define ENT_INT_SRC_MSK3_ENT95_MSK_MSK	(0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF)
#define SAS_ECC_INTR			0x1e8
#define SAS_ECC_INTR_DQE_ECC_1B_OFF		0
#define SAS_ECC_INTR_DQE_ECC_MB_OFF		1
#define SAS_ECC_INTR_IOST_ECC_1B_OFF	2
#define SAS_ECC_INTR_IOST_ECC_MB_OFF	3
#define SAS_ECC_INTR_ITCT_ECC_1B_OFF	4
#define SAS_ECC_INTR_ITCT_ECC_MB_OFF	5
#define SAS_ECC_INTR_ITCTLIST_ECC_1B_OFF	6
#define SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF	7
#define SAS_ECC_INTR_IOSTLIST_ECC_1B_OFF	8
#define SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF	9
#define SAS_ECC_INTR_CQE_ECC_1B_OFF		10
#define SAS_ECC_INTR_CQE_ECC_MB_OFF		11
#define SAS_ECC_INTR_NCQ_MEM0_ECC_1B_OFF	12
#define SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF	13
#define SAS_ECC_INTR_NCQ_MEM1_ECC_1B_OFF	14
#define SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF	15
#define SAS_ECC_INTR_NCQ_MEM2_ECC_1B_OFF	16
#define SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF	17
#define SAS_ECC_INTR_NCQ_MEM3_ECC_1B_OFF	18
#define SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF	19
#define SAS_ECC_INTR_OOO_RAM_ECC_1B_OFF		20
#define SAS_ECC_INTR_OOO_RAM_ECC_MB_OFF		21
#define SAS_ECC_INTR_MSK		0x1ec
#define HGC_ERR_STAT_EN			0x238
#define CQE_SEND_CNT			0x248
#define DLVRY_Q_0_BASE_ADDR_LO		0x260
#define DLVRY_Q_0_BASE_ADDR_HI		0x264
#define DLVRY_Q_0_DEPTH			0x268
#define DLVRY_Q_0_WR_PTR		0x26c
#define DLVRY_Q_0_RD_PTR		0x270
#define HYPER_STREAM_ID_EN_CFG		0xc80
#define OQ0_INT_SRC_MSK			0xc90
#define COMPL_Q_0_BASE_ADDR_LO		0x4e0
#define COMPL_Q_0_BASE_ADDR_HI		0x4e4
#define COMPL_Q_0_DEPTH			0x4e8
#define COMPL_Q_0_WR_PTR		0x4ec
#define COMPL_Q_0_RD_PTR		0x4f0
#define HGC_RXM_DFX_STATUS14		0xae8
#define HGC_RXM_DFX_STATUS14_MEM0_OFF	0
#define HGC_RXM_DFX_STATUS14_MEM0_MSK	(0x1ff << \
					 HGC_RXM_DFX_STATUS14_MEM0_OFF)
#define HGC_RXM_DFX_STATUS14_MEM1_OFF	9
#define HGC_RXM_DFX_STATUS14_MEM1_MSK	(0x1ff << \
					 HGC_RXM_DFX_STATUS14_MEM1_OFF)
#define HGC_RXM_DFX_STATUS14_MEM2_OFF	18
#define HGC_RXM_DFX_STATUS14_MEM2_MSK	(0x1ff << \
					 HGC_RXM_DFX_STATUS14_MEM2_OFF)
#define HGC_RXM_DFX_STATUS15		0xaec
#define HGC_RXM_DFX_STATUS15_MEM3_OFF	0
#define HGC_RXM_DFX_STATUS15_MEM3_MSK	(0x1ff << \
					 HGC_RXM_DFX_STATUS15_MEM3_OFF)
#define AWQOS_AWCACHE_CFG	0xc84
#define ARQOS_ARCACHE_CFG	0xc88
#define HILINK_ERR_DFX		0xe04
#define SAS_GPIO_CFG_0		0x1000
#define SAS_GPIO_CFG_1		0x1004
#define SAS_GPIO_TX_0_1	0x1040
#define SAS_CFG_DRIVE_VLD	0x1070

/* phy registers requiring init */
#define PORT_BASE			(0x2000)
#define PHY_CFG				(PORT_BASE + 0x0)
#define HARD_PHY_LINKRATE		(PORT_BASE + 0x4)
#define PHY_CFG_ENA_OFF			0
#define PHY_CFG_ENA_MSK			(0x1 << PHY_CFG_ENA_OFF)
#define PHY_CFG_DC_OPT_OFF		2
#define PHY_CFG_DC_OPT_MSK		(0x1 << PHY_CFG_DC_OPT_OFF)
#define PHY_CFG_PHY_RST_OFF		3
#define PHY_CFG_PHY_RST_MSK		(0x1 << PHY_CFG_PHY_RST_OFF)
#define PROG_PHY_LINK_RATE		(PORT_BASE + 0x8)
#define CFG_PROG_PHY_LINK_RATE_OFF	0
#define CFG_PROG_PHY_LINK_RATE_MSK	(0xff << CFG_PROG_PHY_LINK_RATE_OFF)
#define CFG_PROG_OOB_PHY_LINK_RATE_OFF	8
#define CFG_PROG_OOB_PHY_LINK_RATE_MSK	(0xf << CFG_PROG_OOB_PHY_LINK_RATE_OFF)
#define PHY_CTRL			(PORT_BASE + 0x14)
#define PHY_CTRL_RESET_OFF		0
#define PHY_CTRL_RESET_MSK		(0x1 << PHY_CTRL_RESET_OFF)
#define CMD_HDR_PIR_OFF			8
#define CMD_HDR_PIR_MSK			(0x1 << CMD_HDR_PIR_OFF)
#define SERDES_CFG			(PORT_BASE + 0x1c)
#define CFG_ALOS_CHK_DISABLE_OFF	9
#define CFG_ALOS_CHK_DISABLE_MSK	(0x1 << CFG_ALOS_CHK_DISABLE_OFF)
#define SAS_PHY_BIST_CTRL		(PORT_BASE + 0x2c)
#define CFG_BIST_MODE_SEL_OFF		0
#define CFG_BIST_MODE_SEL_MSK		(0xf << CFG_BIST_MODE_SEL_OFF)
#define CFG_LOOP_TEST_MODE_OFF		14
#define CFG_LOOP_TEST_MODE_MSK		(0x3 << CFG_LOOP_TEST_MODE_OFF)
#define CFG_RX_BIST_EN_OFF		16
#define CFG_RX_BIST_EN_MSK		(0x1 << CFG_RX_BIST_EN_OFF)
#define CFG_TX_BIST_EN_OFF		17
#define CFG_TX_BIST_EN_MSK		(0x1 << CFG_TX_BIST_EN_OFF)
#define CFG_BIST_TEST_OFF		18
#define CFG_BIST_TEST_MSK		(0x1 << CFG_BIST_TEST_OFF)
#define SAS_PHY_BIST_CODE		(PORT_BASE + 0x30)
#define SAS_PHY_BIST_CODE1		(PORT_BASE + 0x34)
#define SAS_BIST_ERR_CNT		(PORT_BASE + 0x38)
#define SL_CFG				(PORT_BASE + 0x84)
#define AIP_LIMIT			(PORT_BASE + 0x90)
#define SL_CONTROL			(PORT_BASE + 0x94)
#define SL_CONTROL_NOTIFY_EN_OFF	0
#define SL_CONTROL_NOTIFY_EN_MSK	(0x1 << SL_CONTROL_NOTIFY_EN_OFF)
#define SL_CTA_OFF		17
#define SL_CTA_MSK		(0x1 << SL_CTA_OFF)
#define RX_PRIMS_STATUS			(PORT_BASE + 0x98)
#define RX_BCAST_CHG_OFF		1
#define RX_BCAST_CHG_MSK		(0x1 << RX_BCAST_CHG_OFF)
#define TX_ID_DWORD0			(PORT_BASE + 0x9c)
#define TX_ID_DWORD1			(PORT_BASE + 0xa0)
#define TX_ID_DWORD2			(PORT_BASE + 0xa4)
#define TX_ID_DWORD3			(PORT_BASE + 0xa8)
#define TX_ID_DWORD4			(PORT_BASE + 0xaC)
#define TX_ID_DWORD5			(PORT_BASE + 0xb0)
#define TX_ID_DWORD6			(PORT_BASE + 0xb4)
#define TXID_AUTO				(PORT_BASE + 0xb8)
#define CT3_OFF		1
#define CT3_MSK		(0x1 << CT3_OFF)
#define TX_HARDRST_OFF          2
#define TX_HARDRST_MSK          (0x1 << TX_HARDRST_OFF)
#define RX_IDAF_DWORD0			(PORT_BASE + 0xc4)
#define RXOP_CHECK_CFG_H		(PORT_BASE + 0xfc)
#define STP_LINK_TIMER			(PORT_BASE + 0x120)
#define STP_LINK_TIMEOUT_STATE		(PORT_BASE + 0x124)
#define CON_CFG_DRIVER			(PORT_BASE + 0x130)
#define SAS_SSP_CON_TIMER_CFG		(PORT_BASE + 0x134)
#define SAS_SMP_CON_TIMER_CFG		(PORT_BASE + 0x138)
#define SAS_STP_CON_TIMER_CFG		(PORT_BASE + 0x13c)
#define CHL_INT0			(PORT_BASE + 0x1b4)
#define CHL_INT0_HOTPLUG_TOUT_OFF	0
#define CHL_INT0_HOTPLUG_TOUT_MSK	(0x1 << CHL_INT0_HOTPLUG_TOUT_OFF)
#define CHL_INT0_SL_RX_BCST_ACK_OFF	1
#define CHL_INT0_SL_RX_BCST_ACK_MSK	(0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF)
#define CHL_INT0_SL_PHY_ENABLE_OFF	2
#define CHL_INT0_SL_PHY_ENABLE_MSK	(0x1 << CHL_INT0_SL_PHY_ENABLE_OFF)
#define CHL_INT0_NOT_RDY_OFF		4
#define CHL_INT0_NOT_RDY_MSK		(0x1 << CHL_INT0_NOT_RDY_OFF)
#define CHL_INT0_PHY_RDY_OFF		5
#define CHL_INT0_PHY_RDY_MSK		(0x1 << CHL_INT0_PHY_RDY_OFF)
#define CHL_INT1			(PORT_BASE + 0x1b8)
#define CHL_INT1_DMAC_TX_ECC_MB_ERR_OFF	15
#define CHL_INT1_DMAC_TX_ECC_1B_ERR_OFF	16
#define CHL_INT1_DMAC_RX_ECC_MB_ERR_OFF	17
#define CHL_INT1_DMAC_RX_ECC_1B_ERR_OFF	18
#define CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF	19
#define CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF	20
#define CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF	21
#define CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF	22
#define CHL_INT1_DMAC_TX_FIFO_ERR_OFF	23
#define CHL_INT1_DMAC_RX_FIFO_ERR_OFF	24
#define CHL_INT1_DMAC_TX_AXI_RUSER_ERR_OFF	26
#define CHL_INT1_DMAC_RX_AXI_RUSER_ERR_OFF	27
#define CHL_INT2			(PORT_BASE + 0x1bc)
#define CHL_INT2_SL_IDAF_TOUT_CONF_OFF	0
#define CHL_INT2_RX_DISP_ERR_OFF	28
#define CHL_INT2_RX_CODE_ERR_OFF	29
#define CHL_INT2_RX_INVLD_DW_OFF	30
#define CHL_INT2_STP_LINK_TIMEOUT_OFF	31
#define CHL_INT0_MSK			(PORT_BASE + 0x1c0)
#define CHL_INT1_MSK			(PORT_BASE + 0x1c4)
#define CHL_INT2_MSK			(PORT_BASE + 0x1c8)
#define SAS_EC_INT_COAL_TIME		(PORT_BASE + 0x1cc)
#define CHL_INT_COAL_EN			(PORT_BASE + 0x1d0)
#define SAS_RX_TRAIN_TIMER		(PORT_BASE + 0x2a4)
#define PHY_CTRL_RDY_MSK		(PORT_BASE + 0x2b0)
#define PHYCTRL_NOT_RDY_MSK		(PORT_BASE + 0x2b4)
#define PHYCTRL_DWS_RESET_MSK		(PORT_BASE + 0x2b8)
#define PHYCTRL_PHY_ENA_MSK		(PORT_BASE + 0x2bc)
#define SL_RX_BCAST_CHK_MSK		(PORT_BASE + 0x2c0)
#define PHYCTRL_OOB_RESTART_MSK		(PORT_BASE + 0x2c4)
#define DMA_TX_STATUS			(PORT_BASE + 0x2d0)
#define DMA_TX_STATUS_BUSY_OFF		0
#define DMA_TX_STATUS_BUSY_MSK		(0x1 << DMA_TX_STATUS_BUSY_OFF)
#define DMA_RX_STATUS			(PORT_BASE + 0x2e8)
#define DMA_RX_STATUS_BUSY_OFF		0
#define DMA_RX_STATUS_BUSY_MSK		(0x1 << DMA_RX_STATUS_BUSY_OFF)

#define COARSETUNE_TIME			(PORT_BASE + 0x304)
#define TXDEEMPH_G1			(PORT_BASE + 0x350)
#define ERR_CNT_DWS_LOST		(PORT_BASE + 0x380)
#define ERR_CNT_RESET_PROB		(PORT_BASE + 0x384)
#define ERR_CNT_INVLD_DW		(PORT_BASE + 0x390)
#define ERR_CNT_CODE_ERR		(PORT_BASE + 0x394)
#define ERR_CNT_DISP_ERR		(PORT_BASE + 0x398)
#define DFX_FIFO_CTRL			(PORT_BASE + 0x3a0)
#define DFX_FIFO_CTRL_TRIGGER_MODE_OFF	0
#define DFX_FIFO_CTRL_TRIGGER_MODE_MSK	(0x7 << DFX_FIFO_CTRL_TRIGGER_MODE_OFF)
#define DFX_FIFO_CTRL_DUMP_MODE_OFF	3
#define DFX_FIFO_CTRL_DUMP_MODE_MSK	(0x7 << DFX_FIFO_CTRL_DUMP_MODE_OFF)
#define DFX_FIFO_CTRL_SIGNAL_SEL_OFF	6
#define DFX_FIFO_CTRL_SIGNAL_SEL_MSK	(0xF << DFX_FIFO_CTRL_SIGNAL_SEL_OFF)
#define DFX_FIFO_CTRL_DUMP_DISABLE_OFF	10
#define DFX_FIFO_CTRL_DUMP_DISABLE_MSK	(0x1 << DFX_FIFO_CTRL_DUMP_DISABLE_OFF)
#define DFX_FIFO_TRIGGER		(PORT_BASE + 0x3a4)
#define DFX_FIFO_TRIGGER_MSK		(PORT_BASE + 0x3a8)
#define DFX_FIFO_DUMP_MSK		(PORT_BASE + 0x3aC)
#define DFX_FIFO_RD_DATA		(PORT_BASE + 0x3b0)

#define DEFAULT_ITCT_HW		2048 /* reset value, not reprogrammed */
#if (HISI_SAS_MAX_DEVICES > DEFAULT_ITCT_HW)
#error Max ITCT exceeded
#endif

#define AXI_MASTER_CFG_BASE		(0x5000)
#define AM_CTRL_GLOBAL			(0x0)
#define AM_CTRL_SHUTDOWN_REQ_OFF	0
#define AM_CTRL_SHUTDOWN_REQ_MSK	(0x1 << AM_CTRL_SHUTDOWN_REQ_OFF)
#define AM_CURR_TRANS_RETURN	(0x150)

#define AM_CFG_MAX_TRANS		(0x5010)
#define AM_CFG_SINGLE_PORT_MAX_TRANS	(0x5014)
#define AXI_CFG					(0x5100)
#define AM_ROB_ECC_ERR_ADDR		(0x510c)
#define AM_ROB_ECC_ERR_ADDR_OFF	0
#define AM_ROB_ECC_ERR_ADDR_MSK	0xffffffff

/* RAS registers need init */
#define RAS_BASE		(0x6000)
#define SAS_RAS_INTR0			(RAS_BASE)
#define SAS_RAS_INTR1			(RAS_BASE + 0x04)
#define SAS_RAS_INTR0_MASK		(RAS_BASE + 0x08)
#define SAS_RAS_INTR1_MASK		(RAS_BASE + 0x0c)
#define CFG_SAS_RAS_INTR_MASK		(RAS_BASE + 0x1c)
#define SAS_RAS_INTR2			(RAS_BASE + 0x20)
#define SAS_RAS_INTR2_MASK		(RAS_BASE + 0x24)

/* HW dma structures */
/* Delivery queue header */
/* dw0 */
#define CMD_HDR_ABORT_FLAG_OFF		0
#define CMD_HDR_ABORT_FLAG_MSK		(0x3 << CMD_HDR_ABORT_FLAG_OFF)
#define CMD_HDR_ABORT_DEVICE_TYPE_OFF	2
#define CMD_HDR_ABORT_DEVICE_TYPE_MSK	(0x1 << CMD_HDR_ABORT_DEVICE_TYPE_OFF)
#define CMD_HDR_RESP_REPORT_OFF		5
#define CMD_HDR_RESP_REPORT_MSK		(0x1 << CMD_HDR_RESP_REPORT_OFF)
#define CMD_HDR_TLR_CTRL_OFF		6
#define CMD_HDR_TLR_CTRL_MSK		(0x3 << CMD_HDR_TLR_CTRL_OFF)
#define CMD_HDR_PORT_OFF		18
#define CMD_HDR_PORT_MSK		(0xf << CMD_HDR_PORT_OFF)
#define CMD_HDR_PRIORITY_OFF		27
#define CMD_HDR_PRIORITY_MSK		(0x1 << CMD_HDR_PRIORITY_OFF)
#define CMD_HDR_CMD_OFF			29
#define CMD_HDR_CMD_MSK			(0x7 << CMD_HDR_CMD_OFF)
/* dw1 */
#define CMD_HDR_UNCON_CMD_OFF	3
#define CMD_HDR_DIR_OFF			5
#define CMD_HDR_DIR_MSK			(0x3 << CMD_HDR_DIR_OFF)
#define CMD_HDR_RESET_OFF		7
#define CMD_HDR_RESET_MSK		(0x1 << CMD_HDR_RESET_OFF)
#define CMD_HDR_VDTL_OFF		10
#define CMD_HDR_VDTL_MSK		(0x1 << CMD_HDR_VDTL_OFF)
#define CMD_HDR_FRAME_TYPE_OFF		11
#define CMD_HDR_FRAME_TYPE_MSK		(0x1f << CMD_HDR_FRAME_TYPE_OFF)
#define CMD_HDR_DEV_ID_OFF		16
#define CMD_HDR_DEV_ID_MSK		(0xffff << CMD_HDR_DEV_ID_OFF)
/* dw2 */
#define CMD_HDR_CFL_OFF			0
#define CMD_HDR_CFL_MSK			(0x1ff << CMD_HDR_CFL_OFF)
#define CMD_HDR_NCQ_TAG_OFF		10
#define CMD_HDR_NCQ_TAG_MSK		(0x1f << CMD_HDR_NCQ_TAG_OFF)
#define CMD_HDR_MRFL_OFF		15
#define CMD_HDR_MRFL_MSK		(0x1ff << CMD_HDR_MRFL_OFF)
#define CMD_HDR_SG_MOD_OFF		24
#define CMD_HDR_SG_MOD_MSK		(0x3 << CMD_HDR_SG_MOD_OFF)
/* dw3 */
#define CMD_HDR_IPTT_OFF		0
#define CMD_HDR_IPTT_MSK		(0xffff << CMD_HDR_IPTT_OFF)
/* dw6 */
#define CMD_HDR_DIF_SGL_LEN_OFF		0
#define CMD_HDR_DIF_SGL_LEN_MSK		(0xffff << CMD_HDR_DIF_SGL_LEN_OFF)
#define CMD_HDR_DATA_SGL_LEN_OFF	16
#define CMD_HDR_DATA_SGL_LEN_MSK	(0xffff << CMD_HDR_DATA_SGL_LEN_OFF)
/* dw7 */
#define CMD_HDR_ADDR_MODE_SEL_OFF		15
#define CMD_HDR_ADDR_MODE_SEL_MSK		(1 << CMD_HDR_ADDR_MODE_SEL_OFF)
#define CMD_HDR_ABORT_IPTT_OFF		16
#define CMD_HDR_ABORT_IPTT_MSK		(0xffff << CMD_HDR_ABORT_IPTT_OFF)

/* Completion header */
/* dw0 */
#define CMPLT_HDR_CMPLT_OFF		0
#define CMPLT_HDR_CMPLT_MSK		(0x3 << CMPLT_HDR_CMPLT_OFF)
#define CMPLT_HDR_ERROR_PHASE_OFF   2
#define CMPLT_HDR_ERROR_PHASE_MSK   (0xff << CMPLT_HDR_ERROR_PHASE_OFF)
/* bit[9:2] Error Phase */
#define ERR_PHASE_RESPONSE_FRAME_REV_STAGE_OFF	\
					8
#define ERR_PHASE_RESPONSE_FRAME_REV_STAGE_MSK	\
	(0x1 << ERR_PHASE_RESPONSE_FRAME_REV_STAGE_OFF)
#define CMPLT_HDR_RSPNS_XFRD_OFF	10
#define CMPLT_HDR_RSPNS_XFRD_MSK	(0x1 << CMPLT_HDR_RSPNS_XFRD_OFF)
#define CMPLT_HDR_RSPNS_GOOD_OFF	11
#define CMPLT_HDR_RSPNS_GOOD_MSK	(0x1 << CMPLT_HDR_RSPNS_GOOD_OFF)
#define CMPLT_HDR_ERX_OFF		12
#define CMPLT_HDR_ERX_MSK		(0x1 << CMPLT_HDR_ERX_OFF)
#define CMPLT_HDR_ABORT_STAT_OFF	13
#define CMPLT_HDR_ABORT_STAT_MSK	(0x7 << CMPLT_HDR_ABORT_STAT_OFF)
/* abort_stat */
#define STAT_IO_NOT_VALID		0x1
#define STAT_IO_NO_DEVICE		0x2
#define STAT_IO_COMPLETE		0x3
#define STAT_IO_ABORTED			0x4
/* dw1 */
#define CMPLT_HDR_IPTT_OFF		0
#define CMPLT_HDR_IPTT_MSK		(0xffff << CMPLT_HDR_IPTT_OFF)
#define CMPLT_HDR_DEV_ID_OFF		16
#define CMPLT_HDR_DEV_ID_MSK		(0xffff << CMPLT_HDR_DEV_ID_OFF)
/* dw3 */
#define SATA_DISK_IN_ERROR_STATUS_OFF	8
#define SATA_DISK_IN_ERROR_STATUS_MSK	(0x1 << SATA_DISK_IN_ERROR_STATUS_OFF)
#define CMPLT_HDR_SATA_DISK_ERR_OFF	16
#define CMPLT_HDR_SATA_DISK_ERR_MSK	(0x1 << CMPLT_HDR_SATA_DISK_ERR_OFF)
#define CMPLT_HDR_IO_IN_TARGET_OFF	17
#define CMPLT_HDR_IO_IN_TARGET_MSK	(0x1 << CMPLT_HDR_IO_IN_TARGET_OFF)
/* bit[23:18] ERR_FIS_ATA_STATUS */
#define FIS_ATA_STATUS_ERR_OFF		18
#define FIS_ATA_STATUS_ERR_MSK		(0x1 << FIS_ATA_STATUS_ERR_OFF)
#define FIS_TYPE_SDB_OFF		31
#define FIS_TYPE_SDB_MSK		(0x1 << FIS_TYPE_SDB_OFF)

/* ITCT header */
/* qw0 */
#define ITCT_HDR_DEV_TYPE_OFF		0
#define ITCT_HDR_DEV_TYPE_MSK		(0x3 << ITCT_HDR_DEV_TYPE_OFF)
#define ITCT_HDR_VALID_OFF		2
#define ITCT_HDR_VALID_MSK		(0x1 << ITCT_HDR_VALID_OFF)
#define ITCT_HDR_MCR_OFF		5
#define ITCT_HDR_MCR_MSK		(0xf << ITCT_HDR_MCR_OFF)
#define ITCT_HDR_VLN_OFF		9
#define ITCT_HDR_VLN_MSK		(0xf << ITCT_HDR_VLN_OFF)
#define ITCT_HDR_SMP_TIMEOUT_OFF	16
#define ITCT_HDR_AWT_CONTINUE_OFF	25
#define ITCT_HDR_PORT_ID_OFF		28
#define ITCT_HDR_PORT_ID_MSK		(0xf << ITCT_HDR_PORT_ID_OFF)
/* qw2 */
#define ITCT_HDR_INLT_OFF		0
#define ITCT_HDR_INLT_MSK		(0xffffULL << ITCT_HDR_INLT_OFF)
#define ITCT_HDR_RTOLT_OFF		48
#define ITCT_HDR_RTOLT_MSK		(0xffffULL << ITCT_HDR_RTOLT_OFF)

struct hisi_sas_protect_iu_v3_hw {
	u32 dw0;
	u32 lbrtcv;
	u32 lbrtgv;
	u32 dw3;
	u32 dw4;
	u32 dw5;
	u32 rsv;
};

struct hisi_sas_complete_v3_hdr {
	__le32 dw0;
	__le32 dw1;
	__le32 act;
	__le32 dw3;
};

struct hisi_sas_err_record_v3 {
	/* dw0 */
	__le32 trans_tx_fail_type;

	/* dw1 */
	__le32 trans_rx_fail_type;

	/* dw2 */
	__le16 dma_tx_err_type;
	__le16 sipc_rx_err_type;

	/* dw3 */
	__le32 dma_rx_err_type;
};

#define RX_DATA_LEN_UNDERFLOW_OFF	6
#define RX_DATA_LEN_UNDERFLOW_MSK	(1 << RX_DATA_LEN_UNDERFLOW_OFF)

#define RX_FIS_STATUS_ERR_OFF		0
#define RX_FIS_STATUS_ERR_MSK		(1 << RX_FIS_STATUS_ERR_OFF)

#define HISI_SAS_COMMAND_ENTRIES_V3_HW 4096
#define HISI_SAS_MSI_COUNT_V3_HW 32

#define DIR_NO_DATA 0
#define DIR_TO_INI 1
#define DIR_TO_DEVICE 2
#define DIR_RESERVED 3

#define FIS_CMD_IS_UNCONSTRAINED(fis) \
	((fis.command == ATA_CMD_READ_LOG_EXT) || \
	(fis.command == ATA_CMD_READ_LOG_DMA_EXT) || \
	((fis.command == ATA_CMD_DEV_RESET) && \
	((fis.control & ATA_SRST) != 0)))

#define T10_INSRT_EN_OFF    0
#define T10_INSRT_EN_MSK    (1 << T10_INSRT_EN_OFF)
#define T10_RMV_EN_OFF	    1
#define T10_RMV_EN_MSK	    (1 << T10_RMV_EN_OFF)
#define T10_RPLC_EN_OFF	    2
#define T10_RPLC_EN_MSK	    (1 << T10_RPLC_EN_OFF)
#define T10_CHK_EN_OFF	    3
#define T10_CHK_EN_MSK	    (1 << T10_CHK_EN_OFF)
#define INCR_LBRT_OFF	    5
#define INCR_LBRT_MSK	    (1 << INCR_LBRT_OFF)
#define USR_DATA_BLOCK_SZ_OFF	20
#define USR_DATA_BLOCK_SZ_MSK	(0x3 << USR_DATA_BLOCK_SZ_OFF)
#define T10_CHK_MSK_OFF	    16
#define T10_CHK_REF_TAG_MSK (0xf0 << T10_CHK_MSK_OFF)
#define T10_CHK_APP_TAG_MSK (0xc << T10_CHK_MSK_OFF)

#define BASE_VECTORS_V3_HW  16
#define MIN_AFFINE_VECTORS_V3_HW  (BASE_VECTORS_V3_HW + 1)

#define CHNL_INT_STS_MSK	0xeeeeeeee
#define CHNL_INT_STS_PHY_MSK	0xe
#define CHNL_INT_STS_INT0_MSK BIT(1)
#define CHNL_INT_STS_INT1_MSK BIT(2)
#define CHNL_INT_STS_INT2_MSK BIT(3)
#define CHNL_WIDTH 4

#define BAR_NO_V3_HW	5

enum {
	DSM_FUNC_ERR_HANDLE_MSI = 0,
};

static bool hisi_sas_intr_conv;
MODULE_PARM_DESC(intr_conv, "interrupt converge enable (0-1)");

/* permit overriding the host protection capabilities mask (EEDP/T10 PI) */
static int prot_mask;
module_param(prot_mask, int, 0444);
MODULE_PARM_DESC(prot_mask, " host protection capabilities mask, def=0x0 ");

/* the index of iopoll queues are bigger than interrupt queues' */
static int experimental_iopoll_q_cnt;
module_param(experimental_iopoll_q_cnt, int, 0444);
MODULE_PARM_DESC(experimental_iopoll_q_cnt, "number of queues to be used as poll mode, def=0");

static int debugfs_snapshot_regs_v3_hw(struct hisi_hba *hisi_hba);

static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off)
{
	void __iomem *regs = hisi_hba->regs + off;

	return readl(regs);
}

static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val)
{
	void __iomem *regs = hisi_hba->regs + off;

	writel(val, regs);
}

static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no,
				 u32 off, u32 val)
{
	void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;

	writel(val, regs);
}

static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba,
				      int phy_no, u32 off)
{
	void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;

	return readl(regs);
}

#define hisi_sas_read32_poll_timeout(off, val, cond, delay_us,		\
				     timeout_us)			\
({									\
	void __iomem *regs = hisi_hba->regs + off;			\
	readl_poll_timeout(regs, val, cond, delay_us, timeout_us);	\
})

#define hisi_sas_read32_poll_timeout_atomic(off, val, cond, delay_us,	\
					    timeout_us)			\
({									\
	void __iomem *regs = hisi_hba->regs + off;			\
	readl_poll_timeout_atomic(regs, val, cond, delay_us, timeout_us);\
})

static void interrupt_enable_v3_hw(struct hisi_hba *hisi_hba)
{
	int i;

	for (i = 0; i < hisi_hba->queue_count; i++)
		hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK + 0x4 * i, 0);

	hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xfefefefe);
	hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xfefefefe);
	hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffc220ff);
	hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0x155555);

	for (i = 0; i < hisi_hba->n_phy; i++) {
		hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xf2057fff);
		hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffbfe);
		hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x0);
		hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x0);
		hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x0);
	}
}

static void init_reg_v3_hw(struct hisi_hba *hisi_hba)
{
	struct pci_dev *pdev = hisi_hba->pci_dev;
	int i, j;

	/* Global registers init */
	hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE,
			 (u32)((1ULL << hisi_hba->queue_count) - 1));
	hisi_sas_write32(hisi_hba, CFG_MAX_TAG, 0xfff0400);
	/* time / CLK_AHB = 2.5s / 2ns = 0x4A817C80 */
	hisi_sas_write32(hisi_hba, TRANS_LOCK_ICT_TIME, 0x4A817C80);
	hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x108);
	hisi_sas_write32(hisi_hba, CFG_AGING_TIME, 0x1);
	hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1);
	hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x1);
	hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x1);
	hisi_sas_write32(hisi_hba, CQ_INT_CONVERGE_EN,
			 hisi_sas_intr_conv);
	hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0xffff);
	hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff);
	hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff);
	hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 0xffffffff);
	hisi_sas_write32(hisi_hba, CHNL_PHYUPDOWN_INT_MSK, 0x0);
	hisi_sas_write32(hisi_hba, CHNL_ENT_INT_MSK, 0x0);
	hisi_sas_write32(hisi_hba, HGC_COM_INT_MSK, 0x0);
	hisi_sas_write32(hisi_hba, AWQOS_AWCACHE_CFG, 0xf0f0);
	hisi_sas_write32(hisi_hba, ARQOS_ARCACHE_CFG, 0xf0f0);
	hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, 1);

	if (pdev->revision < 0x30)
		hisi_sas_write32(hisi_hba, SAS_AXI_USER3, 0);

	interrupt_enable_v3_hw(hisi_hba);
	for (i = 0; i < hisi_hba->n_phy; i++) {
		enum sas_linkrate max;
		struct hisi_sas_phy *phy = &hisi_hba->phy[i];
		struct asd_sas_phy *sas_phy = &phy->sas_phy;
		u32 prog_phy_link_rate = hisi_sas_phy_read32(hisi_hba, i,
							   PROG_PHY_LINK_RATE);

		prog_phy_link_rate &= ~CFG_PROG_PHY_LINK_RATE_MSK;
		if (!sas_phy->phy || (sas_phy->phy->maximum_linkrate <
				SAS_LINK_RATE_1_5_GBPS))
			max = SAS_LINK_RATE_12_0_GBPS;
		else
			max = sas_phy->phy->maximum_linkrate;
		prog_phy_link_rate |= hisi_sas_get_prog_phy_linkrate_mask(max);
		hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE,
			prog_phy_link_rate);
		hisi_sas_phy_write32(hisi_hba, i, SAS_RX_TRAIN_TIMER, 0x13e80);
		hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff);
		hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff);
		hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, 0xffffffff);
		hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000);
		hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL_RDY_MSK, 0x0);
		hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_DWS_RESET_MSK, 0x0);
		hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x1);
		hisi_sas_phy_write32(hisi_hba, i, STP_LINK_TIMER, 0x7f7a120);
		hisi_sas_phy_write32(hisi_hba, i, CON_CFG_DRIVER, 0x2a0a01);
		hisi_sas_phy_write32(hisi_hba, i, SAS_EC_INT_COAL_TIME,
				     0x30f4240);
		hisi_sas_phy_write32(hisi_hba, i, AIP_LIMIT, 0x2ffff);

		/* set value through firmware for 920B and later version */
		if (pdev->revision < 0x30) {
			hisi_sas_phy_write32(hisi_hba, i, SAS_SSP_CON_TIMER_CFG, 0x32);
			hisi_sas_phy_write32(hisi_hba, i, SERDES_CFG, 0xffc00);
			/* used for 12G negotiate */
			hisi_sas_phy_write32(hisi_hba, i, COARSETUNE_TIME, 0x1e);
		}

		/* get default FFE configuration for BIST */
		for (j = 0; j < FFE_CFG_MAX; j++) {
			u32 val = hisi_sas_phy_read32(hisi_hba, i,
						      TXDEEMPH_G1 + (j * 0x4));
			hisi_hba->debugfs_bist_ffe[i][j] = val;
		}
	}

	for (i = 0; i < hisi_hba->queue_count; i++) {
		/* Delivery queue */
		hisi_sas_write32(hisi_hba,
				 DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14),
				 upper_32_bits(hisi_hba->cmd_hdr_dma[i]));

		hisi_sas_write32(hisi_hba, DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14),
				 lower_32_bits(hisi_hba->cmd_hdr_dma[i]));

		hisi_sas_write32(hisi_hba, DLVRY_Q_0_DEPTH + (i * 0x14),
				 HISI_SAS_QUEUE_SLOTS);

		/* Completion queue */
		hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_HI + (i * 0x14),
				 upper_32_bits(hisi_hba->complete_hdr_dma[i]));

		hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_LO + (i * 0x14),
				 lower_32_bits(hisi_hba->complete_hdr_dma[i]));

		hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14),
				 HISI_SAS_QUEUE_SLOTS);
	}

	/* itct */
	hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO,
			 lower_32_bits(hisi_hba->itct_dma));

	hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI,
			 upper_32_bits(hisi_hba->itct_dma));

	/* iost */
	hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO,
			 lower_32_bits(hisi_hba->iost_dma));

	hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI,
			 upper_32_bits(hisi_hba->iost_dma));

	/* breakpoint */
	hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_LO,
			 lower_32_bits(hisi_hba->breakpoint_dma));

	hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_HI,
			 upper_32_bits(hisi_hba->breakpoint_dma));

	/* SATA broken msg */
	hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_LO,
			 lower_32_bits(hisi_hba->sata_breakpoint_dma));

	hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_HI,
			 upper_32_bits(hisi_hba->sata_breakpoint_dma));

	/* SATA initial fis */
	hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_LO,
			 lower_32_bits(hisi_hba->initial_fis_dma));

	hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_HI,
			 upper_32_bits(hisi_hba->initial_fis_dma));

	/* RAS registers init */
	hisi_sas_write32(hisi_hba, SAS_RAS_INTR0_MASK, 0x0);
	hisi_sas_write32(hisi_hba, SAS_RAS_INTR1_MASK, 0x0);
	hisi_sas_write32(hisi_hba, SAS_RAS_INTR2_MASK, 0x0);
	hisi_sas_write32(hisi_hba, CFG_SAS_RAS_INTR_MASK, 0x0);

	/* LED registers init */
	hisi_sas_write32(hisi_hba, SAS_CFG_DRIVE_VLD, 0x80000ff);
	hisi_sas_write32(hisi_hba, SAS_GPIO_TX_0_1, 0x80808080);
	hisi_sas_write32(hisi_hba, SAS_GPIO_TX_0_1 + 0x4, 0x80808080);
	/* Configure blink generator rate A to 1Hz and B to 4Hz */
	hisi_sas_write32(hisi_hba, SAS_GPIO_CFG_1, 0x121700);
	hisi_sas_write32(hisi_hba, SAS_GPIO_CFG_0, 0x800000);
}

static void config_phy_opt_mode_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
{
	u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);

	cfg &= ~PHY_CFG_DC_OPT_MSK;
	cfg |= 1 << PHY_CFG_DC_OPT_OFF;
	hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
}

static void config_id_frame_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
{
	struct sas_identify_frame identify_frame;
	u32 *identify_buffer;

	memset(&identify_frame, 0, sizeof(identify_frame));
	identify_frame.dev_type = SAS_END_DEVICE;
	identify_frame.frame_type = 0;
	identify_frame._un1 = 1;
	identify_frame.initiator_bits = SAS_PROTOCOL_ALL;
	identify_frame.target_bits = SAS_PROTOCOL_NONE;
	memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
	memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr,	SAS_ADDR_SIZE);
	identify_frame.phy_id = phy_no;
	identify_buffer = (u32 *)(&identify_frame);

	hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0,
			__swab32(identify_buffer[0]));
	hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1,
			__swab32(identify_buffer[1]));
	hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2,
			__swab32(identify_buffer[2]));
	hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3,
			__swab32(identify_buffer[3]));
	hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4,
			__swab32(identify_buffer[4]));
	hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5,
			__swab32(identify_buffer[5]));
}

static void setup_itct_v3_hw(struct hisi_hba *hisi_hba,
			     struct hisi_sas_device *sas_dev)
{
	struct domain_device *device = sas_dev->sas_device;
	struct device *dev = hisi_hba->dev;
	u64 qw0, device_id = sas_dev->device_id;
	struct hisi_sas_itct *itct = &hisi_hba->itct[device_id];
	struct domain_device *parent_dev = device->parent;
	struct asd_sas_port *sas_port = device->port;
	struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
	u64 sas_addr;

	memset(itct, 0, sizeof(*itct));

	/* qw0 */
	qw0 = 0;
	switch (sas_dev->dev_type) {
	case SAS_END_DEVICE:
	case SAS_EDGE_EXPANDER_DEVICE:
	case SAS_FANOUT_EXPANDER_DEVICE:
		qw0 = HISI_SAS_DEV_TYPE_SSP << ITCT_HDR_DEV_TYPE_OFF;
		break;
	case SAS_SATA_DEV:
	case SAS_SATA_PENDING:
		if (parent_dev && dev_is_expander(parent_dev->dev_type))
			qw0 = HISI_SAS_DEV_TYPE_STP << ITCT_HDR_DEV_TYPE_OFF;
		else
			qw0 = HISI_SAS_DEV_TYPE_SATA << ITCT_HDR_DEV_TYPE_OFF;
		break;
	default:
		dev_warn(dev, "setup itct: unsupported dev type (%d)\n",
			 sas_dev->dev_type);
	}

	qw0 |= ((1 << ITCT_HDR_VALID_OFF) |
		(device->linkrate << ITCT_HDR_MCR_OFF) |
		(1 << ITCT_HDR_VLN_OFF) |
		(0xfa << ITCT_HDR_SMP_TIMEOUT_OFF) |
		(1 << ITCT_HDR_AWT_CONTINUE_OFF) |
		(port->id << ITCT_HDR_PORT_ID_OFF));
	itct->qw0 = cpu_to_le64(qw0);

	/* qw1 */
	memcpy(&sas_addr, device->sas_addr, SAS_ADDR_SIZE);
	itct->sas_addr = cpu_to_le64(__swab64(sas_addr));

	/* qw2 */
	if (!dev_is_sata(device))
		itct->qw2 = cpu_to_le64((5000ULL << ITCT_HDR_INLT_OFF) |
					(0x1ULL << ITCT_HDR_RTOLT_OFF));
}

static int clear_itct_v3_hw(struct hisi_hba *hisi_hba,
			    struct hisi_sas_device *sas_dev)
{
	DECLARE_COMPLETION_ONSTACK(completion);
	u64 dev_id = sas_dev->device_id;
	struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id];
	u32 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
	struct device *dev = hisi_hba->dev;

	sas_dev->completion = &completion;

	/* clear the itct interrupt state */
	if (ENT_INT_SRC3_ITC_INT_MSK & reg_val)
		hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
				 ENT_INT_SRC3_ITC_INT_MSK);

	/* clear the itct table */
	reg_val = ITCT_CLR_EN_MSK | (dev_id & ITCT_DEV_MSK);
	hisi_sas_write32(hisi_hba, ITCT_CLR, reg_val);

	if (!wait_for_completion_timeout(sas_dev->completion,
					 HISI_SAS_CLEAR_ITCT_TIMEOUT)) {
		dev_warn(dev, "failed to clear ITCT\n");
		return -ETIMEDOUT;
	}

	memset(itct, 0, sizeof(struct hisi_sas_itct));
	return 0;
}

static void dereg_device_v3_hw(struct hisi_hba *hisi_hba,
				struct domain_device *device)
{
	struct hisi_sas_slot *slot, *slot2;
	struct hisi_sas_device *sas_dev = device->lldd_dev;
	u32 cfg_abt_set_query_iptt;

	cfg_abt_set_query_iptt = hisi_sas_read32(hisi_hba,
		CFG_ABT_SET_QUERY_IPTT);
	spin_lock(&sas_dev->lock);
	list_for_each_entry_safe(slot, slot2, &sas_dev->list, entry) {
		cfg_abt_set_query_iptt &= ~CFG_SET_ABORTED_IPTT_MSK;
		cfg_abt_set_query_iptt |= (1 << CFG_SET_ABORTED_EN_OFF) |
			(slot->idx << CFG_SET_ABORTED_IPTT_OFF);
		hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT,
			cfg_abt_set_query_iptt);
	}
	spin_unlock(&sas_dev->lock);
	cfg_abt_set_query_iptt &= ~(1 << CFG_SET_ABORTED_EN_OFF);
	hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT,
		cfg_abt_set_query_iptt);
	hisi_sas_write32(hisi_hba, CFG_ABT_SET_IPTT_DONE,
					1 << CFG_ABT_SET_IPTT_DONE_OFF);
}

static int reset_hw_v3_hw(struct hisi_hba *hisi_hba)
{
	struct device *dev = hisi_hba->dev;
	int ret;
	u32 val;

	hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0);

	/* Disable all of the PHYs */
	hisi_sas_stop_phys(hisi_hba);
	udelay(50);

	/* Ensure axi bus idle */
	ret = hisi_sas_read32_poll_timeout(AXI_CFG, val, !val,
					   20000, 1000000);
	if (ret) {
		dev_err(dev, "axi bus is not idle, ret = %d!\n", ret);
		return -EIO;
	}

	if (ACPI_HANDLE(dev)) {
		acpi_status s;

		s = acpi_evaluate_object(ACPI_HANDLE(dev), "_RST", NULL, NULL);
		if (ACPI_FAILURE(s)) {
			dev_err(dev, "Reset failed\n");
			return -EIO;
		}
	} else {
		dev_err(dev, "no reset method!\n");
		return -EINVAL;
	}

	return 0;
}

static int hw_init_v3_hw(struct hisi_hba *hisi_hba)
{
	struct device *dev = hisi_hba->dev;
	struct acpi_device *acpi_dev;
	union acpi_object *obj;
	guid_t guid;
	int rc;

	rc = reset_hw_v3_hw(hisi_hba);
	if (rc) {
		dev_err(dev, "hisi_sas_reset_hw failed, rc=%d\n", rc);
		return rc;
	}

	msleep(100);
	init_reg_v3_hw(hisi_hba);

	if (guid_parse("D5918B4B-37AE-4E10-A99F-E5E8A6EF4C1F", &guid)) {
		dev_err(dev, "Parse GUID failed\n");
		return -EINVAL;
	}

	/*
	 * This DSM handles some hardware-related configurations:
	 * 1. Switch over to MSI error handling in kernel
	 * 2. BIOS *may* reset some register values through this method
	 */
	obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &guid, 0,
				DSM_FUNC_ERR_HANDLE_MSI, NULL);
	if (!obj)
		dev_warn(dev, "can not find DSM method, ignore\n");
	else
		ACPI_FREE(obj);

	acpi_dev = ACPI_COMPANION(dev);
	if (!acpi_device_power_manageable(acpi_dev))
		dev_notice(dev, "neither _PS0 nor _PR0 is defined\n");
	return 0;
}

static void enable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
{
	u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);

	cfg |= PHY_CFG_ENA_MSK;
	cfg &= ~PHY_CFG_PHY_RST_MSK;
	hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
}

static void disable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
{
	u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
	u32 irq_msk = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2_MSK);
	static const u32 msk = BIT(CHL_INT2_RX_DISP_ERR_OFF) |
			       BIT(CHL_INT2_RX_CODE_ERR_OFF) |
			       BIT(CHL_INT2_RX_INVLD_DW_OFF);
	u32 state;

	hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2_MSK, msk | irq_msk);

	cfg &= ~PHY_CFG_ENA_MSK;
	hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);

	mdelay(50);

	state = hisi_sas_read32(hisi_hba, PHY_STATE);
	if (state & BIT(phy_no)) {
		cfg |= PHY_CFG_PHY_RST_MSK;
		hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
	}

	udelay(1);

	hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_INVLD_DW);
	hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DISP_ERR);
	hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_CODE_ERR);

	hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2, msk);
	hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2_MSK, irq_msk);
}

static void start_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
{
	config_id_frame_v3_hw(hisi_hba, phy_no);
	config_phy_opt_mode_v3_hw(hisi_hba, phy_no);
	enable_phy_v3_hw(hisi_hba, phy_no);
}

static void phy_hard_reset_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
{
	struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
	u32 txid_auto;

	hisi_sas_phy_enable(hisi_hba, phy_no, 0);
	if (phy->identify.device_type == SAS_END_DEVICE) {
		txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
		hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
					txid_auto | TX_HARDRST_MSK);
	}
	msleep(100);
	hisi_sas_phy_enable(hisi_hba, phy_no, 1);
}

static enum sas_linkrate phy_get_max_linkrate_v3_hw(void)
{
	return SAS_LINK_RATE_12_0_GBPS;
}

static void phys_init_v3_hw(struct hisi_hba *hisi_hba)
{
	int i;

	for (i = 0; i < hisi_hba->n_phy; i++) {
		struct hisi_sas_phy *phy = &hisi_hba->phy[i];
		struct asd_sas_phy *sas_phy = &phy->sas_phy;

		if (!sas_phy->phy->enabled)
			continue;

		hisi_sas_phy_enable(hisi_hba, i, 1);
	}
}

static void sl_notify_ssp_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
{
	u32 sl_control;

	sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
	sl_control |= SL_CONTROL_NOTIFY_EN_MSK;
	hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
	msleep(1);
	sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
	sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK;
	hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
}

static int get_wideport_bitmap_v3_hw(struct hisi_hba *hisi_hba, int port_id)
{
	int i, bitmap = 0;
	u32 phy_port_num_ma = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
	u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);

	for (i = 0; i < hisi_hba->n_phy; i++)
		if (phy_state & BIT(i))
			if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id)
				bitmap |= BIT(i);

	return bitmap;
}

static void start_delivery_v3_hw(struct hisi_sas_dq *dq)
{
	struct hisi_hba *hisi_hba = dq->hisi_hba;
	struct hisi_sas_slot *s, *s1, *s2 = NULL;
	int dlvry_queue = dq->id;
	int wp;

	list_for_each_entry_safe(s, s1, &dq->list, delivery) {
		if (!s->ready)
			break;
		s2 = s;
		list_del(&s->delivery);
	}

	if (!s2)
		return;

	/*
	 * Ensure that memories for slots built on other CPUs is observed.
	 */
	smp_rmb();
	wp = (s2->dlvry_queue_slot + 1) % HISI_SAS_QUEUE_SLOTS;

	hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14), wp);
}

static void prep_prd_sge_v3_hw(struct hisi_hba *hisi_hba,
			      struct hisi_sas_slot *slot,
			      struct hisi_sas_cmd_hdr *hdr,
			      struct scatterlist *scatter,
			      int n_elem)
{
	struct hisi_sas_sge_page *sge_page = hisi_sas_sge_addr_mem(slot);
	struct scatterlist *sg;
	int i;

	for_each_sg(scatter, sg, n_elem, i) {
		struct hisi_sas_sge *entry = &sge_page->sge[i];

		entry->addr = cpu_to_le64(sg_dma_address(sg));
		entry->page_ctrl_0 = entry->page_ctrl_1 = 0;
		entry->data_len = cpu_to_le32(sg_dma_len(sg));
		entry->data_off = 0;
	}

	hdr->prd_table_addr = cpu_to_le64(hisi_sas_sge_addr_dma(slot));

	hdr->sg_len |= cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF);
}

static void prep_prd_sge_dif_v3_hw(struct hisi_hba *hisi_hba,
				   struct hisi_sas_slot *slot,
				   struct hisi_sas_cmd_hdr *hdr,
				   struct scatterlist *scatter,
				   int n_elem)
{
	struct hisi_sas_sge_dif_page *sge_dif_page;
	struct scatterlist *sg;
	int i;

	sge_dif_page = hisi_sas_sge_dif_addr_mem(slot);

	for_each_sg(scatter, sg, n_elem, i) {
		struct hisi_sas_sge *entry = &sge_dif_page->sge[i];

		entry->addr = cpu_to_le64(sg_dma_address(sg));
		entry->page_ctrl_0 = 0;
		entry->page_ctrl_1 = 0;
		entry->data_len = cpu_to_le32(sg_dma_len(sg));
		entry->data_off = 0;
	}

	hdr->dif_prd_table_addr =
		cpu_to_le64(hisi_sas_sge_dif_addr_dma(slot));

	hdr->sg_len |= cpu_to_le32(n_elem << CMD_HDR_DIF_SGL_LEN_OFF);
}

static u32 get_prot_chk_msk_v3_hw(struct scsi_cmnd *scsi_cmnd)
{
	unsigned char prot_flags = scsi_cmnd->prot_flags;

	if (prot_flags & SCSI_PROT_REF_CHECK)
		return T10_CHK_APP_TAG_MSK;
	return T10_CHK_REF_TAG_MSK | T10_CHK_APP_TAG_MSK;
}

static void fill_prot_v3_hw(struct scsi_cmnd *scsi_cmnd,
			    struct hisi_sas_protect_iu_v3_hw *prot)
{
	unsigned char prot_op = scsi_get_prot_op(scsi_cmnd);
	unsigned int interval = scsi_prot_interval(scsi_cmnd);
	u32 lbrt_chk_val = t10_pi_ref_tag(scsi_cmd_to_rq(scsi_cmnd));

	switch (prot_op) {
	case SCSI_PROT_READ_INSERT:
		prot->dw0 |= T10_INSRT_EN_MSK;
		prot->lbrtgv = lbrt_chk_val;
		break;
	case SCSI_PROT_READ_STRIP:
		prot->dw0 |= (T10_RMV_EN_MSK | T10_CHK_EN_MSK);
		prot->lbrtcv = lbrt_chk_val;
		prot->dw4 |= get_prot_chk_msk_v3_hw(scsi_cmnd);
		break;
	case SCSI_PROT_READ_PASS:
		prot->dw0 |= T10_CHK_EN_MSK;
		prot->lbrtcv = lbrt_chk_val;
		prot->dw4 |= get_prot_chk_msk_v3_hw(scsi_cmnd);
		break;
	case SCSI_PROT_WRITE_INSERT:
		prot->dw0 |= T10_INSRT_EN_MSK;
		prot->lbrtgv = lbrt_chk_val;
		break;
	case SCSI_PROT_WRITE_STRIP:
		prot->dw0 |= (T10_RMV_EN_MSK | T10_CHK_EN_MSK);
		prot->lbrtcv = lbrt_chk_val;
		break;
	case SCSI_PROT_WRITE_PASS:
		prot->dw0 |= T10_CHK_EN_MSK;
		prot->lbrtcv = lbrt_chk_val;
		prot->dw4 |= get_prot_chk_msk_v3_hw(scsi_cmnd);
		break;
	default:
		WARN(1, "prot_op(0x%x) is not valid\n", prot_op);
		break;
	}

	switch (interval) {
	case 512:
		break;
	case 4096:
		prot->dw0 |= (0x1 << USR_DATA_BLOCK_SZ_OFF);
		break;
	case 520:
		prot->dw0 |= (0x2 << USR_DATA_BLOCK_SZ_OFF);
		break;
	default:
		WARN(1, "protection interval (0x%x) invalid\n",
		     interval);
		break;
	}

	prot->dw0 |= INCR_LBRT_MSK;
}

static void prep_ssp_v3_hw(struct hisi_hba *hisi_hba,
			  struct hisi_sas_slot *slot)
{
	struct sas_task *task = slot->task;
	struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
	struct domain_device *device = task->dev;
	struct hisi_sas_device *sas_dev = device->lldd_dev;
	struct hisi_sas_port *port = slot->port;
	struct sas_ssp_task *ssp_task = &task->ssp_task;
	struct scsi_cmnd *scsi_cmnd = ssp_task->cmd;
	struct sas_tmf_task *tmf = slot->tmf;
	int has_data = 0, priority = !!tmf;
	unsigned char prot_op;
	u8 *buf_cmd;
	u32 dw1 = 0, dw2 = 0, len = 0;

	hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) |
			       (2 << CMD_HDR_TLR_CTRL_OFF) |
			       (port->id << CMD_HDR_PORT_OFF) |
			       (priority << CMD_HDR_PRIORITY_OFF) |
			       (1 << CMD_HDR_CMD_OFF)); /* ssp */

	dw1 = 1 << CMD_HDR_VDTL_OFF;
	if (tmf) {
		dw1 |= 2 << CMD_HDR_FRAME_TYPE_OFF;
		dw1 |= DIR_NO_DATA << CMD_HDR_DIR_OFF;
	} else {
		prot_op = scsi_get_prot_op(scsi_cmnd);
		dw1 |= 1 << CMD_HDR_FRAME_TYPE_OFF;
		switch (scsi_cmnd->sc_data_direction) {
		case DMA_TO_DEVICE:
			has_data = 1;
			dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
			break;
		case DMA_FROM_DEVICE:
			has_data = 1;
			dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
			break;
		default:
			dw1 &= ~CMD_HDR_DIR_MSK;
		}
	}

	/* map itct entry */
	dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;

	dw2 = (((sizeof(struct ssp_command_iu) + sizeof(struct ssp_frame_hdr)
	      + 3) / 4) << CMD_HDR_CFL_OFF) |
	      ((HISI_SAS_MAX_SSP_RESP_SZ / 4) << CMD_HDR_MRFL_OFF) |
	      (2 << CMD_HDR_SG_MOD_OFF);
	hdr->dw2 = cpu_to_le32(dw2);
	hdr->transfer_tags = cpu_to_le32(slot->idx);

	if (has_data) {
		prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter,
				   slot->n_elem);

		if (scsi_prot_sg_count(scsi_cmnd))
			prep_prd_sge_dif_v3_hw(hisi_hba, slot, hdr,
					       scsi_prot_sglist(scsi_cmnd),
					       slot->n_elem_dif);
	}

	hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
	hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));

	buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot) +
		sizeof(struct ssp_frame_hdr);

	memcpy(buf_cmd, &task->ssp_task.LUN, 8);
	if (!tmf) {
		buf_cmd[9] = ssp_task->task_attr;
		memcpy(buf_cmd + 12, scsi_cmnd->cmnd, scsi_cmnd->cmd_len);
	} else {
		buf_cmd[10] = tmf->tmf;
		switch (tmf->tmf) {
		case TMF_ABORT_TASK:
		case TMF_QUERY_TASK:
			buf_cmd[12] =
				(tmf->tag_of_task_to_be_managed >> 8) & 0xff;
			buf_cmd[13] =
				tmf->tag_of_task_to_be_managed & 0xff;
			break;
		default:
			break;
		}
	}

	if (has_data && (prot_op != SCSI_PROT_NORMAL)) {
		struct hisi_sas_protect_iu_v3_hw prot;
		u8 *buf_cmd_prot;

		hdr->dw7 |= cpu_to_le32(1 << CMD_HDR_ADDR_MODE_SEL_OFF);
		dw1 |= CMD_HDR_PIR_MSK;
		buf_cmd_prot = hisi_sas_cmd_hdr_addr_mem(slot) +
			       sizeof(struct ssp_frame_hdr) +
			       sizeof(struct ssp_command_iu);

		memset(&prot, 0, sizeof(struct hisi_sas_protect_iu_v3_hw));
		fill_prot_v3_hw(scsi_cmnd, &prot);
		memcpy(buf_cmd_prot, &prot,
		       sizeof(struct hisi_sas_protect_iu_v3_hw));
		/*
		 * For READ, we need length of info read to memory, while for
		 * WRITE we need length of data written to the disk.
		 */
		if (prot_op == SCSI_PROT_WRITE_INSERT ||
		    prot_op == SCSI_PROT_READ_INSERT ||
		    prot_op == SCSI_PROT_WRITE_PASS ||
		    prot_op == SCSI_PROT_READ_PASS) {
			unsigned int interval = scsi_prot_interval(scsi_cmnd);
			unsigned int ilog2_interval = ilog2(interval);

			len = (task->total_xfer_len >> ilog2_interval) * 8;
		}
	}

	hdr->dw1 = cpu_to_le32(dw1);

	hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len + len);
}

static void prep_smp_v3_hw(struct hisi_hba *hisi_hba,
			  struct hisi_sas_slot *slot)
{
	struct sas_task *task = slot->task;
	struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
	struct domain_device *device = task->dev;
	struct hisi_sas_port *port = slot->port;
	struct scatterlist *sg_req;
	struct hisi_sas_device *sas_dev = device->lldd_dev;
	dma_addr_t req_dma_addr;
	unsigned int req_len;

	/* req */
	sg_req = &task->smp_task.smp_req;
	req_len = sg_dma_len(sg_req);
	req_dma_addr = sg_dma_address(sg_req);

	/* create header */
	/* dw0 */
	hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) |
			       (1 << CMD_HDR_PRIORITY_OFF) | /* high pri */
			       (2 << CMD_HDR_CMD_OFF)); /* smp */

	/* map itct entry */
	hdr->dw1 = cpu_to_le32((sas_dev->device_id << CMD_HDR_DEV_ID_OFF) |
			       (1 << CMD_HDR_FRAME_TYPE_OFF) |
			       (DIR_NO_DATA << CMD_HDR_DIR_OFF));

	/* dw2 */
	hdr->dw2 = cpu_to_le32((((req_len - 4) / 4) << CMD_HDR_CFL_OFF) |
			       (HISI_SAS_MAX_SMP_RESP_SZ / 4 <<
			       CMD_HDR_MRFL_OFF));

	hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF);

	hdr->cmd_table_addr = cpu_to_le64(req_dma_addr);
	hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
}

static void prep_ata_v3_hw(struct hisi_hba *hisi_hba,
			  struct hisi_sas_slot *slot)
{
	struct sas_task *task = slot->task;
	struct domain_device *device = task->dev;
	struct domain_device *parent_dev = device->parent;
	struct hisi_sas_device *sas_dev = device->lldd_dev;
	struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
	struct asd_sas_port *sas_port = device->port;
	struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
	u8 *buf_cmd;
	int has_data = 0, hdr_tag = 0;
	u32 dw1 = 0, dw2 = 0;

	hdr->dw0 = cpu_to_le32(port->id << CMD_HDR_PORT_OFF);
	if (parent_dev && dev_is_expander(parent_dev->dev_type))
		hdr->dw0 |= cpu_to_le32(3 << CMD_HDR_CMD_OFF);
	else
		hdr->dw0 |= cpu_to_le32(4U << CMD_HDR_CMD_OFF);

	switch (task->data_dir) {
	case DMA_TO_DEVICE:
		has_data = 1;
		dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
		break;
	case DMA_FROM_DEVICE:
		has_data = 1;
		dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
		break;
	default:
		dw1 &= ~CMD_HDR_DIR_MSK;
	}

	if ((task->ata_task.fis.command == ATA_CMD_DEV_RESET) &&
			(task->ata_task.fis.control & ATA_SRST))
		dw1 |= 1 << CMD_HDR_RESET_OFF;

	dw1 |= (hisi_sas_get_ata_protocol(
		&task->ata_task.fis, task->data_dir))
		<< CMD_HDR_FRAME_TYPE_OFF;
	dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;

	if (FIS_CMD_IS_UNCONSTRAINED(task->ata_task.fis))
		dw1 |= 1 << CMD_HDR_UNCON_CMD_OFF;

	hdr->dw1 = cpu_to_le32(dw1);

	/* dw2 */
	if (task->ata_task.use_ncq) {
		struct ata_queued_cmd *qc = task->uldd_task;

		hdr_tag = qc->tag;
		task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
		dw2 |= hdr_tag << CMD_HDR_NCQ_TAG_OFF;
	}

	dw2 |= (HISI_SAS_MAX_STP_RESP_SZ / 4) << CMD_HDR_CFL_OFF |
			2 << CMD_HDR_SG_MOD_OFF;
	hdr->dw2 = cpu_to_le32(dw2);

	/* dw3 */
	hdr->transfer_tags = cpu_to_le32(slot->idx);

	if (has_data)
		prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter,
					slot->n_elem);

	hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
	hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
	hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));

	buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot);

	if (likely(!task->ata_task.device_control_reg_update))
		task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */
	/* fill in command FIS */
	memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis));
}

static void prep_abort_v3_hw(struct hisi_hba *hisi_hba,
			     struct hisi_sas_slot *slot)
{
	struct sas_task *task = slot->task;
	struct sas_internal_abort_task *abort = &task->abort_task;
	struct domain_device *dev = task->dev;
	struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
	struct hisi_sas_port *port = slot->port;
	struct hisi_sas_device *sas_dev = dev->lldd_dev;
	bool sata = dev_is_sata(dev);

	/* dw0 */
	hdr->dw0 = cpu_to_le32((5U << CMD_HDR_CMD_OFF) | /* abort */
			       (port->id << CMD_HDR_PORT_OFF) |
				(sata << CMD_HDR_ABORT_DEVICE_TYPE_OFF) |
				(abort->type << CMD_HDR_ABORT_FLAG_OFF));

	/* dw1 */
	hdr->dw1 = cpu_to_le32(sas_dev->device_id
			<< CMD_HDR_DEV_ID_OFF);

	/* dw7 */
	hdr->dw7 = cpu_to_le32(abort->tag << CMD_HDR_ABORT_IPTT_OFF);
	hdr->transfer_tags = cpu_to_le32(slot->idx);
}

static irqreturn_t phy_up_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
{
	int i;
	irqreturn_t res;
	u32 context, port_id, link_rate;
	struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
	struct asd_sas_phy *sas_phy = &phy->sas_phy;
	struct device *dev = hisi_hba->dev;

	hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 1);

	port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
	port_id = (port_id >> (4 * phy_no)) & 0xf;
	link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
	link_rate = (link_rate >> (phy_no * 4)) & 0xf;

	if (port_id == 0xf) {
		dev_err(dev, "phyup: phy%d invalid portid\n", phy_no);
		res = IRQ_NONE;
		goto end;
	}
	sas_phy->linkrate = link_rate;
	phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);

	/* Check for SATA dev */
	context = hisi_sas_read32(hisi_hba, PHY_CONTEXT);
	if (context & (1 << phy_no)) {
		struct hisi_sas_initial_fis *initial_fis;
		struct dev_to_host_fis *fis;
		u8 attached_sas_addr[SAS_ADDR_SIZE] = {0};
		struct Scsi_Host *shost = hisi_hba->shost;

		dev_info(dev, "phyup: phy%d link_rate=%d(sata)\n", phy_no, link_rate);
		initial_fis = &hisi_hba->initial_fis[phy_no];
		fis = &initial_fis->fis;

		/* check ERR bit of Status Register */
		if (fis->status & ATA_ERR) {
			dev_warn(dev, "sata int: phy%d FIS status: 0x%x\n",
				 phy_no, fis->status);
			hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET);
			res = IRQ_NONE;
			goto end;
		}

		sas_phy->oob_mode = SATA_OOB_MODE;
		attached_sas_addr[0] = 0x50;
		attached_sas_addr[6] = shost->host_no;
		attached_sas_addr[7] = phy_no;
		memcpy(sas_phy->attached_sas_addr,
		       attached_sas_addr,
		       SAS_ADDR_SIZE);
		memcpy(sas_phy->frame_rcvd, fis,
		       sizeof(struct dev_to_host_fis));
		phy->phy_type |= PORT_TYPE_SATA;
		phy->identify.device_type = SAS_SATA_DEV;
		phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
		phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
	} else {
		u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd;
		struct sas_identify_frame *id =
			(struct sas_identify_frame *)frame_rcvd;

		dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate);
		for (i = 0; i < 6; i++) {
			u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no,
					       RX_IDAF_DWORD0 + (i * 4));
			frame_rcvd[i] = __swab32(idaf);
		}
		sas_phy->oob_mode = SAS_OOB_MODE;
		memcpy(sas_phy->attached_sas_addr,
		       &id->sas_addr,
		       SAS_ADDR_SIZE);
		phy->phy_type |= PORT_TYPE_SAS;
		phy->identify.device_type = id->dev_type;
		phy->frame_rcvd_size = sizeof(struct sas_identify_frame);
		if (phy->identify.device_type == SAS_END_DEVICE)
			phy->identify.target_port_protocols =
				SAS_PROTOCOL_SSP;
		else if (phy->identify.device_type != SAS_PHY_UNUSED)
			phy->identify.target_port_protocols =
				SAS_PROTOCOL_SMP;
	}

	phy->port_id = port_id;
	spin_lock(&phy->lock);
	/* Delete timer and set phy_attached atomically */
	del_timer(&phy->timer);
	phy->phy_attached = 1;
	spin_unlock(&phy->lock);

	/*
	 * Call pm_runtime_get_noresume() which pairs with
	 * hisi_sas_phyup_pm_work() -> pm_runtime_put_sync().
	 * For failure call pm_runtime_put() as we are in a hardirq context.
	 */
	pm_runtime_get_noresume(dev);
	res = hisi_sas_notify_phy_event(phy, HISI_PHYE_PHY_UP_PM);
	if (!res)
		pm_runtime_put(dev);

	res = IRQ_HANDLED;

end:
	if (phy->reset_completion)
		complete(phy->reset_completion);
	hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
			     CHL_INT0_SL_PHY_ENABLE_MSK);
	hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 0);

	return res;
}

static irqreturn_t phy_down_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
{
	struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
	u32 phy_state, sl_ctrl, txid_auto;
	struct device *dev = hisi_hba->dev;

	atomic_inc(&phy->down_cnt);

	del_timer(&phy->timer);
	hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 1);

	phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
	dev_info(dev, "phydown: phy%d phy_state=0x%x\n", phy_no, phy_state);
	hisi_sas_phy_down(hisi_hba, phy_no, (phy_state & 1 << phy_no) ? 1 : 0,
			  GFP_ATOMIC);

	sl_ctrl = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
	hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL,
						sl_ctrl&(~SL_CTA_MSK));

	txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
	hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
						txid_auto | CT3_MSK);

	hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, CHL_INT0_NOT_RDY_MSK);
	hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 0);

	return IRQ_HANDLED;
}

static irqreturn_t phy_bcast_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
{
	struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
	u32 bcast_status;

	hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 1);
	bcast_status = hisi_sas_phy_read32(hisi_hba, phy_no, RX_PRIMS_STATUS);
	if (bcast_status & RX_BCAST_CHG_MSK)
		hisi_sas_phy_bcast(phy);
	hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
			     CHL_INT0_SL_RX_BCST_ACK_MSK);
	hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 0);

	return IRQ_HANDLED;
}

static irqreturn_t int_phy_up_down_bcast_v3_hw(int irq_no, void *p)
{
	struct hisi_hba *hisi_hba = p;
	u32 irq_msk;
	int phy_no = 0;
	irqreturn_t res = IRQ_NONE;

	irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS)
				& 0x11111111;
	while (irq_msk) {
		if (irq_msk  & 1) {
			u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no,
							    CHL_INT0);
			u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
			int rdy = phy_state & (1 << phy_no);

			if (rdy) {
				if (irq_value & CHL_INT0_SL_PHY_ENABLE_MSK)
					/* phy up */
					if (phy_up_v3_hw(phy_no, hisi_hba)
							== IRQ_HANDLED)
						res = IRQ_HANDLED;
				if (irq_value & CHL_INT0_SL_RX_BCST_ACK_MSK)
					/* phy bcast */
					if (phy_bcast_v3_hw(phy_no, hisi_hba)
							== IRQ_HANDLED)
						res = IRQ_HANDLED;
			} else {
				if (irq_value & CHL_INT0_NOT_RDY_MSK)
					/* phy down */
					if (phy_down_v3_hw(phy_no, hisi_hba)
							== IRQ_HANDLED)
						res = IRQ_HANDLED;
			}
		}
		irq_msk >>= 4;
		phy_no++;
	}

	return res;
}

static const struct hisi_sas_hw_error port_axi_error[] = {
	{
		.irq_msk = BIT(CHL_INT1_DMAC_TX_ECC_MB_ERR_OFF),
		.msg = "dmac_tx_ecc_bad_err",
	},
	{
		.irq_msk = BIT(CHL_INT1_DMAC_RX_ECC_MB_ERR_OFF),
		.msg = "dmac_rx_ecc_bad_err",
	},
	{
		.irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF),
		.msg = "dma_tx_axi_wr_err",
	},
	{
		.irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF),
		.msg = "dma_tx_axi_rd_err",
	},
	{
		.irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF),
		.msg = "dma_rx_axi_wr_err",
	},
	{
		.irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF),
		.msg = "dma_rx_axi_rd_err",
	},
	{
		.irq_msk = BIT(CHL_INT1_DMAC_TX_FIFO_ERR_OFF),
		.msg = "dma_tx_fifo_err",
	},
	{
		.irq_msk = BIT(CHL_INT1_DMAC_RX_FIFO_ERR_OFF),
		.msg = "dma_rx_fifo_err",
	},
	{
		.irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_RUSER_ERR_OFF),
		.msg = "dma_tx_axi_ruser_err",
	},
	{
		.irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_RUSER_ERR_OFF),
		.msg = "dma_rx_axi_ruser_err",
	},
};

static void handle_chl_int1_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
{
	u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT1);
	u32 irq_msk = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT1_MSK);
	struct device *dev = hisi_hba->dev;
	int i;

	irq_value &= ~irq_msk;
	if (!irq_value) {
		dev_warn(dev, "phy%d channel int 1 received with status bits cleared\n",
			 phy_no);
		return;
	}

	for (i = 0; i < ARRAY_SIZE(port_axi_error); i++) {
		const struct hisi_sas_hw_error *error = &port_axi_error[i];

		if (!(irq_value & error->irq_msk))
			continue;

		dev_err(dev, "%s error (phy%d 0x%x) found!\n",
			error->msg, phy_no, irq_value);
		queue_work(hisi_hba->wq, &hisi_hba->rst_work);
	}

	hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT1, irq_value);
}

static void phy_get_events_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
{
	struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
	struct asd_sas_phy *sas_phy = &phy->sas_phy;
	struct sas_phy *sphy = sas_phy->phy;
	unsigned long flags;
	u32 reg_value;

	spin_lock_irqsave(&phy->lock, flags);

	/* loss dword sync */
	reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DWS_LOST);
	sphy->loss_of_dword_sync_count += reg_value;

	/* phy reset problem */
	reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_RESET_PROB);
	sphy->phy_reset_problem_count += reg_value;

	/* invalid dword */
	reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_INVLD_DW);
	sphy->invalid_dword_count += reg_value;

	/* disparity err */
	reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DISP_ERR);
	sphy->running_disparity_error_count += reg_value;

	/* code violation error */
	reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_CODE_ERR);
	phy->code_violation_err_count += reg_value;

	spin_unlock_irqrestore(&phy->lock, flags);
}

static void handle_chl_int2_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
{
	u32 irq_msk = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2_MSK);
	u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2);
	struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
	struct pci_dev *pci_dev = hisi_hba->pci_dev;
	struct device *dev = hisi_hba->dev;
	static const u32 msk = BIT(CHL_INT2_RX_DISP_ERR_OFF) |
			BIT(CHL_INT2_RX_CODE_ERR_OFF) |
			BIT(CHL_INT2_RX_INVLD_DW_OFF);

	irq_value &= ~irq_msk;
	if (!irq_value) {
		dev_warn(dev, "phy%d channel int 2 received with status bits cleared\n",
			 phy_no);
		return;
	}

	if (irq_value & BIT(CHL_INT2_SL_IDAF_TOUT_CONF_OFF)) {
		dev_warn(dev, "phy%d identify timeout\n", phy_no);
		hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET);
	}

	if (irq_value & BIT(CHL_INT2_STP_LINK_TIMEOUT_OFF)) {
		u32 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no,
				STP_LINK_TIMEOUT_STATE);

		dev_warn(dev, "phy%d stp link timeout (0x%x)\n",
			 phy_no, reg_value);
		if (reg_value & BIT(4))
			hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET);
	}

	if (pci_dev->revision > 0x20 && (irq_value & msk)) {
		struct asd_sas_phy *sas_phy = &phy->sas_phy;
		struct sas_phy *sphy = sas_phy->phy;

		phy_get_events_v3_hw(hisi_hba, phy_no);

		if (irq_value & BIT(CHL_INT2_RX_INVLD_DW_OFF))
			dev_info(dev, "phy%d invalid dword cnt:   %u\n", phy_no,
				 sphy->invalid_dword_count);

		if (irq_value & BIT(CHL_INT2_RX_CODE_ERR_OFF))
			dev_info(dev, "phy%d code violation cnt:  %u\n", phy_no,
				 phy->code_violation_err_count);

		if (irq_value & BIT(CHL_INT2_RX_DISP_ERR_OFF))
			dev_info(dev, "phy%d disparity error cnt: %u\n", phy_no,
				 sphy->running_disparity_error_count);
	}

	if ((irq_value & BIT(CHL_INT2_RX_INVLD_DW_OFF)) &&
	    (pci_dev->revision == 0x20)) {
		u32 reg_value;
		int rc;

		rc = hisi_sas_read32_poll_timeout_atomic(
				HILINK_ERR_DFX, reg_value,
				!((reg_value >> 8) & BIT(phy_no)),
				1000, 10000);
		if (rc)
			hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET);
	}

	hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2, irq_value);
}

static void handle_chl_int0_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
{
	u32 irq_value0 = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT0);

	if (irq_value0 & CHL_INT0_PHY_RDY_MSK)
		hisi_sas_phy_oob_ready(hisi_hba, phy_no);

	hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
			     irq_value0 & (~CHL_INT0_SL_RX_BCST_ACK_MSK)
			     & (~CHL_INT0_SL_PHY_ENABLE_MSK)
			     & (~CHL_INT0_NOT_RDY_MSK));
}

static irqreturn_t int_chnl_int_v3_hw(int irq_no, void *p)
{
	struct hisi_hba *hisi_hba = p;
	u32 irq_msk;
	int phy_no = 0;

	irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS)
		  & CHNL_INT_STS_MSK;

	while (irq_msk) {
		if (irq_msk & (CHNL_INT_STS_INT0_MSK << (phy_no * CHNL_WIDTH)))
			handle_chl_int0_v3_hw(hisi_hba, phy_no);

		if (irq_msk & (CHNL_INT_STS_INT1_MSK << (phy_no * CHNL_WIDTH)))
			handle_chl_int1_v3_hw(hisi_hba, phy_no);

		if (irq_msk & (CHNL_INT_STS_INT2_MSK << (phy_no * CHNL_WIDTH)))
			handle_chl_int2_v3_hw(hisi_hba, phy_no);

		irq_msk &= ~(CHNL_INT_STS_PHY_MSK << (phy_no * CHNL_WIDTH));
		phy_no++;
	}

	return IRQ_HANDLED;
}

static const struct hisi_sas_hw_error multi_bit_ecc_errors[] = {
	{
		.irq_msk = BIT(SAS_ECC_INTR_DQE_ECC_MB_OFF),
		.msk = HGC_DQE_ECC_MB_ADDR_MSK,
		.shift = HGC_DQE_ECC_MB_ADDR_OFF,
		.msg = "hgc_dqe_eccbad_intr",
		.reg = HGC_DQE_ECC_ADDR,
	},
	{
		.irq_msk = BIT(SAS_ECC_INTR_IOST_ECC_MB_OFF),
		.msk = HGC_IOST_ECC_MB_ADDR_MSK,
		.shift = HGC_IOST_ECC_MB_ADDR_OFF,
		.msg = "hgc_iost_eccbad_intr",
		.reg = HGC_IOST_ECC_ADDR,
	},
	{
		.irq_msk = BIT(SAS_ECC_INTR_ITCT_ECC_MB_OFF),
		.msk = HGC_ITCT_ECC_MB_ADDR_MSK,
		.shift = HGC_ITCT_ECC_MB_ADDR_OFF,
		.msg = "hgc_itct_eccbad_intr",
		.reg = HGC_ITCT_ECC_ADDR,
	},
	{
		.irq_msk = BIT(SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF),
		.msk = HGC_LM_DFX_STATUS2_IOSTLIST_MSK,
		.shift = HGC_LM_DFX_STATUS2_IOSTLIST_OFF,
		.msg = "hgc_iostl_eccbad_intr",
		.reg = HGC_LM_DFX_STATUS2,
	},
	{
		.irq_msk = BIT(SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF),
		.msk = HGC_LM_DFX_STATUS2_ITCTLIST_MSK,
		.shift = HGC_LM_DFX_STATUS2_ITCTLIST_OFF,
		.msg = "hgc_itctl_eccbad_intr",
		.reg = HGC_LM_DFX_STATUS2,
	},
	{
		.irq_msk = BIT(SAS_ECC_INTR_CQE_ECC_MB_OFF),
		.msk = HGC_CQE_ECC_MB_ADDR_MSK,
		.shift = HGC_CQE_ECC_MB_ADDR_OFF,
		.msg = "hgc_cqe_eccbad_intr",
		.reg = HGC_CQE_ECC_ADDR,
	},
	{
		.irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF),
		.msk = HGC_RXM_DFX_STATUS14_MEM0_MSK,
		.shift = HGC_RXM_DFX_STATUS14_MEM0_OFF,
		.msg = "rxm_mem0_eccbad_intr",
		.reg = HGC_RXM_DFX_STATUS14,
	},
	{
		.irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF),
		.msk = HGC_RXM_DFX_STATUS14_MEM1_MSK,
		.shift = HGC_RXM_DFX_STATUS14_MEM1_OFF,
		.msg = "rxm_mem1_eccbad_intr",
		.reg = HGC_RXM_DFX_STATUS14,
	},
	{
		.irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF),
		.msk = HGC_RXM_DFX_STATUS14_MEM2_MSK,
		.shift = HGC_RXM_DFX_STATUS14_MEM2_OFF,
		.msg = "rxm_mem2_eccbad_intr",
		.reg = HGC_RXM_DFX_STATUS14,
	},
	{
		.irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF),
		.msk = HGC_RXM_DFX_STATUS15_MEM3_MSK,
		.shift = HGC_RXM_DFX_STATUS15_MEM3_OFF,
		.msg = "rxm_mem3_eccbad_intr",
		.reg = HGC_RXM_DFX_STATUS15,
	},
	{
		.irq_msk = BIT(SAS_ECC_INTR_OOO_RAM_ECC_MB_OFF),
		.msk = AM_ROB_ECC_ERR_ADDR_MSK,
		.shift = AM_ROB_ECC_ERR_ADDR_OFF,
		.msg = "ooo_ram_eccbad_intr",
		.reg = AM_ROB_ECC_ERR_ADDR,
	},
};

static void multi_bit_ecc_error_process_v3_hw(struct hisi_hba *hisi_hba,
					      u32 irq_value)
{
	struct device *dev = hisi_hba->dev;
	const struct hisi_sas_hw_error *ecc_error;
	u32 val;
	int i;

	for (i = 0; i < ARRAY_SIZE(multi_bit_ecc_errors); i++) {
		ecc_error = &multi_bit_ecc_errors[i];
		if (irq_value & ecc_error->irq_msk) {
			val = hisi_sas_read32(hisi_hba, ecc_error->reg);
			val &= ecc_error->msk;
			val >>= ecc_error->shift;
			dev_err(dev, "%s (0x%x) found: mem addr is 0x%08X\n",
				ecc_error->msg, irq_value, val);
			queue_work(hisi_hba->wq, &hisi_hba->rst_work);
		}
	}
}

static void fatal_ecc_int_v3_hw(struct hisi_hba *hisi_hba)
{
	u32 irq_value, irq_msk;

	irq_msk = hisi_sas_read32(hisi_hba, SAS_ECC_INTR_MSK);
	hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xffffffff);

	irq_value = hisi_sas_read32(hisi_hba, SAS_ECC_INTR);
	if (irq_value)
		multi_bit_ecc_error_process_v3_hw(hisi_hba, irq_value);

	hisi_sas_write32(hisi_hba, SAS_ECC_INTR, irq_value);
	hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, irq_msk);
}

static const struct hisi_sas_hw_error axi_error[] = {
	{ .msk = BIT(0), .msg = "IOST_AXI_W_ERR" },
	{ .msk = BIT(1), .msg = "IOST_AXI_R_ERR" },
	{ .msk = BIT(2), .msg = "ITCT_AXI_W_ERR" },
	{ .msk = BIT(3), .msg = "ITCT_AXI_R_ERR" },
	{ .msk = BIT(4), .msg = "SATA_AXI_W_ERR" },
	{ .msk = BIT(5), .msg = "SATA_AXI_R_ERR" },
	{ .msk = BIT(6), .msg = "DQE_AXI_R_ERR" },
	{ .msk = BIT(7), .msg = "CQE_AXI_W_ERR" },
	{}
};

static const struct hisi_sas_hw_error fifo_error[] = {
	{ .msk = BIT(8),  .msg = "CQE_WINFO_FIFO" },
	{ .msk = BIT(9),  .msg = "CQE_MSG_FIFIO" },
	{ .msk = BIT(10), .msg = "GETDQE_FIFO" },
	{ .msk = BIT(11), .msg = "CMDP_FIFO" },
	{ .msk = BIT(12), .msg = "AWTCTRL_FIFO" },
	{}
};

static const struct hisi_sas_hw_error fatal_axi_error[] = {
	{
		.irq_msk = BIT(ENT_INT_SRC3_WP_DEPTH_OFF),
		.msg = "write pointer and depth",
	},
	{
		.irq_msk = BIT(ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF),
		.msg = "iptt no match slot",
	},
	{
		.irq_msk = BIT(ENT_INT_SRC3_RP_DEPTH_OFF),
		.msg = "read pointer and depth",
	},
	{
		.irq_msk = BIT(ENT_INT_SRC3_AXI_OFF),
		.reg = HGC_AXI_FIFO_ERR_INFO,
		.sub = axi_error,
	},
	{
		.irq_msk = BIT(ENT_INT_SRC3_FIFO_OFF),
		.reg = HGC_AXI_FIFO_ERR_INFO,
		.sub = fifo_error,
	},
	{
		.irq_msk = BIT(ENT_INT_SRC3_LM_OFF),
		.msg = "LM add/fetch list",
	},
	{
		.irq_msk = BIT(ENT_INT_SRC3_ABT_OFF),
		.msg = "SAS_HGC_ABT fetch LM list",
	},
	{
		.irq_msk = BIT(ENT_INT_SRC3_DQE_POISON_OFF),
		.msg = "read dqe poison",
	},
	{
		.irq_msk = BIT(ENT_INT_SRC3_IOST_POISON_OFF),
		.msg = "read iost poison",
	},
	{
		.irq_msk = BIT(ENT_INT_SRC3_ITCT_POISON_OFF),
		.msg = "read itct poison",
	},
	{
		.irq_msk = BIT(ENT_INT_SRC3_ITCT_NCQ_POISON_OFF),
		.msg = "read itct ncq poison",
	},

};

static irqreturn_t fatal_axi_int_v3_hw(int irq_no, void *p)
{
	u32 irq_value, irq_msk;
	struct hisi_hba *hisi_hba = p;
	struct device *dev = hisi_hba->dev;
	struct pci_dev *pdev = hisi_hba->pci_dev;
	int i;

	irq_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3);
	hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk | 0x1df00);

	irq_value = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
	irq_value &= ~irq_msk;

	for (i = 0; i < ARRAY_SIZE(fatal_axi_error); i++) {
		const struct hisi_sas_hw_error *error = &fatal_axi_error[i];

		if (!(irq_value & error->irq_msk))
			continue;

		if (error->sub) {
			const struct hisi_sas_hw_error *sub = error->sub;
			u32 err_value = hisi_sas_read32(hisi_hba, error->reg);

			for (; sub->msk || sub->msg; sub++) {
				if (!(err_value & sub->msk))
					continue;

				dev_err(dev, "%s error (0x%x) found!\n",
					sub->msg, irq_value);
				queue_work(hisi_hba->wq, &hisi_hba->rst_work);
			}
		} else {
			dev_err(dev, "%s error (0x%x) found!\n",
				error->msg, irq_value);
			queue_work(hisi_hba->wq, &hisi_hba->rst_work);
		}

		if (pdev->revision < 0x21) {
			u32 reg_val;

			reg_val = hisi_sas_read32(hisi_hba,
						  AXI_MASTER_CFG_BASE +
						  AM_CTRL_GLOBAL);
			reg_val |= AM_CTRL_SHUTDOWN_REQ_MSK;
			hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE +
					 AM_CTRL_GLOBAL, reg_val);
		}
	}

	fatal_ecc_int_v3_hw(hisi_hba);

	if (irq_value & BIT(ENT_INT_SRC3_ITC_INT_OFF)) {
		u32 reg_val = hisi_sas_read32(hisi_hba, ITCT_CLR);
		u32 dev_id = reg_val & ITCT_DEV_MSK;
		struct hisi_sas_device *sas_dev =
				&hisi_hba->devices[dev_id];

		hisi_sas_write32(hisi_hba, ITCT_CLR, 0);
		dev_dbg(dev, "clear ITCT ok\n");
		complete(sas_dev->completion);
	}

	hisi_sas_write32(hisi_hba, ENT_INT_SRC3, irq_value & 0x1df00);
	hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk);

	return IRQ_HANDLED;
}

static bool is_ncq_err_v3_hw(struct hisi_sas_complete_v3_hdr *complete_hdr)
{
	u32 dw0, dw3;

	dw0 = le32_to_cpu(complete_hdr->dw0);
	dw3 = le32_to_cpu(complete_hdr->dw3);

	return (dw0 & ERR_PHASE_RESPONSE_FRAME_REV_STAGE_MSK) &&
	       (dw3 & FIS_TYPE_SDB_MSK) &&
	       (dw3 & FIS_ATA_STATUS_ERR_MSK);
}

static bool
slot_err_v3_hw(struct hisi_hba *hisi_hba, struct sas_task *task,
	       struct hisi_sas_slot *slot)
{
	struct task_status_struct *ts = &task->task_status;
	struct hisi_sas_complete_v3_hdr *complete_queue =
			hisi_hba->complete_hdr[slot->cmplt_queue];
	struct hisi_sas_complete_v3_hdr *complete_hdr =
			&complete_queue[slot->cmplt_queue_slot];
	struct hisi_sas_err_record_v3 *record =
			hisi_sas_status_buf_addr_mem(slot);
	u32 dma_rx_err_type = le32_to_cpu(record->dma_rx_err_type);
	u32 trans_tx_fail_type = le32_to_cpu(record->trans_tx_fail_type);
	u16 sipc_rx_err_type = le16_to_cpu(record->sipc_rx_err_type);
	u32 dw3 = le32_to_cpu(complete_hdr->dw3);
	u32 dw0 = le32_to_cpu(complete_hdr->dw0);

	switch (task->task_proto) {
	case SAS_PROTOCOL_SSP:
		if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) {
			/*
			 * If returned response frame is incorrect because of data underflow,
			 * but I/O information has been written to the host memory, we examine
			 * response IU.
			 */
			if (!(dw0 & CMPLT_HDR_RSPNS_GOOD_MSK) &&
			    (dw0 & CMPLT_HDR_RSPNS_XFRD_MSK))
				return false;

			ts->residual = trans_tx_fail_type;
			ts->stat = SAS_DATA_UNDERRUN;
		} else if (dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) {
			ts->stat = SAS_QUEUE_FULL;
			slot->abort = 1;
		} else {
			ts->stat = SAS_OPEN_REJECT;
			ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
		}
		break;
	case SAS_PROTOCOL_SATA:
	case SAS_PROTOCOL_STP:
	case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
		if ((dw0 & CMPLT_HDR_RSPNS_XFRD_MSK) &&
		    (sipc_rx_err_type & RX_FIS_STATUS_ERR_MSK)) {
			if (task->ata_task.use_ncq) {
				struct domain_device *device = task->dev;
				struct hisi_sas_device *sas_dev = device->lldd_dev;

				sas_dev->dev_status = HISI_SAS_DEV_NCQ_ERR;
				slot->abort = 1;
			} else {
				ts->stat = SAS_PROTO_RESPONSE;
			}
		} else if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) {
			ts->residual = trans_tx_fail_type;
			ts->stat = SAS_DATA_UNDERRUN;
		} else if ((dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) ||
			   (dw3 & SATA_DISK_IN_ERROR_STATUS_MSK)) {
			ts->stat = SAS_PHY_DOWN;
			slot->abort = 1;
		} else {
			ts->stat = SAS_OPEN_REJECT;
			ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
		}
		if (dw0 & CMPLT_HDR_RSPNS_XFRD_MSK)
			hisi_sas_sata_done(task, slot);
		break;
	case SAS_PROTOCOL_SMP:
		ts->stat = SAS_SAM_STAT_CHECK_CONDITION;
		break;
	default:
		break;
	}
	return true;
}

static void slot_complete_v3_hw(struct hisi_hba *hisi_hba,
				struct hisi_sas_slot *slot)
{
	struct sas_task *task = slot->task;
	struct hisi_sas_device *sas_dev;
	struct device *dev = hisi_hba->dev;
	struct task_status_struct *ts;
	struct domain_device *device;
	struct sas_ha_struct *ha;
	struct hisi_sas_complete_v3_hdr *complete_queue =
			hisi_hba->complete_hdr[slot->cmplt_queue];
	struct hisi_sas_complete_v3_hdr *complete_hdr =
			&complete_queue[slot->cmplt_queue_slot];
	unsigned long flags;
	bool is_internal = slot->is_internal;
	u32 dw0, dw1, dw3;

	if (unlikely(!task || !task->lldd_task || !task->dev))
		return;

	ts = &task->task_status;
	device = task->dev;
	ha = device->port->ha;
	sas_dev = device->lldd_dev;

	spin_lock_irqsave(&task->task_state_lock, flags);
	task->task_state_flags &= ~SAS_TASK_STATE_PENDING;
	spin_unlock_irqrestore(&task->task_state_lock, flags);

	memset(ts, 0, sizeof(*ts));
	ts->resp = SAS_TASK_COMPLETE;

	if (unlikely(!sas_dev)) {
		dev_dbg(dev, "slot complete: port has not device\n");
		ts->stat = SAS_PHY_DOWN;
		goto out;
	}

	dw0 = le32_to_cpu(complete_hdr->dw0);
	dw1 = le32_to_cpu(complete_hdr->dw1);
	dw3 = le32_to_cpu(complete_hdr->dw3);

	/*
	 * Use SAS+TMF status codes
	 */
	switch ((dw0 & CMPLT_HDR_ABORT_STAT_MSK) >> CMPLT_HDR_ABORT_STAT_OFF) {
	case STAT_IO_ABORTED:
		/* this IO has been aborted by abort command */
		ts->stat = SAS_ABORTED_TASK;
		goto out;
	case STAT_IO_COMPLETE:
		/* internal abort command complete */
		ts->stat = TMF_RESP_FUNC_SUCC;
		goto out;
	case STAT_IO_NO_DEVICE:
		ts->stat = TMF_RESP_FUNC_COMPLETE;
		goto out;
	case STAT_IO_NOT_VALID:
		/*
		 * abort single IO, the controller can't find the IO
		 */
		ts->stat = TMF_RESP_FUNC_FAILED;
		goto out;
	default:
		break;
	}

	/* check for erroneous completion */
	if ((dw0 & CMPLT_HDR_CMPLT_MSK) == 0x3) {
		u32 *error_info = hisi_sas_status_buf_addr_mem(slot);

		if (slot_err_v3_hw(hisi_hba, task, slot)) {
			if (ts->stat != SAS_DATA_UNDERRUN)
				dev_info(dev, "erroneous completion iptt=%d task=%pK dev id=%d addr=%016llx CQ hdr: 0x%x 0x%x 0x%x 0x%x Error info: 0x%x 0x%x 0x%x 0x%x\n",
					slot->idx, task, sas_dev->device_id,
					SAS_ADDR(device->sas_addr),
					dw0, dw1, complete_hdr->act, dw3,
					error_info[0], error_info[1],
					error_info[2], error_info[3]);
			if (unlikely(slot->abort)) {
				if (dev_is_sata(device) && task->ata_task.use_ncq)
					sas_ata_device_link_abort(device, true);
				else
					sas_task_abort(task);

				return;
			}
			goto out;
		}
	}

	switch (task->task_proto) {
	case SAS_PROTOCOL_SSP: {
		struct ssp_response_iu *iu =
			hisi_sas_status_buf_addr_mem(slot) +
			sizeof(struct hisi_sas_err_record);

		sas_ssp_task_response(dev, task, iu);
		break;
	}
	case SAS_PROTOCOL_SMP: {
		struct scatterlist *sg_resp = &task->smp_task.smp_resp;
		void *to = page_address(sg_page(sg_resp));

		ts->stat = SAS_SAM_STAT_GOOD;

		memcpy(to + sg_resp->offset,
			hisi_sas_status_buf_addr_mem(slot) +
		       sizeof(struct hisi_sas_err_record),
		       sg_resp->length);
		break;
	}
	case SAS_PROTOCOL_SATA:
	case SAS_PROTOCOL_STP:
	case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
		ts->stat = SAS_SAM_STAT_GOOD;
		if (dw0 & CMPLT_HDR_RSPNS_XFRD_MSK)
			hisi_sas_sata_done(task, slot);
		break;
	default:
		ts->stat = SAS_SAM_STAT_CHECK_CONDITION;
		break;
	}

	if (!slot->port->port_attached) {
		dev_warn(dev, "slot complete: port %d has removed\n",
			slot->port->sas_port.id);
		ts->stat = SAS_PHY_DOWN;
	}

out:
	spin_lock_irqsave(&task->task_state_lock, flags);
	if (task->task_state_flags & SAS_TASK_STATE_ABORTED) {
		spin_unlock_irqrestore(&task->task_state_lock, flags);
		dev_info(dev, "slot complete: task(%pK) aborted\n", task);
		return;
	}
	task->task_state_flags |= SAS_TASK_STATE_DONE;
	spin_unlock_irqrestore(&task->task_state_lock, flags);
	hisi_sas_slot_task_free(hisi_hba, task, slot, true);

	if (!is_internal && (task->task_proto != SAS_PROTOCOL_SMP)) {
		spin_lock_irqsave(&device->done_lock, flags);
		if (test_bit(SAS_HA_FROZEN, &ha->state)) {
			spin_unlock_irqrestore(&device->done_lock, flags);
			dev_info(dev, "slot complete: task(%pK) ignored\n ",
				 task);
			return;
		}
		spin_unlock_irqrestore(&device->done_lock, flags);
	}

	if (task->task_done)
		task->task_done(task);
}

static int complete_v3_hw(struct hisi_sas_cq *cq)
{
	struct hisi_sas_complete_v3_hdr *complete_queue;
	struct hisi_hba *hisi_hba = cq->hisi_hba;
	u32 rd_point, wr_point;
	int queue = cq->id;
	int completed;

	rd_point = cq->rd_point;
	complete_queue = hisi_hba->complete_hdr[queue];

	wr_point = hisi_sas_read32(hisi_hba, COMPL_Q_0_WR_PTR +
				   (0x14 * queue));
	completed = (wr_point + HISI_SAS_QUEUE_SLOTS - rd_point) % HISI_SAS_QUEUE_SLOTS;

	while (rd_point != wr_point) {
		struct hisi_sas_complete_v3_hdr *complete_hdr;
		struct device *dev = hisi_hba->dev;
		struct hisi_sas_slot *slot;
		u32 dw0, dw1, dw3;
		int iptt;

		complete_hdr = &complete_queue[rd_point];
		dw0 = le32_to_cpu(complete_hdr->dw0);
		dw1 = le32_to_cpu(complete_hdr->dw1);
		dw3 = le32_to_cpu(complete_hdr->dw3);

		iptt = dw1 & CMPLT_HDR_IPTT_MSK;
		if (unlikely((dw0 & CMPLT_HDR_CMPLT_MSK) == 0x3) &&
			     (dw3 & CMPLT_HDR_SATA_DISK_ERR_MSK)) {
			int device_id = (dw1 & CMPLT_HDR_DEV_ID_MSK) >>
					CMPLT_HDR_DEV_ID_OFF;
			struct hisi_sas_itct *itct =
				&hisi_hba->itct[device_id];
			struct hisi_sas_device *sas_dev =
				&hisi_hba->devices[device_id];
			struct domain_device *device = sas_dev->sas_device;

			dev_err(dev, "erroneous completion disk err dev id=%d sas_addr=0x%llx CQ hdr: 0x%x 0x%x 0x%x 0x%x\n",
				device_id, itct->sas_addr, dw0, dw1,
				complete_hdr->act, dw3);

			if (is_ncq_err_v3_hw(complete_hdr))
				sas_dev->dev_status = HISI_SAS_DEV_NCQ_ERR;

			sas_ata_device_link_abort(device, true);
		} else if (likely(iptt < HISI_SAS_COMMAND_ENTRIES_V3_HW)) {
			slot = &hisi_hba->slot_info[iptt];
			slot->cmplt_queue_slot = rd_point;
			slot->cmplt_queue = queue;
			slot_complete_v3_hw(hisi_hba, slot);
		} else
			dev_err(dev, "IPTT %d is invalid, discard it.\n", iptt);

		if (++rd_point >= HISI_SAS_QUEUE_SLOTS)
			rd_point = 0;
	}

	/* update rd_point */
	cq->rd_point = rd_point;
	hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point);

	return completed;
}

static int queue_complete_v3_hw(struct Scsi_Host *shost, unsigned int queue)
{
	struct hisi_hba *hisi_hba = shost_priv(shost);
	struct hisi_sas_cq *cq = &hisi_hba->cq[queue];
	int completed;

	spin_lock(&cq->poll_lock);
	completed = complete_v3_hw(cq);
	spin_unlock(&cq->poll_lock);

	return completed;
}

static irqreturn_t cq_thread_v3_hw(int irq_no, void *p)
{
	struct hisi_sas_cq *cq = p;

	complete_v3_hw(cq);

	return IRQ_HANDLED;
}

static irqreturn_t cq_interrupt_v3_hw(int irq_no, void *p)
{
	struct hisi_sas_cq *cq = p;
	struct hisi_hba *hisi_hba = cq->hisi_hba;
	int queue = cq->id;

	hisi_sas_write32(hisi_hba, OQ_INT_SRC, 1 << queue);

	return IRQ_WAKE_THREAD;
}

static void hisi_sas_v3_free_vectors(void *data)
{
	struct pci_dev *pdev = data;

	pci_free_irq_vectors(pdev);
}

static int interrupt_preinit_v3_hw(struct hisi_hba *hisi_hba)
{
	/* Allocate all MSI vectors to avoid re-insertion issue */
	int max_msi = HISI_SAS_MSI_COUNT_V3_HW;
	int vectors, min_msi;
	struct Scsi_Host *shost = hisi_hba->shost;
	struct pci_dev *pdev = hisi_hba->pci_dev;
	struct irq_affinity desc = {
		.pre_vectors = BASE_VECTORS_V3_HW,
	};

	min_msi = MIN_AFFINE_VECTORS_V3_HW;
	vectors = pci_alloc_irq_vectors_affinity(pdev,
						 min_msi, max_msi,
						 PCI_IRQ_MSI |
						 PCI_IRQ_AFFINITY,
						 &desc);
	if (vectors < 0)
		return -ENOENT;


	hisi_hba->cq_nvecs = vectors - BASE_VECTORS_V3_HW - hisi_hba->iopoll_q_cnt;
	shost->nr_hw_queues = hisi_hba->cq_nvecs + hisi_hba->iopoll_q_cnt;

	return devm_add_action(&pdev->dev, hisi_sas_v3_free_vectors, pdev);
}

static int interrupt_init_v3_hw(struct hisi_hba *hisi_hba)
{
	struct device *dev = hisi_hba->dev;
	struct pci_dev *pdev = hisi_hba->pci_dev;
	int rc, i;

	rc = devm_request_irq(dev, pci_irq_vector(pdev, 1),
			      int_phy_up_down_bcast_v3_hw, 0,
			      DRV_NAME " phy", hisi_hba);
	if (rc) {
		dev_err(dev, "could not request phy interrupt, rc=%d\n", rc);
		return -ENOENT;
	}

	rc = devm_request_irq(dev, pci_irq_vector(pdev, 2),
			      int_chnl_int_v3_hw, 0,
			      DRV_NAME " channel", hisi_hba);
	if (rc) {
		dev_err(dev, "could not request chnl interrupt, rc=%d\n", rc);
		return -ENOENT;
	}

	rc = devm_request_irq(dev, pci_irq_vector(pdev, 11),
			      fatal_axi_int_v3_hw, 0,
			      DRV_NAME " fatal", hisi_hba);
	if (rc) {
		dev_err(dev, "could not request fatal interrupt, rc=%d\n", rc);
		return -ENOENT;
	}

	if (hisi_sas_intr_conv)
		dev_info(dev, "Enable interrupt converge\n");

	for (i = 0; i < hisi_hba->cq_nvecs; i++) {
		struct hisi_sas_cq *cq = &hisi_hba->cq[i];
		int nr = hisi_sas_intr_conv ? 16 : 16 + i;
		unsigned long irqflags = hisi_sas_intr_conv ? IRQF_SHARED :
							      IRQF_ONESHOT;

		cq->irq_no = pci_irq_vector(pdev, nr);
		rc = devm_request_threaded_irq(dev, cq->irq_no,
				      cq_interrupt_v3_hw,
				      cq_thread_v3_hw,
				      irqflags,
				      DRV_NAME " cq", cq);
		if (rc) {
			dev_err(dev, "could not request cq%d interrupt, rc=%d\n",
				i, rc);
			return -ENOENT;
		}
		cq->irq_mask = pci_irq_get_affinity(pdev, i + BASE_VECTORS_V3_HW);
		if (!cq->irq_mask) {
			dev_err(dev, "could not get cq%d irq affinity!\n", i);
			return -ENOENT;
		}
	}

	return 0;
}

static int hisi_sas_v3_init(struct hisi_hba *hisi_hba)
{
	int rc;

	rc = hw_init_v3_hw(hisi_hba);
	if (rc)
		return rc;

	rc = interrupt_init_v3_hw(hisi_hba);
	if (rc)
		return rc;

	return 0;
}

static void phy_set_linkrate_v3_hw(struct hisi_hba *hisi_hba, int phy_no,
		struct sas_phy_linkrates *r)
{
	enum sas_linkrate max = r->maximum_linkrate;
	u32 prog_phy_link_rate = hisi_sas_phy_read32(hisi_hba, phy_no,
						     PROG_PHY_LINK_RATE);

	prog_phy_link_rate &= ~CFG_PROG_PHY_LINK_RATE_MSK;
	prog_phy_link_rate |= hisi_sas_get_prog_phy_linkrate_mask(max);
	hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE,
			     prog_phy_link_rate);
}

static void interrupt_disable_v3_hw(struct hisi_hba *hisi_hba)
{
	struct pci_dev *pdev = hisi_hba->pci_dev;
	int i;

	synchronize_irq(pci_irq_vector(pdev, 1));
	synchronize_irq(pci_irq_vector(pdev, 2));
	synchronize_irq(pci_irq_vector(pdev, 11));
	for (i = 0; i < hisi_hba->queue_count; i++)
		hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK + 0x4 * i, 0x1);

	for (i = 0; i < hisi_hba->cq_nvecs; i++)
		synchronize_irq(pci_irq_vector(pdev, i + 16));

	hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xffffffff);
	hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xffffffff);
	hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffffffff);
	hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xffffffff);

	for (i = 0; i < hisi_hba->n_phy; i++) {
		hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff);
		hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffffff);
		hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x1);
		hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x1);
		hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x1);
	}
}

static u32 get_phys_state_v3_hw(struct hisi_hba *hisi_hba)
{
	return hisi_sas_read32(hisi_hba, PHY_STATE);
}

static int disable_host_v3_hw(struct hisi_hba *hisi_hba)
{
	struct device *dev = hisi_hba->dev;
	u32 status, reg_val;
	int rc;

	hisi_sas_sync_poll_cqs(hisi_hba);
	hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0x0);

	hisi_sas_stop_phys(hisi_hba);

	mdelay(10);

	reg_val = hisi_sas_read32(hisi_hba, AXI_MASTER_CFG_BASE +
				  AM_CTRL_GLOBAL);
	reg_val |= AM_CTRL_SHUTDOWN_REQ_MSK;
	hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE +
			 AM_CTRL_GLOBAL, reg_val);

	/* wait until bus idle */
	rc = hisi_sas_read32_poll_timeout(AXI_MASTER_CFG_BASE +
					  AM_CURR_TRANS_RETURN, status,
					  status == 0x3, 10, 100);
	if (rc) {
		dev_err(dev, "axi bus is not idle, rc=%d\n", rc);
		return rc;
	}

	return 0;
}

static int soft_reset_v3_hw(struct hisi_hba *hisi_hba)
{
	struct device *dev = hisi_hba->dev;
	int rc;

	interrupt_disable_v3_hw(hisi_hba);
	rc = disable_host_v3_hw(hisi_hba);
	if (rc) {
		dev_err(dev, "soft reset: disable host failed rc=%d\n", rc);
		return rc;
	}

	hisi_sas_init_mem(hisi_hba);

	return hw_init_v3_hw(hisi_hba);
}

static int write_gpio_v3_hw(struct hisi_hba *hisi_hba, u8 reg_type,
			u8 reg_index, u8 reg_count, u8 *write_data)
{
	struct device *dev = hisi_hba->dev;
	u32 *data = (u32 *)write_data;
	int i;

	switch (reg_type) {
	case SAS_GPIO_REG_TX:
		if ((reg_index + reg_count) > ((hisi_hba->n_phy + 3) / 4)) {
			dev_err(dev, "write gpio: invalid reg range[%d, %d]\n",
				reg_index, reg_index + reg_count - 1);
			return -EINVAL;
		}

		for (i = 0; i < reg_count; i++)
			hisi_sas_write32(hisi_hba,
					 SAS_GPIO_TX_0_1 + (reg_index + i) * 4,
					 data[i]);
		break;
	default:
		dev_err(dev, "write gpio: unsupported or bad reg type %d\n",
			reg_type);
		return -EINVAL;
	}

	return 0;
}

static void wait_cmds_complete_timeout_v3_hw(struct hisi_hba *hisi_hba,
					     int delay_ms, int timeout_ms)
{
	struct device *dev = hisi_hba->dev;
	int entries, entries_old = 0, time;

	for (time = 0; time < timeout_ms; time += delay_ms) {
		entries = hisi_sas_read32(hisi_hba, CQE_SEND_CNT);
		if (entries == entries_old)
			break;

		entries_old = entries;
		msleep(delay_ms);
	}

	if (time >= timeout_ms) {
		dev_dbg(dev, "Wait commands complete timeout!\n");
		return;
	}

	dev_dbg(dev, "wait commands complete %dms\n", time);
}

static ssize_t intr_conv_v3_hw_show(struct device *dev,
				    struct device_attribute *attr, char *buf)
{
	return scnprintf(buf, PAGE_SIZE, "%u\n", hisi_sas_intr_conv);
}
static DEVICE_ATTR_RO(intr_conv_v3_hw);

static void config_intr_coal_v3_hw(struct hisi_hba *hisi_hba)
{
	/* config those registers between enable and disable PHYs */
	hisi_sas_stop_phys(hisi_hba);

	if (hisi_hba->intr_coal_ticks == 0 ||
	    hisi_hba->intr_coal_count == 0) {
		hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1);
		hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x1);
		hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x1);
	} else {
		hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x3);
		hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME,
				 hisi_hba->intr_coal_ticks);
		hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT,
				 hisi_hba->intr_coal_count);
	}
	phys_init_v3_hw(hisi_hba);
}

static ssize_t intr_coal_ticks_v3_hw_show(struct device *dev,
					  struct device_attribute *attr,
					  char *buf)
{
	struct Scsi_Host *shost = class_to_shost(dev);
	struct hisi_hba *hisi_hba = shost_priv(shost);

	return scnprintf(buf, PAGE_SIZE, "%u\n",
			 hisi_hba->intr_coal_ticks);
}

static ssize_t intr_coal_ticks_v3_hw_store(struct device *dev,
					   struct device_attribute *attr,
					   const char *buf, size_t count)
{
	struct Scsi_Host *shost = class_to_shost(dev);
	struct hisi_hba *hisi_hba = shost_priv(shost);
	u32 intr_coal_ticks;
	int ret;

	ret = kstrtou32(buf, 10, &intr_coal_ticks);
	if (ret) {
		dev_err(dev, "Input data of interrupt coalesce unmatch\n");
		return -EINVAL;
	}

	if (intr_coal_ticks >= BIT(24)) {
		dev_err(dev, "intr_coal_ticks must be less than 2^24!\n");
		return -EINVAL;
	}

	hisi_hba->intr_coal_ticks = intr_coal_ticks;

	config_intr_coal_v3_hw(hisi_hba);

	return count;
}
static DEVICE_ATTR_RW(intr_coal_ticks_v3_hw);

static ssize_t intr_coal_count_v3_hw_show(struct device *dev,
					  struct device_attribute
					  *attr, char *buf)
{
	struct Scsi_Host *shost = class_to_shost(dev);
	struct hisi_hba *hisi_hba = shost_priv(shost);

	return scnprintf(buf, PAGE_SIZE, "%u\n",
			 hisi_hba->intr_coal_count);
}

static ssize_t intr_coal_count_v3_hw_store(struct device *dev,
		struct device_attribute
		*attr, const char *buf, size_t count)
{
	struct Scsi_Host *shost = class_to_shost(dev);
	struct hisi_hba *hisi_hba = shost_priv(shost);
	u32 intr_coal_count;
	int ret;

	ret = kstrtou32(buf, 10, &intr_coal_count);
	if (ret) {
		dev_err(dev, "Input data of interrupt coalesce unmatch\n");
		return -EINVAL;
	}

	if (intr_coal_count >= BIT(8)) {
		dev_err(dev, "intr_coal_count must be less than 2^8!\n");
		return -EINVAL;
	}

	hisi_hba->intr_coal_count = intr_coal_count;

	config_intr_coal_v3_hw(hisi_hba);

	return count;
}
static DEVICE_ATTR_RW(intr_coal_count_v3_hw);

static ssize_t iopoll_q_cnt_v3_hw_show(struct device *dev,
					  struct device_attribute
					  *attr, char *buf)
{
	struct Scsi_Host *shost = class_to_shost(dev);
	struct hisi_hba *hisi_hba = shost_priv(shost);

	return scnprintf(buf, PAGE_SIZE, "%u\n",
			 hisi_hba->iopoll_q_cnt);
}
static DEVICE_ATTR_RO(iopoll_q_cnt_v3_hw);

static int device_configure_v3_hw(struct scsi_device *sdev,
		struct queue_limits *lim)
{
	struct Scsi_Host *shost = dev_to_shost(&sdev->sdev_gendev);
	struct hisi_hba *hisi_hba = shost_priv(shost);
	int ret = hisi_sas_device_configure(sdev, lim);
	struct device *dev = hisi_hba->dev;

	if (ret)
		return ret;

	if (sdev->type == TYPE_ENCLOSURE)
		return 0;

	if (!device_link_add(&sdev->sdev_gendev, dev,
			     DL_FLAG_PM_RUNTIME | DL_FLAG_RPM_ACTIVE)) {
		if (pm_runtime_enabled(dev)) {
			dev_info(dev, "add device link failed, disable runtime PM for the host\n");
			pm_runtime_disable(dev);
		}
	}

	return 0;
}

static struct attribute *host_v3_hw_attrs[] = {
	&dev_attr_phy_event_threshold.attr,
	&dev_attr_intr_conv_v3_hw.attr,
	&dev_attr_intr_coal_ticks_v3_hw.attr,
	&dev_attr_intr_coal_count_v3_hw.attr,
	&dev_attr_iopoll_q_cnt_v3_hw.attr,
	NULL
};

ATTRIBUTE_GROUPS(host_v3_hw);

static const struct attribute_group *sdev_groups_v3_hw[] = {
	&sas_ata_sdev_attr_group,
	NULL
};

#define HISI_SAS_DEBUGFS_REG(x) {#x, x}

struct hisi_sas_debugfs_reg_lu {
	char *name;
	int off;
};

struct hisi_sas_debugfs_reg {
	const struct hisi_sas_debugfs_reg_lu *lu;
	int count;
	int base_off;
};

static const struct hisi_sas_debugfs_reg_lu debugfs_port_reg_lu[] = {
	HISI_SAS_DEBUGFS_REG(PHY_CFG),
	HISI_SAS_DEBUGFS_REG(HARD_PHY_LINKRATE),
	HISI_SAS_DEBUGFS_REG(PROG_PHY_LINK_RATE),
	HISI_SAS_DEBUGFS_REG(PHY_CTRL),
	HISI_SAS_DEBUGFS_REG(SL_CFG),
	HISI_SAS_DEBUGFS_REG(AIP_LIMIT),
	HISI_SAS_DEBUGFS_REG(SL_CONTROL),
	HISI_SAS_DEBUGFS_REG(RX_PRIMS_STATUS),
	HISI_SAS_DEBUGFS_REG(TX_ID_DWORD0),
	HISI_SAS_DEBUGFS_REG(TX_ID_DWORD1),
	HISI_SAS_DEBUGFS_REG(TX_ID_DWORD2),
	HISI_SAS_DEBUGFS_REG(TX_ID_DWORD3),
	HISI_SAS_DEBUGFS_REG(TX_ID_DWORD4),
	HISI_SAS_DEBUGFS_REG(TX_ID_DWORD5),
	HISI_SAS_DEBUGFS_REG(TX_ID_DWORD6),
	HISI_SAS_DEBUGFS_REG(TXID_AUTO),
	HISI_SAS_DEBUGFS_REG(RX_IDAF_DWORD0),
	HISI_SAS_DEBUGFS_REG(RXOP_CHECK_CFG_H),
	HISI_SAS_DEBUGFS_REG(STP_LINK_TIMER),
	HISI_SAS_DEBUGFS_REG(STP_LINK_TIMEOUT_STATE),
	HISI_SAS_DEBUGFS_REG(CON_CFG_DRIVER),
	HISI_SAS_DEBUGFS_REG(SAS_SSP_CON_TIMER_CFG),
	HISI_SAS_DEBUGFS_REG(SAS_SMP_CON_TIMER_CFG),
	HISI_SAS_DEBUGFS_REG(SAS_STP_CON_TIMER_CFG),
	HISI_SAS_DEBUGFS_REG(CHL_INT0),
	HISI_SAS_DEBUGFS_REG(CHL_INT1),
	HISI_SAS_DEBUGFS_REG(CHL_INT2),
	HISI_SAS_DEBUGFS_REG(CHL_INT0_MSK),
	HISI_SAS_DEBUGFS_REG(CHL_INT1_MSK),
	HISI_SAS_DEBUGFS_REG(CHL_INT2_MSK),
	HISI_SAS_DEBUGFS_REG(SAS_EC_INT_COAL_TIME),
	HISI_SAS_DEBUGFS_REG(CHL_INT_COAL_EN),
	HISI_SAS_DEBUGFS_REG(SAS_RX_TRAIN_TIMER),
	HISI_SAS_DEBUGFS_REG(PHY_CTRL_RDY_MSK),
	HISI_SAS_DEBUGFS_REG(PHYCTRL_NOT_RDY_MSK),
	HISI_SAS_DEBUGFS_REG(PHYCTRL_DWS_RESET_MSK),
	HISI_SAS_DEBUGFS_REG(PHYCTRL_PHY_ENA_MSK),
	HISI_SAS_DEBUGFS_REG(SL_RX_BCAST_CHK_MSK),
	HISI_SAS_DEBUGFS_REG(PHYCTRL_OOB_RESTART_MSK),
	HISI_SAS_DEBUGFS_REG(DMA_TX_STATUS),
	HISI_SAS_DEBUGFS_REG(DMA_RX_STATUS),
	HISI_SAS_DEBUGFS_REG(COARSETUNE_TIME),
	HISI_SAS_DEBUGFS_REG(ERR_CNT_DWS_LOST),
	HISI_SAS_DEBUGFS_REG(ERR_CNT_RESET_PROB),
	HISI_SAS_DEBUGFS_REG(ERR_CNT_INVLD_DW),
	HISI_SAS_DEBUGFS_REG(ERR_CNT_CODE_ERR),
	HISI_SAS_DEBUGFS_REG(ERR_CNT_DISP_ERR),
	{}
};

static const struct hisi_sas_debugfs_reg debugfs_port_reg = {
	.lu = debugfs_port_reg_lu,
	.count = 0x100,
	.base_off = PORT_BASE,
};

static const struct hisi_sas_debugfs_reg_lu debugfs_global_reg_lu[] = {
	HISI_SAS_DEBUGFS_REG(DLVRY_QUEUE_ENABLE),
	HISI_SAS_DEBUGFS_REG(PHY_CONTEXT),
	HISI_SAS_DEBUGFS_REG(PHY_STATE),
	HISI_SAS_DEBUGFS_REG(PHY_PORT_NUM_MA),
	HISI_SAS_DEBUGFS_REG(PHY_CONN_RATE),
	HISI_SAS_DEBUGFS_REG(ITCT_CLR),
	HISI_SAS_DEBUGFS_REG(IO_SATA_BROKEN_MSG_ADDR_LO),
	HISI_SAS_DEBUGFS_REG(IO_SATA_BROKEN_MSG_ADDR_HI),
	HISI_SAS_DEBUGFS_REG(SATA_INITI_D2H_STORE_ADDR_LO),
	HISI_SAS_DEBUGFS_REG(SATA_INITI_D2H_STORE_ADDR_HI),
	HISI_SAS_DEBUGFS_REG(CFG_MAX_TAG),
	HISI_SAS_DEBUGFS_REG(TRANS_LOCK_ICT_TIME),
	HISI_SAS_DEBUGFS_REG(HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL),
	HISI_SAS_DEBUGFS_REG(HGC_SAS_TXFAIL_RETRY_CTRL),
	HISI_SAS_DEBUGFS_REG(HGC_GET_ITV_TIME),
	HISI_SAS_DEBUGFS_REG(DEVICE_MSG_WORK_MODE),
	HISI_SAS_DEBUGFS_REG(OPENA_WT_CONTI_TIME),
	HISI_SAS_DEBUGFS_REG(I_T_NEXUS_LOSS_TIME),
	HISI_SAS_DEBUGFS_REG(MAX_CON_TIME_LIMIT_TIME),
	HISI_SAS_DEBUGFS_REG(BUS_INACTIVE_LIMIT_TIME),
	HISI_SAS_DEBUGFS_REG(REJECT_TO_OPEN_LIMIT_TIME),
	HISI_SAS_DEBUGFS_REG(CQ_INT_CONVERGE_EN),
	HISI_SAS_DEBUGFS_REG(CFG_AGING_TIME),
	HISI_SAS_DEBUGFS_REG(HGC_DFX_CFG2),
	HISI_SAS_DEBUGFS_REG(CFG_ABT_SET_QUERY_IPTT),
	HISI_SAS_DEBUGFS_REG(CFG_ABT_SET_IPTT_DONE),
	HISI_SAS_DEBUGFS_REG(HGC_IOMB_PROC1_STATUS),
	HISI_SAS_DEBUGFS_REG(CHNL_INT_STATUS),
	HISI_SAS_DEBUGFS_REG(HGC_AXI_FIFO_ERR_INFO),
	HISI_SAS_DEBUGFS_REG(INT_COAL_EN),
	HISI_SAS_DEBUGFS_REG(OQ_INT_COAL_TIME),
	HISI_SAS_DEBUGFS_REG(OQ_INT_COAL_CNT),
	HISI_SAS_DEBUGFS_REG(ENT_INT_COAL_TIME),
	HISI_SAS_DEBUGFS_REG(ENT_INT_COAL_CNT),
	HISI_SAS_DEBUGFS_REG(OQ_INT_SRC),
	HISI_SAS_DEBUGFS_REG(OQ_INT_SRC_MSK),
	HISI_SAS_DEBUGFS_REG(ENT_INT_SRC1),
	HISI_SAS_DEBUGFS_REG(ENT_INT_SRC2),
	HISI_SAS_DEBUGFS_REG(ENT_INT_SRC3),
	HISI_SAS_DEBUGFS_REG(ENT_INT_SRC_MSK1),
	HISI_SAS_DEBUGFS_REG(ENT_INT_SRC_MSK2),
	HISI_SAS_DEBUGFS_REG(ENT_INT_SRC_MSK3),
	HISI_SAS_DEBUGFS_REG(CHNL_PHYUPDOWN_INT_MSK),
	HISI_SAS_DEBUGFS_REG(CHNL_ENT_INT_MSK),
	HISI_SAS_DEBUGFS_REG(HGC_COM_INT_MSK),
	HISI_SAS_DEBUGFS_REG(SAS_ECC_INTR),
	HISI_SAS_DEBUGFS_REG(SAS_ECC_INTR_MSK),
	HISI_SAS_DEBUGFS_REG(HGC_ERR_STAT_EN),
	HISI_SAS_DEBUGFS_REG(CQE_SEND_CNT),
	HISI_SAS_DEBUGFS_REG(DLVRY_Q_0_DEPTH),
	HISI_SAS_DEBUGFS_REG(DLVRY_Q_0_WR_PTR),
	HISI_SAS_DEBUGFS_REG(DLVRY_Q_0_RD_PTR),
	HISI_SAS_DEBUGFS_REG(HYPER_STREAM_ID_EN_CFG),
	HISI_SAS_DEBUGFS_REG(OQ0_INT_SRC_MSK),
	HISI_SAS_DEBUGFS_REG(COMPL_Q_0_DEPTH),
	HISI_SAS_DEBUGFS_REG(COMPL_Q_0_WR_PTR),
	HISI_SAS_DEBUGFS_REG(COMPL_Q_0_RD_PTR),
	HISI_SAS_DEBUGFS_REG(AWQOS_AWCACHE_CFG),
	HISI_SAS_DEBUGFS_REG(ARQOS_ARCACHE_CFG),
	HISI_SAS_DEBUGFS_REG(HILINK_ERR_DFX),
	HISI_SAS_DEBUGFS_REG(SAS_GPIO_CFG_0),
	HISI_SAS_DEBUGFS_REG(SAS_GPIO_CFG_1),
	HISI_SAS_DEBUGFS_REG(SAS_GPIO_TX_0_1),
	HISI_SAS_DEBUGFS_REG(SAS_CFG_DRIVE_VLD),
	{}
};

static const struct hisi_sas_debugfs_reg debugfs_global_reg = {
	.lu = debugfs_global_reg_lu,
	.count = 0x800,
};

static const struct hisi_sas_debugfs_reg_lu debugfs_axi_reg_lu[] = {
	HISI_SAS_DEBUGFS_REG(AM_CFG_MAX_TRANS),
	HISI_SAS_DEBUGFS_REG(AM_CFG_SINGLE_PORT_MAX_TRANS),
	HISI_SAS_DEBUGFS_REG(AXI_CFG),
	HISI_SAS_DEBUGFS_REG(AM_ROB_ECC_ERR_ADDR),
	{}
};

static const struct hisi_sas_debugfs_reg debugfs_axi_reg = {
	.lu = debugfs_axi_reg_lu,
	.count = 0x61,
	.base_off = AXI_MASTER_CFG_BASE,
};

static const struct hisi_sas_debugfs_reg_lu debugfs_ras_reg_lu[] = {
	HISI_SAS_DEBUGFS_REG(SAS_RAS_INTR0),
	HISI_SAS_DEBUGFS_REG(SAS_RAS_INTR1),
	HISI_SAS_DEBUGFS_REG(SAS_RAS_INTR0_MASK),
	HISI_SAS_DEBUGFS_REG(SAS_RAS_INTR1_MASK),
	HISI_SAS_DEBUGFS_REG(CFG_SAS_RAS_INTR_MASK),
	HISI_SAS_DEBUGFS_REG(SAS_RAS_INTR2),
	HISI_SAS_DEBUGFS_REG(SAS_RAS_INTR2_MASK),
	{}
};

static const struct hisi_sas_debugfs_reg debugfs_ras_reg = {
	.lu = debugfs_ras_reg_lu,
	.count = 0x10,
	.base_off = RAS_BASE,
};

static void debugfs_snapshot_prepare_v3_hw(struct hisi_hba *hisi_hba)
{
	struct Scsi_Host *shost = hisi_hba->shost;

	scsi_block_requests(shost);
	wait_cmds_complete_timeout_v3_hw(hisi_hba, 100, 5000);

	set_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);
	hisi_sas_sync_cqs(hisi_hba);
	hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0);
}

static void debugfs_snapshot_restore_v3_hw(struct hisi_hba *hisi_hba)
{
	struct Scsi_Host *shost = hisi_hba->shost;

	hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE,
			 (u32)((1ULL << hisi_hba->queue_count) - 1));

	clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);
	scsi_unblock_requests(shost);
}

static void read_iost_itct_cache_v3_hw(struct hisi_hba *hisi_hba,
				       enum hisi_sas_debugfs_cache_type type,
				       u32 *cache)
{
	u32 cache_dw_size = HISI_SAS_IOST_ITCT_CACHE_DW_SZ *
			    HISI_SAS_IOST_ITCT_CACHE_NUM;
	struct device *dev = hisi_hba->dev;
	u32 *buf = cache;
	u32 i, val;

	hisi_sas_write32(hisi_hba, TAB_RD_TYPE, type);

	for (i = 0; i < HISI_SAS_IOST_ITCT_CACHE_DW_SZ; i++) {
		val = hisi_sas_read32(hisi_hba, TAB_DFX);
		if (val == 0xffffffff)
			break;
	}

	if (val != 0xffffffff) {
		dev_err(dev, "Issue occurred in reading IOST/ITCT cache!\n");
		return;
	}

	memset(buf, 0, cache_dw_size * 4);
	buf[0] = val;

	for (i = 1; i < cache_dw_size; i++)
		buf[i] = hisi_sas_read32(hisi_hba, TAB_DFX);
}

static void hisi_sas_bist_test_prep_v3_hw(struct hisi_hba *hisi_hba)
{
	u32 reg_val;
	int phy_no = hisi_hba->debugfs_bist_phy_no;
	int i;

	/* disable PHY */
	hisi_sas_phy_enable(hisi_hba, phy_no, 0);

	/* update FFE */
	for (i = 0; i < FFE_CFG_MAX; i++)
		hisi_sas_phy_write32(hisi_hba, phy_no, TXDEEMPH_G1 + (i * 0x4),
				     hisi_hba->debugfs_bist_ffe[phy_no][i]);

	/* disable ALOS */
	reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, SERDES_CFG);
	reg_val |= CFG_ALOS_CHK_DISABLE_MSK;
	hisi_sas_phy_write32(hisi_hba, phy_no, SERDES_CFG, reg_val);
}

static void hisi_sas_bist_test_restore_v3_hw(struct hisi_hba *hisi_hba)
{
	u32 reg_val;
	int phy_no = hisi_hba->debugfs_bist_phy_no;

	/* disable loopback */
	reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, SAS_PHY_BIST_CTRL);
	reg_val &= ~(CFG_RX_BIST_EN_MSK | CFG_TX_BIST_EN_MSK |
		     CFG_BIST_TEST_MSK);
	hisi_sas_phy_write32(hisi_hba, phy_no, SAS_PHY_BIST_CTRL, reg_val);

	/* enable ALOS */
	reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, SERDES_CFG);
	reg_val &= ~CFG_ALOS_CHK_DISABLE_MSK;
	hisi_sas_phy_write32(hisi_hba, phy_no, SERDES_CFG, reg_val);

	/* restore the linkrate */
	reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, PROG_PHY_LINK_RATE);
	/* init OOB link rate as 1.5 Gbits */
	reg_val &= ~CFG_PROG_OOB_PHY_LINK_RATE_MSK;
	reg_val |= (0x8 << CFG_PROG_OOB_PHY_LINK_RATE_OFF);
	hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE, reg_val);

	/* enable PHY */
	hisi_sas_phy_enable(hisi_hba, phy_no, 1);
}

#define SAS_PHY_BIST_CODE_INIT	0x1
#define SAS_PHY_BIST_CODE1_INIT	0X80
static int debugfs_set_bist_v3_hw(struct hisi_hba *hisi_hba, bool enable)
{
	u32 reg_val, mode_tmp;
	u32 linkrate = hisi_hba->debugfs_bist_linkrate;
	u32 phy_no = hisi_hba->debugfs_bist_phy_no;
	u32 *ffe = hisi_hba->debugfs_bist_ffe[phy_no];
	u32 code_mode = hisi_hba->debugfs_bist_code_mode;
	u32 path_mode = hisi_hba->debugfs_bist_mode;
	u32 *fix_code = &hisi_hba->debugfs_bist_fixed_code[0];
	struct device *dev = hisi_hba->dev;

	dev_info(dev, "BIST info:phy%d link_rate=%d code_mode=%d path_mode=%d ffe={0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x} fixed_code={0x%x, 0x%x}\n",
		 phy_no, linkrate, code_mode, path_mode,
		 ffe[FFE_SAS_1_5_GBPS], ffe[FFE_SAS_3_0_GBPS],
		 ffe[FFE_SAS_6_0_GBPS], ffe[FFE_SAS_12_0_GBPS],
		 ffe[FFE_SATA_1_5_GBPS], ffe[FFE_SATA_3_0_GBPS],
		 ffe[FFE_SATA_6_0_GBPS], fix_code[FIXED_CODE],
		 fix_code[FIXED_CODE_1]);
	mode_tmp = path_mode ? 2 : 1;
	if (enable) {
		/* some preparations before bist test */
		hisi_sas_bist_test_prep_v3_hw(hisi_hba);

		/* set linkrate of bit test*/
		reg_val = hisi_sas_phy_read32(hisi_hba, phy_no,
					      PROG_PHY_LINK_RATE);
		reg_val &= ~CFG_PROG_OOB_PHY_LINK_RATE_MSK;
		reg_val |= (linkrate << CFG_PROG_OOB_PHY_LINK_RATE_OFF);
		hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE,
				     reg_val);

		/* set code mode of bit test */
		reg_val = hisi_sas_phy_read32(hisi_hba, phy_no,
					      SAS_PHY_BIST_CTRL);
		reg_val &= ~(CFG_BIST_MODE_SEL_MSK | CFG_LOOP_TEST_MODE_MSK |
			     CFG_RX_BIST_EN_MSK | CFG_TX_BIST_EN_MSK |
			     CFG_BIST_TEST_MSK);
		reg_val |= ((code_mode << CFG_BIST_MODE_SEL_OFF) |
			    (mode_tmp << CFG_LOOP_TEST_MODE_OFF) |
			    CFG_BIST_TEST_MSK);
		hisi_sas_phy_write32(hisi_hba, phy_no, SAS_PHY_BIST_CTRL,
				     reg_val);

		/* set the bist init value */
		if (code_mode == HISI_SAS_BIST_CODE_MODE_FIXED_DATA) {
			reg_val = hisi_hba->debugfs_bist_fixed_code[0];
			hisi_sas_phy_write32(hisi_hba, phy_no,
					     SAS_PHY_BIST_CODE, reg_val);

			reg_val = hisi_hba->debugfs_bist_fixed_code[1];
			hisi_sas_phy_write32(hisi_hba, phy_no,
					     SAS_PHY_BIST_CODE1, reg_val);
		} else {
			hisi_sas_phy_write32(hisi_hba, phy_no,
					     SAS_PHY_BIST_CODE,
					     SAS_PHY_BIST_CODE_INIT);
			hisi_sas_phy_write32(hisi_hba, phy_no,
					     SAS_PHY_BIST_CODE1,
					     SAS_PHY_BIST_CODE1_INIT);
		}

		mdelay(100);
		reg_val |= (CFG_RX_BIST_EN_MSK | CFG_TX_BIST_EN_MSK);
		hisi_sas_phy_write32(hisi_hba, phy_no, SAS_PHY_BIST_CTRL,
				     reg_val);

		/* clear error bit */
		mdelay(100);
		hisi_sas_phy_read32(hisi_hba, phy_no, SAS_BIST_ERR_CNT);
	} else {
		/* disable bist test and recover it */
		hisi_hba->debugfs_bist_cnt += hisi_sas_phy_read32(hisi_hba,
				phy_no, SAS_BIST_ERR_CNT);
		hisi_sas_bist_test_restore_v3_hw(hisi_hba);
	}

	return 0;
}

static void hisi_sas_map_queues(struct Scsi_Host *shost)
{
	struct hisi_hba *hisi_hba = shost_priv(shost);
	struct blk_mq_queue_map *qmap;
	int i, qoff;

	for (i = 0, qoff = 0; i < shost->nr_maps; i++) {
		qmap = &shost->tag_set.map[i];
		if (i == HCTX_TYPE_DEFAULT) {
			qmap->nr_queues = hisi_hba->cq_nvecs;
		} else if (i == HCTX_TYPE_POLL) {
			qmap->nr_queues = hisi_hba->iopoll_q_cnt;
		} else {
			qmap->nr_queues = 0;
			continue;
		}

		/* At least one interrupt hardware queue */
		if (!qmap->nr_queues)
			WARN_ON(i == HCTX_TYPE_DEFAULT);
		qmap->queue_offset = qoff;
		if (i == HCTX_TYPE_POLL)
			blk_mq_map_queues(qmap);
		else
			blk_mq_pci_map_queues(qmap, hisi_hba->pci_dev,
					      BASE_VECTORS_V3_HW);
		qoff += qmap->nr_queues;
	}
}

static const struct scsi_host_template sht_v3_hw = {
	LIBSAS_SHT_BASE_NO_SLAVE_INIT
	.device_configure	= device_configure_v3_hw,
	.scan_finished		= hisi_sas_scan_finished,
	.scan_start		= hisi_sas_scan_start,
	.map_queues		= hisi_sas_map_queues,
	.sg_tablesize		= HISI_SAS_SGE_PAGE_CNT,
	.sg_prot_tablesize	= HISI_SAS_SGE_PAGE_CNT,
	.slave_alloc		= hisi_sas_slave_alloc,
	.shost_groups		= host_v3_hw_groups,
	.sdev_groups		= sdev_groups_v3_hw,
	.tag_alloc_policy	= BLK_TAG_ALLOC_RR,
	.host_reset             = hisi_sas_host_reset,
	.host_tagset		= 1,
	.mq_poll		= queue_complete_v3_hw,
};

static const struct hisi_sas_hw hisi_sas_v3_hw = {
	.setup_itct = setup_itct_v3_hw,
	.get_wideport_bitmap = get_wideport_bitmap_v3_hw,
	.complete_hdr_size = sizeof(struct hisi_sas_complete_v3_hdr),
	.clear_itct = clear_itct_v3_hw,
	.sl_notify_ssp = sl_notify_ssp_v3_hw,
	.prep_ssp = prep_ssp_v3_hw,
	.prep_smp = prep_smp_v3_hw,
	.prep_stp = prep_ata_v3_hw,
	.prep_abort = prep_abort_v3_hw,
	.start_delivery = start_delivery_v3_hw,
	.phys_init = phys_init_v3_hw,
	.phy_start = start_phy_v3_hw,
	.phy_disable = disable_phy_v3_hw,
	.phy_hard_reset = phy_hard_reset_v3_hw,
	.phy_get_max_linkrate = phy_get_max_linkrate_v3_hw,
	.phy_set_linkrate = phy_set_linkrate_v3_hw,
	.dereg_device = dereg_device_v3_hw,
	.soft_reset = soft_reset_v3_hw,
	.get_phys_state = get_phys_state_v3_hw,
	.get_events = phy_get_events_v3_hw,
	.write_gpio = write_gpio_v3_hw,
	.wait_cmds_complete_timeout = wait_cmds_complete_timeout_v3_hw,
	.debugfs_snapshot_regs = debugfs_snapshot_regs_v3_hw,
};

static struct Scsi_Host *
hisi_sas_shost_alloc_pci(struct pci_dev *pdev)
{
	struct Scsi_Host *shost;
	struct hisi_hba *hisi_hba;
	struct device *dev = &pdev->dev;

	shost = scsi_host_alloc(&sht_v3_hw, sizeof(*hisi_hba));
	if (!shost) {
		dev_err(dev, "shost alloc failed\n");
		return NULL;
	}
	hisi_hba = shost_priv(shost);

	INIT_WORK(&hisi_hba->rst_work, hisi_sas_rst_work_handler);
	hisi_hba->hw = &hisi_sas_v3_hw;
	hisi_hba->pci_dev = pdev;
	hisi_hba->dev = dev;
	hisi_hba->shost = shost;
	SHOST_TO_SAS_HA(shost) = &hisi_hba->sha;

	if (prot_mask & ~HISI_SAS_PROT_MASK)
		dev_err(dev, "unsupported protection mask 0x%x, using default (0x0)\n",
			prot_mask);
	else
		hisi_hba->prot_mask = prot_mask;

	if (hisi_sas_get_fw_info(hisi_hba) < 0)
		goto err_out;

	if (experimental_iopoll_q_cnt < 0 ||
		experimental_iopoll_q_cnt >= hisi_hba->queue_count)
		dev_err(dev, "iopoll queue count %d cannot exceed or equal 16, using default 0\n",
			experimental_iopoll_q_cnt);
	else
		hisi_hba->iopoll_q_cnt = experimental_iopoll_q_cnt;

	if (hisi_sas_alloc(hisi_hba)) {
		hisi_sas_free(hisi_hba);
		goto err_out;
	}

	return shost;
err_out:
	scsi_host_put(shost);
	dev_err(dev, "shost alloc failed\n");
	return NULL;
}

static void debugfs_snapshot_cq_reg_v3_hw(struct hisi_hba *hisi_hba)
{
	int queue_entry_size = hisi_hba->hw->complete_hdr_size;
	int dump_index = hisi_hba->debugfs_dump_index;
	int i;

	for (i = 0; i < hisi_hba->queue_count; i++)
		memcpy(hisi_hba->debugfs_cq[dump_index][i].complete_hdr,
		       hisi_hba->complete_hdr[i],
		       HISI_SAS_QUEUE_SLOTS * queue_entry_size);
}

static void debugfs_snapshot_dq_reg_v3_hw(struct hisi_hba *hisi_hba)
{
	int queue_entry_size = sizeof(struct hisi_sas_cmd_hdr);
	int dump_index = hisi_hba->debugfs_dump_index;
	int i;

	for (i = 0; i < hisi_hba->queue_count; i++) {
		struct hisi_sas_cmd_hdr *debugfs_cmd_hdr, *cmd_hdr;
		int j;

		debugfs_cmd_hdr = hisi_hba->debugfs_dq[dump_index][i].hdr;
		cmd_hdr = hisi_hba->cmd_hdr[i];

		for (j = 0; j < HISI_SAS_QUEUE_SLOTS; j++)
			memcpy(&debugfs_cmd_hdr[j], &cmd_hdr[j],
			       queue_entry_size);
	}
}

static void debugfs_snapshot_port_reg_v3_hw(struct hisi_hba *hisi_hba)
{
	int dump_index = hisi_hba->debugfs_dump_index;
	const struct hisi_sas_debugfs_reg *port = &debugfs_port_reg;
	int i, phy_cnt;
	u32 offset;
	u32 *databuf;

	for (phy_cnt = 0; phy_cnt < hisi_hba->n_phy; phy_cnt++) {
		databuf = hisi_hba->debugfs_port_reg[dump_index][phy_cnt].data;
		for (i = 0; i < port->count; i++, databuf++) {
			offset = port->base_off + 4 * i;
			*databuf = hisi_sas_phy_read32(hisi_hba, phy_cnt,
						       offset);
		}
	}
}

static void debugfs_snapshot_global_reg_v3_hw(struct hisi_hba *hisi_hba)
{
	int dump_index = hisi_hba->debugfs_dump_index;
	u32 *databuf = hisi_hba->debugfs_regs[dump_index][DEBUGFS_GLOBAL].data;
	int i;

	for (i = 0; i < debugfs_global_reg.count; i++, databuf++)
		*databuf = hisi_sas_read32(hisi_hba, 4 * i);
}

static void debugfs_snapshot_axi_reg_v3_hw(struct hisi_hba *hisi_hba)
{
	int dump_index = hisi_hba->debugfs_dump_index;
	u32 *databuf = hisi_hba->debugfs_regs[dump_index][DEBUGFS_AXI].data;
	const struct hisi_sas_debugfs_reg *axi = &debugfs_axi_reg;
	int i;

	for (i = 0; i < axi->count; i++, databuf++)
		*databuf = hisi_sas_read32(hisi_hba, 4 * i + axi->base_off);
}

static void debugfs_snapshot_ras_reg_v3_hw(struct hisi_hba *hisi_hba)
{
	int dump_index = hisi_hba->debugfs_dump_index;
	u32 *databuf = hisi_hba->debugfs_regs[dump_index][DEBUGFS_RAS].data;
	const struct hisi_sas_debugfs_reg *ras = &debugfs_ras_reg;
	int i;

	for (i = 0; i < ras->count; i++, databuf++)
		*databuf = hisi_sas_read32(hisi_hba, 4 * i + ras->base_off);
}

static void debugfs_snapshot_itct_reg_v3_hw(struct hisi_hba *hisi_hba)
{
	int dump_index = hisi_hba->debugfs_dump_index;
	void *cachebuf = hisi_hba->debugfs_itct_cache[dump_index].cache;
	void *databuf = hisi_hba->debugfs_itct[dump_index].itct;
	struct hisi_sas_itct *itct;
	int i;

	read_iost_itct_cache_v3_hw(hisi_hba, HISI_SAS_ITCT_CACHE, cachebuf);

	itct = hisi_hba->itct;

	for (i = 0; i < HISI_SAS_MAX_ITCT_ENTRIES; i++, itct++) {
		memcpy(databuf, itct, sizeof(struct hisi_sas_itct));
		databuf += sizeof(struct hisi_sas_itct);
	}
}

static void debugfs_snapshot_iost_reg_v3_hw(struct hisi_hba *hisi_hba)
{
	int dump_index = hisi_hba->debugfs_dump_index;
	int max_command_entries = HISI_SAS_MAX_COMMANDS;
	void *cachebuf = hisi_hba->debugfs_iost_cache[dump_index].cache;
	void *databuf = hisi_hba->debugfs_iost[dump_index].iost;
	struct hisi_sas_iost *iost;
	int i;

	read_iost_itct_cache_v3_hw(hisi_hba, HISI_SAS_IOST_CACHE, cachebuf);

	iost = hisi_hba->iost;

	for (i = 0; i < max_command_entries; i++, iost++) {
		memcpy(databuf, iost, sizeof(struct hisi_sas_iost));
		databuf += sizeof(struct hisi_sas_iost);
	}
}

static const char *
debugfs_to_reg_name_v3_hw(int off, int base_off,
			  const struct hisi_sas_debugfs_reg_lu *lu)
{
	for (; lu->name; lu++) {
		if (off == lu->off - base_off)
			return lu->name;
	}

	return NULL;
}

static void debugfs_print_reg_v3_hw(u32 *regs_val, struct seq_file *s,
				    const struct hisi_sas_debugfs_reg *reg)
{
	int i;

	for (i = 0; i < reg->count; i++) {
		int off = i * 4;
		const char *name;

		name = debugfs_to_reg_name_v3_hw(off, reg->base_off,
						 reg->lu);

		if (name)
			seq_printf(s, "0x%08x 0x%08x %s\n", off,
				   regs_val[i], name);
		else
			seq_printf(s, "0x%08x 0x%08x\n", off,
				   regs_val[i]);
	}
}

static int debugfs_global_v3_hw_show(struct seq_file *s, void *p)
{
	struct hisi_sas_debugfs_regs *global = s->private;

	debugfs_print_reg_v3_hw(global->data, s,
				&debugfs_global_reg);

	return 0;
}
DEFINE_SHOW_ATTRIBUTE(debugfs_global_v3_hw);

static int debugfs_axi_v3_hw_show(struct seq_file *s, void *p)
{
	struct hisi_sas_debugfs_regs *axi = s->private;

	debugfs_print_reg_v3_hw(axi->data, s,
				&debugfs_axi_reg);

	return 0;
}
DEFINE_SHOW_ATTRIBUTE(debugfs_axi_v3_hw);

static int debugfs_ras_v3_hw_show(struct seq_file *s, void *p)
{
	struct hisi_sas_debugfs_regs *ras = s->private;

	debugfs_print_reg_v3_hw(ras->data, s,
				&debugfs_ras_reg);

	return 0;
}
DEFINE_SHOW_ATTRIBUTE(debugfs_ras_v3_hw);

static int debugfs_port_v3_hw_show(struct seq_file *s, void *p)
{
	struct hisi_sas_debugfs_port *port = s->private;
	const struct hisi_sas_debugfs_reg *reg_port = &debugfs_port_reg;

	debugfs_print_reg_v3_hw(port->data, s, reg_port);

	return 0;
}
DEFINE_SHOW_ATTRIBUTE(debugfs_port_v3_hw);

static void debugfs_show_row_64_v3_hw(struct seq_file *s, int index,
				      int sz, __le64 *ptr)
{
	int i;

	/* completion header size not fixed per HW version */
	seq_printf(s, "index %04d:\n\t", index);
	for (i = 1; i <= sz / 8; i++, ptr++) {
		seq_printf(s, " 0x%016llx", le64_to_cpu(*ptr));
		if (!(i % 2))
			seq_puts(s, "\n\t");
	}

	seq_puts(s, "\n");
}

static void debugfs_show_row_32_v3_hw(struct seq_file *s, int index,
				      int sz, __le32 *ptr)
{
	int i;

	/* completion header size not fixed per HW version */
	seq_printf(s, "index %04d:\n\t", index);
	for (i = 1; i <= sz / 4; i++, ptr++) {
		seq_printf(s, " 0x%08x", le32_to_cpu(*ptr));
		if (!(i % 4))
			seq_puts(s, "\n\t");
	}
	seq_puts(s, "\n");
}

static void debugfs_cq_show_slot_v3_hw(struct seq_file *s, int slot,
				       struct hisi_sas_debugfs_cq *debugfs_cq)
{
	struct hisi_sas_cq *cq = debugfs_cq->cq;
	struct hisi_hba *hisi_hba = cq->hisi_hba;
	__le32 *complete_hdr = debugfs_cq->complete_hdr +
			       (hisi_hba->hw->complete_hdr_size * slot);

	debugfs_show_row_32_v3_hw(s, slot,
				  hisi_hba->hw->complete_hdr_size,
				  complete_hdr);
}

static int debugfs_cq_v3_hw_show(struct seq_file *s, void *p)
{
	struct hisi_sas_debugfs_cq *debugfs_cq = s->private;
	int slot;

	for (slot = 0; slot < HISI_SAS_QUEUE_SLOTS; slot++)
		debugfs_cq_show_slot_v3_hw(s, slot, debugfs_cq);

	return 0;
}
DEFINE_SHOW_ATTRIBUTE(debugfs_cq_v3_hw);

static void debugfs_dq_show_slot_v3_hw(struct seq_file *s, int slot,
				       void *dq_ptr)
{
	struct hisi_sas_debugfs_dq *debugfs_dq = dq_ptr;
	void *cmd_queue = debugfs_dq->hdr;
	__le32 *cmd_hdr = cmd_queue +
		sizeof(struct hisi_sas_cmd_hdr) * slot;

	debugfs_show_row_32_v3_hw(s, slot, sizeof(struct hisi_sas_cmd_hdr),
				  cmd_hdr);
}

static int debugfs_dq_v3_hw_show(struct seq_file *s, void *p)
{
	int slot;

	for (slot = 0; slot < HISI_SAS_QUEUE_SLOTS; slot++)
		debugfs_dq_show_slot_v3_hw(s, slot, s->private);

	return 0;
}
DEFINE_SHOW_ATTRIBUTE(debugfs_dq_v3_hw);

static int debugfs_iost_v3_hw_show(struct seq_file *s, void *p)
{
	struct hisi_sas_debugfs_iost *debugfs_iost = s->private;
	struct hisi_sas_iost *iost = debugfs_iost->iost;
	int i, max_command_entries = HISI_SAS_MAX_COMMANDS;

	for (i = 0; i < max_command_entries; i++, iost++) {
		__le64 *data = &iost->qw0;

		debugfs_show_row_64_v3_hw(s, i, sizeof(*iost), data);
	}

	return 0;
}
DEFINE_SHOW_ATTRIBUTE(debugfs_iost_v3_hw);

static int debugfs_iost_cache_v3_hw_show(struct seq_file *s, void *p)
{
	struct hisi_sas_debugfs_iost_cache *debugfs_iost_cache = s->private;
	struct hisi_sas_iost_itct_cache *iost_cache =
						debugfs_iost_cache->cache;
	u32 cache_size = HISI_SAS_IOST_ITCT_CACHE_DW_SZ * 4;
	int i, tab_idx;
	__le64 *iost;

	for (i = 0; i < HISI_SAS_IOST_ITCT_CACHE_NUM; i++, iost_cache++) {
		/*
		 * Data struct of IOST cache:
		 * Data[1]: BIT0~15: Table index
		 *	    Bit16:   Valid mask
		 * Data[2]~[9]: IOST table
		 */
		tab_idx = (iost_cache->data[1] & 0xffff);
		iost = (__le64 *)iost_cache;

		debugfs_show_row_64_v3_hw(s, tab_idx, cache_size, iost);
	}

	return 0;
}
DEFINE_SHOW_ATTRIBUTE(debugfs_iost_cache_v3_hw);

static int debugfs_itct_v3_hw_show(struct seq_file *s, void *p)
{
	int i;
	struct hisi_sas_debugfs_itct *debugfs_itct = s->private;
	struct hisi_sas_itct *itct = debugfs_itct->itct;

	for (i = 0; i < HISI_SAS_MAX_ITCT_ENTRIES; i++, itct++) {
		__le64 *data = &itct->qw0;

		debugfs_show_row_64_v3_hw(s, i, sizeof(*itct), data);
	}

	return 0;
}
DEFINE_SHOW_ATTRIBUTE(debugfs_itct_v3_hw);

static int debugfs_itct_cache_v3_hw_show(struct seq_file *s, void *p)
{
	struct hisi_sas_debugfs_itct_cache *debugfs_itct_cache = s->private;
	struct hisi_sas_iost_itct_cache *itct_cache =
						debugfs_itct_cache->cache;
	u32 cache_size = HISI_SAS_IOST_ITCT_CACHE_DW_SZ * 4;
	int i, tab_idx;
	__le64 *itct;

	for (i = 0; i < HISI_SAS_IOST_ITCT_CACHE_NUM; i++, itct_cache++) {
		/*
		 * Data struct of ITCT cache:
		 * Data[1]: BIT0~15: Table index
		 *	    Bit16:   Valid mask
		 * Data[2]~[9]: ITCT table
		 */
		tab_idx = itct_cache->data[1] & 0xffff;
		itct = (__le64 *)itct_cache;

		debugfs_show_row_64_v3_hw(s, tab_idx, cache_size, itct);
	}

	return 0;
}
DEFINE_SHOW_ATTRIBUTE(debugfs_itct_cache_v3_hw);

static void debugfs_create_files_v3_hw(struct hisi_hba *hisi_hba)
{
	u64 *debugfs_timestamp;
	int dump_index = hisi_hba->debugfs_dump_index;
	struct dentry *dump_dentry;
	struct dentry *dentry;
	char name[256];
	int p;
	int c;
	int d;

	snprintf(name, 256, "%d", dump_index);

	dump_dentry = debugfs_create_dir(name, hisi_hba->debugfs_dump_dentry);

	debugfs_timestamp = &hisi_hba->debugfs_timestamp[dump_index];

	debugfs_create_u64("timestamp", 0400, dump_dentry,
			   debugfs_timestamp);

	debugfs_create_file("global", 0400, dump_dentry,
			    &hisi_hba->debugfs_regs[dump_index][DEBUGFS_GLOBAL],
			    &debugfs_global_v3_hw_fops);

	/* Create port dir and files */
	dentry = debugfs_create_dir("port", dump_dentry);
	for (p = 0; p < hisi_hba->n_phy; p++) {
		snprintf(name, 256, "%d", p);

		debugfs_create_file(name, 0400, dentry,
				    &hisi_hba->debugfs_port_reg[dump_index][p],
				    &debugfs_port_v3_hw_fops);
	}

	/* Create CQ dir and files */
	dentry = debugfs_create_dir("cq", dump_dentry);
	for (c = 0; c < hisi_hba->queue_count; c++) {
		snprintf(name, 256, "%d", c);

		debugfs_create_file(name, 0400, dentry,
				    &hisi_hba->debugfs_cq[dump_index][c],
				    &debugfs_cq_v3_hw_fops);
	}

	/* Create DQ dir and files */
	dentry = debugfs_create_dir("dq", dump_dentry);
	for (d = 0; d < hisi_hba->queue_count; d++) {
		snprintf(name, 256, "%d", d);

		debugfs_create_file(name, 0400, dentry,
				    &hisi_hba->debugfs_dq[dump_index][d],
				    &debugfs_dq_v3_hw_fops);
	}

	debugfs_create_file("iost", 0400, dump_dentry,
			    &hisi_hba->debugfs_iost[dump_index],
			    &debugfs_iost_v3_hw_fops);

	debugfs_create_file("iost_cache", 0400, dump_dentry,
			    &hisi_hba->debugfs_iost_cache[dump_index],
			    &debugfs_iost_cache_v3_hw_fops);

	debugfs_create_file("itct", 0400, dump_dentry,
			    &hisi_hba->debugfs_itct[dump_index],
			    &debugfs_itct_v3_hw_fops);

	debugfs_create_file("itct_cache", 0400, dump_dentry,
			    &hisi_hba->debugfs_itct_cache[dump_index],
			    &debugfs_itct_cache_v3_hw_fops);

	debugfs_create_file("axi", 0400, dump_dentry,
			    &hisi_hba->debugfs_regs[dump_index][DEBUGFS_AXI],
			    &debugfs_axi_v3_hw_fops);

	debugfs_create_file("ras", 0400, dump_dentry,
			    &hisi_hba->debugfs_regs[dump_index][DEBUGFS_RAS],
			    &debugfs_ras_v3_hw_fops);
}

static ssize_t debugfs_trigger_dump_v3_hw_write(struct file *file,
						const char __user *user_buf,
						size_t count, loff_t *ppos)
{
	struct hisi_hba *hisi_hba = file->f_inode->i_private;
	char buf[8];

	if (count > 8)
		return -EFAULT;

	if (copy_from_user(buf, user_buf, count))
		return -EFAULT;

	if (buf[0] != '1')
		return -EFAULT;

	down(&hisi_hba->sem);
	if (debugfs_snapshot_regs_v3_hw(hisi_hba)) {
		up(&hisi_hba->sem);
		return -EFAULT;
	}
	up(&hisi_hba->sem);

	return count;
}

static const struct file_operations debugfs_trigger_dump_v3_hw_fops = {
	.write = &debugfs_trigger_dump_v3_hw_write,
	.owner = THIS_MODULE,
};

enum {
	HISI_SAS_BIST_LOOPBACK_MODE_DIGITAL = 0,
	HISI_SAS_BIST_LOOPBACK_MODE_SERDES,
	HISI_SAS_BIST_LOOPBACK_MODE_REMOTE,
};

static const struct {
	int		value;
	char		*name;
} debugfs_loop_linkrate_v3_hw[] = {
	{ SAS_LINK_RATE_1_5_GBPS, "1.5 Gbit" },
	{ SAS_LINK_RATE_3_0_GBPS, "3.0 Gbit" },
	{ SAS_LINK_RATE_6_0_GBPS, "6.0 Gbit" },
	{ SAS_LINK_RATE_12_0_GBPS, "12.0 Gbit" },
};

static int debugfs_bist_linkrate_v3_hw_show(struct seq_file *s, void *p)
{
	struct hisi_hba *hisi_hba = s->private;
	int i;

	for (i = 0; i < ARRAY_SIZE(debugfs_loop_linkrate_v3_hw); i++) {
		int match = (hisi_hba->debugfs_bist_linkrate ==
			     debugfs_loop_linkrate_v3_hw[i].value);

		seq_printf(s, "%s%s%s ", match ? "[" : "",
			   debugfs_loop_linkrate_v3_hw[i].name,
			   match ? "]" : "");
	}
	seq_puts(s, "\n");

	return 0;
}

static ssize_t debugfs_bist_linkrate_v3_hw_write(struct file *filp,
						 const char __user *buf,
						 size_t count, loff_t *ppos)
{
	struct seq_file *m = filp->private_data;
	struct hisi_hba *hisi_hba = m->private;
	char kbuf[16] = {}, *pkbuf;
	bool found = false;
	int i;

	if (hisi_hba->debugfs_bist_enable)
		return -EPERM;

	if (count >= sizeof(kbuf))
		return -EOVERFLOW;

	if (copy_from_user(kbuf, buf, count))
		return -EINVAL;

	pkbuf = strstrip(kbuf);

	for (i = 0; i < ARRAY_SIZE(debugfs_loop_linkrate_v3_hw); i++) {
		if (!strncmp(debugfs_loop_linkrate_v3_hw[i].name,
			     pkbuf, 16)) {
			hisi_hba->debugfs_bist_linkrate =
				debugfs_loop_linkrate_v3_hw[i].value;
			found = true;
			break;
		}
	}

	if (!found)
		return -EINVAL;

	return count;
}
DEFINE_SHOW_STORE_ATTRIBUTE(debugfs_bist_linkrate_v3_hw);

static const struct {
	int		value;
	char		*name;
} debugfs_loop_code_mode_v3_hw[] = {
	{ HISI_SAS_BIST_CODE_MODE_PRBS7, "PRBS7" },
	{ HISI_SAS_BIST_CODE_MODE_PRBS23, "PRBS23" },
	{ HISI_SAS_BIST_CODE_MODE_PRBS31, "PRBS31" },
	{ HISI_SAS_BIST_CODE_MODE_JTPAT, "JTPAT" },
	{ HISI_SAS_BIST_CODE_MODE_CJTPAT, "CJTPAT" },
	{ HISI_SAS_BIST_CODE_MODE_SCRAMBED_0, "SCRAMBED_0" },
	{ HISI_SAS_BIST_CODE_MODE_TRAIN, "TRAIN" },
	{ HISI_SAS_BIST_CODE_MODE_TRAIN_DONE, "TRAIN_DONE" },
	{ HISI_SAS_BIST_CODE_MODE_HFTP, "HFTP" },
	{ HISI_SAS_BIST_CODE_MODE_MFTP, "MFTP" },
	{ HISI_SAS_BIST_CODE_MODE_LFTP, "LFTP" },
	{ HISI_SAS_BIST_CODE_MODE_FIXED_DATA, "FIXED_DATA" },
};

static int debugfs_bist_code_mode_v3_hw_show(struct seq_file *s, void *p)
{
	struct hisi_hba *hisi_hba = s->private;
	int i;

	for (i = 0; i < ARRAY_SIZE(debugfs_loop_code_mode_v3_hw); i++) {
		int match = (hisi_hba->debugfs_bist_code_mode ==
			     debugfs_loop_code_mode_v3_hw[i].value);

		seq_printf(s, "%s%s%s ", match ? "[" : "",
			   debugfs_loop_code_mode_v3_hw[i].name,
			   match ? "]" : "");
	}
	seq_puts(s, "\n");

	return 0;
}

static ssize_t debugfs_bist_code_mode_v3_hw_write(struct file *filp,
						  const char __user *buf,
						  size_t count,
						  loff_t *ppos)
{
	struct seq_file *m = filp->private_data;
	struct hisi_hba *hisi_hba = m->private;
	char kbuf[16] = {}, *pkbuf;
	bool found = false;
	int i;

	if (hisi_hba->debugfs_bist_enable)
		return -EPERM;

	if (count >= sizeof(kbuf))
		return -EINVAL;

	if (copy_from_user(kbuf, buf, count))
		return -EOVERFLOW;

	pkbuf = strstrip(kbuf);

	for (i = 0; i < ARRAY_SIZE(debugfs_loop_code_mode_v3_hw); i++) {
		if (!strncmp(debugfs_loop_code_mode_v3_hw[i].name,
			     pkbuf, 16)) {
			hisi_hba->debugfs_bist_code_mode =
				debugfs_loop_code_mode_v3_hw[i].value;
			found = true;
			break;
		}
	}

	if (!found)
		return -EINVAL;

	return count;
}
DEFINE_SHOW_STORE_ATTRIBUTE(debugfs_bist_code_mode_v3_hw);

static ssize_t debugfs_bist_phy_v3_hw_write(struct file *filp,
					    const char __user *buf,
					    size_t count, loff_t *ppos)
{
	struct seq_file *m = filp->private_data;
	struct hisi_hba *hisi_hba = m->private;
	unsigned int phy_no;
	int val;

	if (hisi_hba->debugfs_bist_enable)
		return -EPERM;

	val = kstrtouint_from_user(buf, count, 0, &phy_no);
	if (val)
		return val;

	if (phy_no >= hisi_hba->n_phy)
		return -EINVAL;

	hisi_hba->debugfs_bist_phy_no = phy_no;

	return count;
}

static int debugfs_bist_phy_v3_hw_show(struct seq_file *s, void *p)
{
	struct hisi_hba *hisi_hba = s->private;

	seq_printf(s, "%d\n", hisi_hba->debugfs_bist_phy_no);

	return 0;
}
DEFINE_SHOW_STORE_ATTRIBUTE(debugfs_bist_phy_v3_hw);

static ssize_t debugfs_bist_cnt_v3_hw_write(struct file *filp,
					const char __user *buf,
					size_t count, loff_t *ppos)
{
	struct seq_file *m = filp->private_data;
	struct hisi_hba *hisi_hba = m->private;
	unsigned int cnt;
	int val;

	if (hisi_hba->debugfs_bist_enable)
		return -EPERM;

	val = kstrtouint_from_user(buf, count, 0, &cnt);
	if (val)
		return val;

	if (cnt)
		return -EINVAL;

	hisi_hba->debugfs_bist_cnt = 0;
	return count;
}

static int debugfs_bist_cnt_v3_hw_show(struct seq_file *s, void *p)
{
	struct hisi_hba *hisi_hba = s->private;

	seq_printf(s, "%u\n", hisi_hba->debugfs_bist_cnt);

	return 0;
}
DEFINE_SHOW_STORE_ATTRIBUTE(debugfs_bist_cnt_v3_hw);

static const struct {
	int		value;
	char		*name;
} debugfs_loop_modes_v3_hw[] = {
	{ HISI_SAS_BIST_LOOPBACK_MODE_DIGITAL, "digital" },
	{ HISI_SAS_BIST_LOOPBACK_MODE_SERDES, "serdes" },
	{ HISI_SAS_BIST_LOOPBACK_MODE_REMOTE, "remote" },
};

static int debugfs_bist_mode_v3_hw_show(struct seq_file *s, void *p)
{
	struct hisi_hba *hisi_hba = s->private;
	int i;

	for (i = 0; i < ARRAY_SIZE(debugfs_loop_modes_v3_hw); i++) {
		int match = (hisi_hba->debugfs_bist_mode ==
			     debugfs_loop_modes_v3_hw[i].value);

		seq_printf(s, "%s%s%s ", match ? "[" : "",
			   debugfs_loop_modes_v3_hw[i].name,
			   match ? "]" : "");
	}
	seq_puts(s, "\n");

	return 0;
}

static ssize_t debugfs_bist_mode_v3_hw_write(struct file *filp,
					     const char __user *buf,
					     size_t count, loff_t *ppos)
{
	struct seq_file *m = filp->private_data;
	struct hisi_hba *hisi_hba = m->private;
	char kbuf[16] = {}, *pkbuf;
	bool found = false;
	int i;

	if (hisi_hba->debugfs_bist_enable)
		return -EPERM;

	if (count >= sizeof(kbuf))
		return -EINVAL;

	if (copy_from_user(kbuf, buf, count))
		return -EOVERFLOW;

	pkbuf = strstrip(kbuf);

	for (i = 0; i < ARRAY_SIZE(debugfs_loop_modes_v3_hw); i++) {
		if (!strncmp(debugfs_loop_modes_v3_hw[i].name, pkbuf, 16)) {
			hisi_hba->debugfs_bist_mode =
				debugfs_loop_modes_v3_hw[i].value;
			found = true;
			break;
		}
	}

	if (!found)
		return -EINVAL;

	return count;
}
DEFINE_SHOW_STORE_ATTRIBUTE(debugfs_bist_mode_v3_hw);

static ssize_t debugfs_bist_enable_v3_hw_write(struct file *filp,
					       const char __user *buf,
					       size_t count, loff_t *ppos)
{
	struct seq_file *m = filp->private_data;
	struct hisi_hba *hisi_hba = m->private;
	unsigned int enable;
	int val;

	val = kstrtouint_from_user(buf, count, 0, &enable);
	if (val)
		return val;

	if (enable > 1)
		return -EINVAL;

	if (enable == hisi_hba->debugfs_bist_enable)
		return count;

	val = debugfs_set_bist_v3_hw(hisi_hba, enable);
	if (val < 0)
		return val;

	hisi_hba->debugfs_bist_enable = enable;

	return count;
}

static int debugfs_bist_enable_v3_hw_show(struct seq_file *s, void *p)
{
	struct hisi_hba *hisi_hba = s->private;

	seq_printf(s, "%d\n", hisi_hba->debugfs_bist_enable);

	return 0;
}
DEFINE_SHOW_STORE_ATTRIBUTE(debugfs_bist_enable_v3_hw);

static const struct {
	char *name;
} debugfs_ffe_name_v3_hw[FFE_CFG_MAX] = {
	{ "SAS_1_5_GBPS" },
	{ "SAS_3_0_GBPS" },
	{ "SAS_6_0_GBPS" },
	{ "SAS_12_0_GBPS" },
	{ "FFE_RESV" },
	{ "SATA_1_5_GBPS" },
	{ "SATA_3_0_GBPS" },
	{ "SATA_6_0_GBPS" },
};

static ssize_t debugfs_v3_hw_write(struct file *filp,
				   const char __user *buf,
				   size_t count, loff_t *ppos)
{
	struct seq_file *m = filp->private_data;
	u32 *val = m->private;
	int res;

	res = kstrtouint_from_user(buf, count, 0, val);
	if (res)
		return res;

	return count;
}

static int debugfs_v3_hw_show(struct seq_file *s, void *p)
{
	u32 *val = s->private;

	seq_printf(s, "0x%x\n", *val);

	return 0;
}
DEFINE_SHOW_STORE_ATTRIBUTE(debugfs_v3_hw);

static ssize_t debugfs_phy_down_cnt_v3_hw_write(struct file *filp,
						const char __user *buf,
						size_t count, loff_t *ppos)
{
	struct seq_file *s = filp->private_data;
	struct hisi_sas_phy *phy = s->private;
	unsigned int set_val;
	int res;

	res = kstrtouint_from_user(buf, count, 0, &set_val);
	if (res)
		return res;

	if (set_val > 0)
		return -EINVAL;

	atomic_set(&phy->down_cnt, 0);

	return count;
}

static int debugfs_phy_down_cnt_v3_hw_show(struct seq_file *s, void *p)
{
	struct hisi_sas_phy *phy = s->private;

	seq_printf(s, "%d\n", atomic_read(&phy->down_cnt));

	return 0;
}
DEFINE_SHOW_STORE_ATTRIBUTE(debugfs_phy_down_cnt_v3_hw);

enum fifo_dump_mode_v3_hw {
	FIFO_DUMP_FORVER =		(1U << 0),
	FIFO_DUMP_AFTER_TRIGGER =	(1U << 1),
	FIFO_DUMP_UNTILL_TRIGGER =	(1U << 2),
};

enum fifo_trigger_mode_v3_hw {
	FIFO_TRIGGER_EDGE =		(1U << 0),
	FIFO_TRIGGER_SAME_LEVEL =	(1U << 1),
	FIFO_TRIGGER_DIFF_LEVEL =	(1U << 2),
};

static int debugfs_is_fifo_config_valid_v3_hw(struct hisi_sas_phy *phy)
{
	struct hisi_hba *hisi_hba = phy->hisi_hba;

	if (phy->fifo.signal_sel > 0xf) {
		dev_info(hisi_hba->dev, "Invalid signal select: %u\n",
			 phy->fifo.signal_sel);
		return -EINVAL;
	}

	switch (phy->fifo.dump_mode) {
	case FIFO_DUMP_FORVER:
	case FIFO_DUMP_AFTER_TRIGGER:
	case FIFO_DUMP_UNTILL_TRIGGER:
		break;
	default:
		dev_info(hisi_hba->dev, "Invalid dump mode: %u\n",
			 phy->fifo.dump_mode);
		return -EINVAL;
	}

	/* when FIFO_DUMP_FORVER, no need to check trigger_mode */
	if (phy->fifo.dump_mode == FIFO_DUMP_FORVER)
		return 0;

	switch (phy->fifo.trigger_mode) {
	case FIFO_TRIGGER_EDGE:
	case FIFO_TRIGGER_SAME_LEVEL:
	case FIFO_TRIGGER_DIFF_LEVEL:
		break;
	default:
		dev_info(hisi_hba->dev, "Invalid trigger mode: %u\n",
			 phy->fifo.trigger_mode);
		return -EINVAL;
	}
	return 0;
}

static int debugfs_update_fifo_config_v3_hw(struct hisi_sas_phy *phy)
{
	u32 trigger_mode = phy->fifo.trigger_mode;
	u32 signal_sel = phy->fifo.signal_sel;
	u32 dump_mode = phy->fifo.dump_mode;
	struct hisi_hba *hisi_hba = phy->hisi_hba;
	int phy_no = phy->sas_phy.id;
	u32 reg_val;
	int res;

	/* Check the validity of trace FIFO configuration */
	res = debugfs_is_fifo_config_valid_v3_hw(phy);
	if (res)
		return res;

	reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, DFX_FIFO_CTRL);
	/* Disable trace FIFO before update configuration */
	reg_val |= DFX_FIFO_CTRL_DUMP_DISABLE_MSK;

	/* Update trace FIFO configuration */
	reg_val &= ~(DFX_FIFO_CTRL_DUMP_MODE_MSK |
		     DFX_FIFO_CTRL_SIGNAL_SEL_MSK |
		     DFX_FIFO_CTRL_TRIGGER_MODE_MSK);

	reg_val |= ((trigger_mode << DFX_FIFO_CTRL_TRIGGER_MODE_OFF) |
		    (dump_mode << DFX_FIFO_CTRL_DUMP_MODE_OFF) |
		    (signal_sel << DFX_FIFO_CTRL_SIGNAL_SEL_OFF));
	hisi_sas_phy_write32(hisi_hba, phy_no, DFX_FIFO_CTRL, reg_val);

	hisi_sas_phy_write32(hisi_hba, phy_no, DFX_FIFO_DUMP_MSK,
			     phy->fifo.dump_msk);

	hisi_sas_phy_write32(hisi_hba, phy_no, DFX_FIFO_TRIGGER,
			     phy->fifo.trigger);

	hisi_sas_phy_write32(hisi_hba, phy_no, DFX_FIFO_TRIGGER_MSK,
			     phy->fifo.trigger_msk);

	/* Enable trace FIFO after updated configuration */
	reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, DFX_FIFO_CTRL);
	reg_val &= ~DFX_FIFO_CTRL_DUMP_DISABLE_MSK;
	hisi_sas_phy_write32(hisi_hba, phy_no, DFX_FIFO_CTRL, reg_val);

	return 0;
}

static ssize_t debugfs_fifo_update_cfg_v3_hw_write(struct file *filp,
						   const char __user *buf,
						   size_t count, loff_t *ppos)
{
	struct hisi_sas_phy *phy = filp->private_data;
	bool update;
	int val;

	val = kstrtobool_from_user(buf, count, &update);
	if (val)
		return val;

	if (update != 1)
		return -EINVAL;

	val = debugfs_update_fifo_config_v3_hw(phy);
	if (val)
		return val;

	return count;
}

static const struct file_operations debugfs_fifo_update_cfg_v3_hw_fops = {
	.open = simple_open,
	.write = debugfs_fifo_update_cfg_v3_hw_write,
	.owner = THIS_MODULE,
};

static void debugfs_read_fifo_data_v3_hw(struct hisi_sas_phy *phy)
{
	struct hisi_hba *hisi_hba = phy->hisi_hba;
	u32 *buf = phy->fifo.rd_data;
	int phy_no = phy->sas_phy.id;
	u32 val;
	int i;

	memset(buf, 0, sizeof(phy->fifo.rd_data));

	/* Disable trace FIFO before read data */
	val = hisi_sas_phy_read32(hisi_hba, phy_no, DFX_FIFO_CTRL);
	val |= DFX_FIFO_CTRL_DUMP_DISABLE_MSK;
	hisi_sas_phy_write32(hisi_hba, phy_no, DFX_FIFO_CTRL, val);

	for (i = 0; i < HISI_SAS_FIFO_DATA_DW_SIZE; i++) {
		val = hisi_sas_phy_read32(hisi_hba, phy_no,
					  DFX_FIFO_RD_DATA);
		buf[i] = val;
	}

	/* Enable trace FIFO after read data */
	val = hisi_sas_phy_read32(hisi_hba, phy_no, DFX_FIFO_CTRL);
	val &= ~DFX_FIFO_CTRL_DUMP_DISABLE_MSK;
	hisi_sas_phy_write32(hisi_hba, phy_no, DFX_FIFO_CTRL, val);
}

static int debugfs_fifo_data_v3_hw_show(struct seq_file *s, void *p)
{
	struct hisi_sas_phy *phy = s->private;

	debugfs_read_fifo_data_v3_hw(phy);

	debugfs_show_row_32_v3_hw(s, 0, HISI_SAS_FIFO_DATA_DW_SIZE * 4,
				  (__le32 *)phy->fifo.rd_data);

	return 0;
}
DEFINE_SHOW_ATTRIBUTE(debugfs_fifo_data_v3_hw);

static void debugfs_fifo_init_v3_hw(struct hisi_hba *hisi_hba)
{
	int phy_no;

	hisi_hba->debugfs_fifo_dentry =
			debugfs_create_dir("fifo", hisi_hba->debugfs_dir);

	for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) {
		struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
		struct dentry *port_dentry;
		char name[256];
		u32 val;

		/* get default configuration for trace FIFO */
		val = hisi_sas_phy_read32(hisi_hba, phy_no, DFX_FIFO_CTRL);
		val &= DFX_FIFO_CTRL_DUMP_MODE_MSK;
		val >>= DFX_FIFO_CTRL_DUMP_MODE_OFF;
		phy->fifo.dump_mode = val;

		val = hisi_sas_phy_read32(hisi_hba, phy_no, DFX_FIFO_CTRL);
		val &= DFX_FIFO_CTRL_TRIGGER_MODE_MSK;
		val >>= DFX_FIFO_CTRL_TRIGGER_MODE_OFF;
		phy->fifo.trigger_mode = val;

		val = hisi_sas_phy_read32(hisi_hba, phy_no, DFX_FIFO_CTRL);
		val &= DFX_FIFO_CTRL_SIGNAL_SEL_MSK;
		val >>= DFX_FIFO_CTRL_SIGNAL_SEL_OFF;
		phy->fifo.signal_sel = val;

		val = hisi_sas_phy_read32(hisi_hba, phy_no, DFX_FIFO_DUMP_MSK);
		phy->fifo.dump_msk = val;

		val = hisi_sas_phy_read32(hisi_hba, phy_no, DFX_FIFO_TRIGGER);
		phy->fifo.trigger = val;
		val = hisi_sas_phy_read32(hisi_hba, phy_no, DFX_FIFO_TRIGGER_MSK);
		phy->fifo.trigger_msk = val;

		snprintf(name, 256, "%d", phy_no);
		port_dentry = debugfs_create_dir(name,
						 hisi_hba->debugfs_fifo_dentry);

		debugfs_create_file("update_config", 0200, port_dentry, phy,
				    &debugfs_fifo_update_cfg_v3_hw_fops);

		debugfs_create_file("signal_sel", 0600, port_dentry,
				    &phy->fifo.signal_sel,
				    &debugfs_v3_hw_fops);

		debugfs_create_file("dump_msk", 0600, port_dentry,
				    &phy->fifo.dump_msk,
				    &debugfs_v3_hw_fops);

		debugfs_create_file("dump_mode", 0600, port_dentry,
				    &phy->fifo.dump_mode,
				    &debugfs_v3_hw_fops);

		debugfs_create_file("trigger_mode", 0600, port_dentry,
				    &phy->fifo.trigger_mode,
				    &debugfs_v3_hw_fops);

		debugfs_create_file("trigger", 0600, port_dentry,
				    &phy->fifo.trigger,
				    &debugfs_v3_hw_fops);

		debugfs_create_file("trigger_msk", 0600, port_dentry,
				    &phy->fifo.trigger_msk,
				    &debugfs_v3_hw_fops);

		debugfs_create_file("fifo_data", 0400, port_dentry, phy,
				    &debugfs_fifo_data_v3_hw_fops);
	}
}

static void debugfs_release_v3_hw(struct hisi_hba *hisi_hba, int dump_index)
{
	struct device *dev = hisi_hba->dev;
	int i;

	devm_kfree(dev, hisi_hba->debugfs_iost_cache[dump_index].cache);
	devm_kfree(dev, hisi_hba->debugfs_itct_cache[dump_index].cache);
	devm_kfree(dev, hisi_hba->debugfs_iost[dump_index].iost);
	devm_kfree(dev, hisi_hba->debugfs_itct[dump_index].itct);

	for (i = 0; i < hisi_hba->queue_count; i++)
		devm_kfree(dev, hisi_hba->debugfs_dq[dump_index][i].hdr);

	for (i = 0; i < hisi_hba->queue_count; i++)
		devm_kfree(dev,
			   hisi_hba->debugfs_cq[dump_index][i].complete_hdr);

	for (i = 0; i < DEBUGFS_REGS_NUM; i++)
		devm_kfree(dev, hisi_hba->debugfs_regs[dump_index][i].data);

	for (i = 0; i < hisi_hba->n_phy; i++)
		devm_kfree(dev, hisi_hba->debugfs_port_reg[dump_index][i].data);
}

static const struct hisi_sas_debugfs_reg *debugfs_reg_array_v3_hw[DEBUGFS_REGS_NUM] = {
	[DEBUGFS_GLOBAL] = &debugfs_global_reg,
	[DEBUGFS_AXI] = &debugfs_axi_reg,
	[DEBUGFS_RAS] = &debugfs_ras_reg,
};

static int debugfs_alloc_v3_hw(struct hisi_hba *hisi_hba, int dump_index)
{
	const struct hisi_sas_hw *hw = hisi_hba->hw;
	struct device *dev = hisi_hba->dev;
	int p, c, d, r;
	size_t sz;

	for (r = 0; r < DEBUGFS_REGS_NUM; r++) {
		struct hisi_sas_debugfs_regs *regs =
				&hisi_hba->debugfs_regs[dump_index][r];

		sz = debugfs_reg_array_v3_hw[r]->count * 4;
		regs->data = devm_kmalloc(dev, sz, GFP_KERNEL);
		if (!regs->data)
			goto fail;
		regs->hisi_hba = hisi_hba;
	}

	sz = debugfs_port_reg.count * 4;
	for (p = 0; p < hisi_hba->n_phy; p++) {
		struct hisi_sas_debugfs_port *port =
				&hisi_hba->debugfs_port_reg[dump_index][p];

		port->data = devm_kmalloc(dev, sz, GFP_KERNEL);
		if (!port->data)
			goto fail;
		port->phy = &hisi_hba->phy[p];
	}

	sz = hw->complete_hdr_size * HISI_SAS_QUEUE_SLOTS;
	for (c = 0; c < hisi_hba->queue_count; c++) {
		struct hisi_sas_debugfs_cq *cq =
				&hisi_hba->debugfs_cq[dump_index][c];

		cq->complete_hdr = devm_kmalloc(dev, sz, GFP_KERNEL);
		if (!cq->complete_hdr)
			goto fail;
		cq->cq = &hisi_hba->cq[c];
	}

	sz = sizeof(struct hisi_sas_cmd_hdr) * HISI_SAS_QUEUE_SLOTS;
	for (d = 0; d < hisi_hba->queue_count; d++) {
		struct hisi_sas_debugfs_dq *dq =
				&hisi_hba->debugfs_dq[dump_index][d];

		dq->hdr = devm_kmalloc(dev, sz, GFP_KERNEL);
		if (!dq->hdr)
			goto fail;
		dq->dq = &hisi_hba->dq[d];
	}

	sz = HISI_SAS_MAX_COMMANDS * sizeof(struct hisi_sas_iost);

	hisi_hba->debugfs_iost[dump_index].iost =
				devm_kmalloc(dev, sz, GFP_KERNEL);
	if (!hisi_hba->debugfs_iost[dump_index].iost)
		goto fail;

	sz = HISI_SAS_IOST_ITCT_CACHE_NUM *
	     sizeof(struct hisi_sas_iost_itct_cache);

	hisi_hba->debugfs_iost_cache[dump_index].cache =
				devm_kmalloc(dev, sz, GFP_KERNEL);
	if (!hisi_hba->debugfs_iost_cache[dump_index].cache)
		goto fail;

	sz = HISI_SAS_IOST_ITCT_CACHE_NUM *
	     sizeof(struct hisi_sas_iost_itct_cache);

	hisi_hba->debugfs_itct_cache[dump_index].cache =
				devm_kmalloc(dev, sz, GFP_KERNEL);
	if (!hisi_hba->debugfs_itct_cache[dump_index].cache)
		goto fail;

	/* New memory allocation must be locate before itct */
	sz = HISI_SAS_MAX_ITCT_ENTRIES * sizeof(struct hisi_sas_itct);

	hisi_hba->debugfs_itct[dump_index].itct =
				devm_kmalloc(dev, sz, GFP_KERNEL);
	if (!hisi_hba->debugfs_itct[dump_index].itct)
		goto fail;

	return 0;
fail:
	debugfs_release_v3_hw(hisi_hba, dump_index);
	return -ENOMEM;
}

static int debugfs_snapshot_regs_v3_hw(struct hisi_hba *hisi_hba)
{
	int debugfs_dump_index = hisi_hba->debugfs_dump_index;
	struct device *dev = hisi_hba->dev;
	u64 timestamp = local_clock();

	if (debugfs_dump_index >= hisi_sas_debugfs_dump_count) {
		dev_warn(dev, "dump count exceeded!\n");
		return -EINVAL;
	}

	if (debugfs_alloc_v3_hw(hisi_hba, debugfs_dump_index)) {
		dev_warn(dev, "failed to alloc memory\n");
		return -ENOMEM;
	}

	do_div(timestamp, NSEC_PER_MSEC);
	hisi_hba->debugfs_timestamp[debugfs_dump_index] = timestamp;

	debugfs_snapshot_prepare_v3_hw(hisi_hba);

	debugfs_snapshot_global_reg_v3_hw(hisi_hba);
	debugfs_snapshot_port_reg_v3_hw(hisi_hba);
	debugfs_snapshot_axi_reg_v3_hw(hisi_hba);
	debugfs_snapshot_ras_reg_v3_hw(hisi_hba);
	debugfs_snapshot_cq_reg_v3_hw(hisi_hba);
	debugfs_snapshot_dq_reg_v3_hw(hisi_hba);
	debugfs_snapshot_itct_reg_v3_hw(hisi_hba);
	debugfs_snapshot_iost_reg_v3_hw(hisi_hba);

	debugfs_create_files_v3_hw(hisi_hba);

	debugfs_snapshot_restore_v3_hw(hisi_hba);
	hisi_hba->debugfs_dump_index++;

	return 0;
}

static void debugfs_phy_down_cnt_init_v3_hw(struct hisi_hba *hisi_hba)
{
	struct dentry *dir = debugfs_create_dir("phy_down_cnt",
						hisi_hba->debugfs_dir);
	char name[16];
	int phy_no;

	for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) {
		snprintf(name, 16, "%d", phy_no);
		debugfs_create_file(name, 0600, dir,
				    &hisi_hba->phy[phy_no],
				    &debugfs_phy_down_cnt_v3_hw_fops);
	}
}

static void debugfs_bist_init_v3_hw(struct hisi_hba *hisi_hba)
{
	struct dentry *ports_dentry;
	int phy_no;

	hisi_hba->debugfs_bist_dentry =
			debugfs_create_dir("bist", hisi_hba->debugfs_dir);
	debugfs_create_file("link_rate", 0600,
			    hisi_hba->debugfs_bist_dentry, hisi_hba,
			    &debugfs_bist_linkrate_v3_hw_fops);

	debugfs_create_file("code_mode", 0600,
			    hisi_hba->debugfs_bist_dentry, hisi_hba,
			    &debugfs_bist_code_mode_v3_hw_fops);

	debugfs_create_file("fixed_code", 0600,
			    hisi_hba->debugfs_bist_dentry,
			    &hisi_hba->debugfs_bist_fixed_code[0],
			    &debugfs_v3_hw_fops);

	debugfs_create_file("fixed_code_1", 0600,
			    hisi_hba->debugfs_bist_dentry,
			    &hisi_hba->debugfs_bist_fixed_code[1],
			    &debugfs_v3_hw_fops);

	debugfs_create_file("phy_id", 0600, hisi_hba->debugfs_bist_dentry,
			    hisi_hba, &debugfs_bist_phy_v3_hw_fops);

	debugfs_create_file("cnt", 0600, hisi_hba->debugfs_bist_dentry,
			    hisi_hba, &debugfs_bist_cnt_v3_hw_fops);

	debugfs_create_file("loopback_mode", 0600,
			    hisi_hba->debugfs_bist_dentry,
			    hisi_hba, &debugfs_bist_mode_v3_hw_fops);

	debugfs_create_file("enable", 0600, hisi_hba->debugfs_bist_dentry,
			    hisi_hba, &debugfs_bist_enable_v3_hw_fops);

	ports_dentry = debugfs_create_dir("port", hisi_hba->debugfs_bist_dentry);

	for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) {
		struct dentry *port_dentry;
		struct dentry *ffe_dentry;
		char name[256];
		int i;

		snprintf(name, 256, "%d", phy_no);
		port_dentry = debugfs_create_dir(name, ports_dentry);
		ffe_dentry = debugfs_create_dir("ffe", port_dentry);
		for (i = 0; i < FFE_CFG_MAX; i++) {
			if (i == FFE_RESV)
				continue;
			debugfs_create_file(debugfs_ffe_name_v3_hw[i].name,
					    0600, ffe_dentry,
					    &hisi_hba->debugfs_bist_ffe[phy_no][i],
					    &debugfs_v3_hw_fops);
		}
	}

	hisi_hba->debugfs_bist_linkrate = SAS_LINK_RATE_1_5_GBPS;
}

static void debugfs_exit_v3_hw(struct hisi_hba *hisi_hba)
{
	debugfs_remove_recursive(hisi_hba->debugfs_dir);
	hisi_hba->debugfs_dir = NULL;
}

static void debugfs_init_v3_hw(struct hisi_hba *hisi_hba)
{
	struct device *dev = hisi_hba->dev;

	hisi_hba->debugfs_dir = debugfs_create_dir(dev_name(dev),
						   hisi_sas_debugfs_dir);
	debugfs_create_file("trigger_dump", 0200,
			    hisi_hba->debugfs_dir,
			    hisi_hba,
			    &debugfs_trigger_dump_v3_hw_fops);

	/* create bist structures */
	debugfs_bist_init_v3_hw(hisi_hba);

	hisi_hba->debugfs_dump_dentry =
			debugfs_create_dir("dump", hisi_hba->debugfs_dir);

	debugfs_phy_down_cnt_init_v3_hw(hisi_hba);
	debugfs_fifo_init_v3_hw(hisi_hba);
}

static int
hisi_sas_v3_probe(struct pci_dev *pdev, const struct pci_device_id *id)
{
	struct Scsi_Host *shost;
	struct hisi_hba *hisi_hba;
	struct device *dev = &pdev->dev;
	struct asd_sas_phy **arr_phy;
	struct asd_sas_port **arr_port;
	struct sas_ha_struct *sha;
	int rc, phy_nr, port_nr, i;

	rc = pcim_enable_device(pdev);
	if (rc)
		goto err_out;

	pci_set_master(pdev);

	rc = pcim_iomap_regions(pdev, 1 << BAR_NO_V3_HW, DRV_NAME);
	if (rc)
		goto err_out;

	rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
	if (rc) {
		dev_err(dev, "No usable DMA addressing method\n");
		rc = -ENODEV;
		goto err_out;
	}

	shost = hisi_sas_shost_alloc_pci(pdev);
	if (!shost) {
		rc = -ENOMEM;
		goto err_out;
	}

	sha = SHOST_TO_SAS_HA(shost);
	hisi_hba = shost_priv(shost);
	dev_set_drvdata(dev, sha);

	hisi_hba->regs = pcim_iomap_table(pdev)[BAR_NO_V3_HW];
	if (!hisi_hba->regs) {
		dev_err(dev, "cannot map register\n");
		rc = -ENOMEM;
		goto err_out_free_host;
	}

	phy_nr = port_nr = hisi_hba->n_phy;

	arr_phy = devm_kcalloc(dev, phy_nr, sizeof(void *), GFP_KERNEL);
	arr_port = devm_kcalloc(dev, port_nr, sizeof(void *), GFP_KERNEL);
	if (!arr_phy || !arr_port) {
		rc = -ENOMEM;
		goto err_out_free_host;
	}

	sha->sas_phy = arr_phy;
	sha->sas_port = arr_port;
	sha->shost = shost;
	sha->lldd_ha = hisi_hba;

	shost->transportt = hisi_sas_stt;
	shost->max_id = HISI_SAS_MAX_DEVICES;
	shost->max_lun = ~0;
	shost->max_channel = 1;
	shost->max_cmd_len = 16;
	shost->can_queue = HISI_SAS_UNRESERVED_IPTT;
	shost->cmd_per_lun = HISI_SAS_UNRESERVED_IPTT;
	if (hisi_hba->iopoll_q_cnt)
		shost->nr_maps = 3;
	else
		shost->nr_maps = 1;

	sha->sas_ha_name = DRV_NAME;
	sha->dev = dev;
	sha->sas_addr = &hisi_hba->sas_addr[0];
	sha->num_phys = hisi_hba->n_phy;

	for (i = 0; i < hisi_hba->n_phy; i++) {
		sha->sas_phy[i] = &hisi_hba->phy[i].sas_phy;
		sha->sas_port[i] = &hisi_hba->port[i].sas_port;
	}

	if (hisi_hba->prot_mask) {
		dev_info(dev, "Registering for DIF/DIX prot_mask=0x%x\n",
			 prot_mask);
		scsi_host_set_prot(hisi_hba->shost, prot_mask);
		if (hisi_hba->prot_mask & HISI_SAS_DIX_PROT_MASK)
			scsi_host_set_guard(hisi_hba->shost,
					    SHOST_DIX_GUARD_CRC);
	}

	if (hisi_sas_debugfs_enable)
		debugfs_init_v3_hw(hisi_hba);

	rc = interrupt_preinit_v3_hw(hisi_hba);
	if (rc)
		goto err_out_undo_debugfs;

	rc = scsi_add_host(shost, dev);
	if (rc)
		goto err_out_undo_debugfs;

	rc = sas_register_ha(sha);
	if (rc)
		goto err_out_remove_host;

	rc = hisi_sas_v3_init(hisi_hba);
	if (rc)
		goto err_out_unregister_ha;

	scsi_scan_host(shost);

	pm_runtime_set_autosuspend_delay(dev, 5000);
	pm_runtime_use_autosuspend(dev);
	/*
	 * For the situation that there are ATA disks connected with SAS
	 * controller, it additionally creates ata_port which will affect the
	 * child_count of hisi_hba->dev. Even if suspended all the disks,
	 * ata_port is still and the child_count of hisi_hba->dev is not 0.
	 * So use pm_suspend_ignore_children() to ignore the effect to
	 * hisi_hba->dev.
	 */
	pm_suspend_ignore_children(dev, true);
	pm_runtime_put_noidle(&pdev->dev);

	return 0;

err_out_unregister_ha:
	sas_unregister_ha(sha);
err_out_remove_host:
	scsi_remove_host(shost);
err_out_undo_debugfs:
	if (hisi_sas_debugfs_enable)
		debugfs_exit_v3_hw(hisi_hba);
err_out_free_host:
	hisi_sas_free(hisi_hba);
	scsi_host_put(shost);
err_out:
	return rc;
}

static void
hisi_sas_v3_destroy_irqs(struct pci_dev *pdev, struct hisi_hba *hisi_hba)
{
	int i;

	devm_free_irq(&pdev->dev, pci_irq_vector(pdev, 1), hisi_hba);
	devm_free_irq(&pdev->dev, pci_irq_vector(pdev, 2), hisi_hba);
	devm_free_irq(&pdev->dev, pci_irq_vector(pdev, 11), hisi_hba);
	for (i = 0; i < hisi_hba->cq_nvecs; i++) {
		struct hisi_sas_cq *cq = &hisi_hba->cq[i];
		int nr = hisi_sas_intr_conv ? 16 : 16 + i;

		devm_free_irq(&pdev->dev, pci_irq_vector(pdev, nr), cq);
	}
}

static void hisi_sas_v3_remove(struct pci_dev *pdev)
{
	struct device *dev = &pdev->dev;
	struct sas_ha_struct *sha = dev_get_drvdata(dev);
	struct hisi_hba *hisi_hba = sha->lldd_ha;
	struct Scsi_Host *shost = sha->shost;

	pm_runtime_get_noresume(dev);

	sas_unregister_ha(sha);
	flush_workqueue(hisi_hba->wq);
	sas_remove_host(shost);

	hisi_sas_v3_destroy_irqs(pdev, hisi_hba);
	hisi_sas_free(hisi_hba);
	if (hisi_sas_debugfs_enable)
		debugfs_exit_v3_hw(hisi_hba);

	scsi_host_put(shost);
}

static void hisi_sas_reset_prepare_v3_hw(struct pci_dev *pdev)
{
	struct sas_ha_struct *sha = pci_get_drvdata(pdev);
	struct hisi_hba *hisi_hba = sha->lldd_ha;
	struct device *dev = hisi_hba->dev;
	int rc;

	dev_info(dev, "FLR prepare\n");
	down(&hisi_hba->sem);
	set_bit(HISI_SAS_RESETTING_BIT, &hisi_hba->flags);
	hisi_sas_controller_reset_prepare(hisi_hba);

	interrupt_disable_v3_hw(hisi_hba);
	rc = disable_host_v3_hw(hisi_hba);
	if (rc)
		dev_err(dev, "FLR: disable host failed rc=%d\n", rc);
}

static void hisi_sas_reset_done_v3_hw(struct pci_dev *pdev)
{
	struct sas_ha_struct *sha = pci_get_drvdata(pdev);
	struct hisi_hba *hisi_hba = sha->lldd_ha;
	struct Scsi_Host *shost = hisi_hba->shost;
	struct device *dev = hisi_hba->dev;
	int rc;

	hisi_sas_init_mem(hisi_hba);

	rc = hw_init_v3_hw(hisi_hba);
	if (rc) {
		dev_err(dev, "FLR: hw init failed rc=%d\n", rc);
		clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);
		scsi_unblock_requests(shost);
		clear_bit(HISI_SAS_RESETTING_BIT, &hisi_hba->flags);
		up(&hisi_hba->sem);
		return;
	}

	hisi_sas_controller_reset_done(hisi_hba);
	dev_info(dev, "FLR done\n");
}

enum {
	/* instances of the controller */
	hip08,
};

static void enable_host_v3_hw(struct hisi_hba *hisi_hba)
{
	u32 reg_val;

	hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE,
			 (u32)((1ULL << hisi_hba->queue_count) - 1));

	phys_init_v3_hw(hisi_hba);
	reg_val = hisi_sas_read32(hisi_hba, AXI_MASTER_CFG_BASE +
				  AM_CTRL_GLOBAL);
	reg_val &= ~AM_CTRL_SHUTDOWN_REQ_MSK;
	hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE +
			 AM_CTRL_GLOBAL, reg_val);
}

static int _suspend_v3_hw(struct device *device)
{
	struct pci_dev *pdev = to_pci_dev(device);
	struct sas_ha_struct *sha = pci_get_drvdata(pdev);
	struct hisi_hba *hisi_hba = sha->lldd_ha;
	struct device *dev = hisi_hba->dev;
	struct Scsi_Host *shost = hisi_hba->shost;
	int rc;

	if (!pdev->pm_cap) {
		dev_err(dev, "PCI PM not supported\n");
		return -ENODEV;
	}

	if (test_and_set_bit(HISI_SAS_RESETTING_BIT, &hisi_hba->flags))
		return -EPERM;

	dev_warn(dev, "entering suspend state\n");

	scsi_block_requests(shost);
	set_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);
	flush_workqueue(hisi_hba->wq);
	interrupt_disable_v3_hw(hisi_hba);

#ifdef CONFIG_PM
	if (atomic_read(&device->power.usage_count)) {
		dev_err(dev, "PM suspend: host status cannot be suspended\n");
		rc = -EBUSY;
		goto err_out;
	}
#endif

	rc = disable_host_v3_hw(hisi_hba);
	if (rc) {
		dev_err(dev, "PM suspend: disable host failed rc=%d\n", rc);
		goto err_out_recover_host;
	}

	hisi_sas_init_mem(hisi_hba);

	hisi_sas_release_tasks(hisi_hba);

	sas_suspend_ha(sha);

	dev_warn(dev, "end of suspending controller\n");
	return 0;

err_out_recover_host:
	enable_host_v3_hw(hisi_hba);
#ifdef CONFIG_PM
err_out:
#endif
	interrupt_enable_v3_hw(hisi_hba);
	clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);
	clear_bit(HISI_SAS_RESETTING_BIT, &hisi_hba->flags);
	scsi_unblock_requests(shost);
	return rc;
}

static int _resume_v3_hw(struct device *device)
{
	struct pci_dev *pdev = to_pci_dev(device);
	struct sas_ha_struct *sha = pci_get_drvdata(pdev);
	struct hisi_hba *hisi_hba = sha->lldd_ha;
	struct Scsi_Host *shost = hisi_hba->shost;
	struct device *dev = hisi_hba->dev;
	unsigned int rc;
	pci_power_t device_state = pdev->current_state;

	dev_warn(dev, "resuming from operating state [D%d]\n",
		 device_state);

	scsi_unblock_requests(shost);
	clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);

	sas_prep_resume_ha(sha);
	rc = hw_init_v3_hw(hisi_hba);
	if (rc) {
		scsi_remove_host(shost);
		return rc;
	}
	phys_init_v3_hw(hisi_hba);

	/*
	 * If a directly-attached disk is removed during suspend, a deadlock
	 * may occur, as the PHYE_RESUME_TIMEOUT processing will require the
	 * hisi_hba->device to be active, which can only happen when resume
	 * completes. So don't wait for the HA event workqueue to drain upon
	 * resume.
	 */
	sas_resume_ha_no_sync(sha);
	clear_bit(HISI_SAS_RESETTING_BIT, &hisi_hba->flags);

	dev_warn(dev, "end of resuming controller\n");

	return 0;
}

static int __maybe_unused suspend_v3_hw(struct device *device)
{
	struct pci_dev *pdev = to_pci_dev(device);
	struct sas_ha_struct *sha = pci_get_drvdata(pdev);
	struct hisi_hba *hisi_hba = sha->lldd_ha;
	int rc;

	set_bit(HISI_SAS_PM_BIT, &hisi_hba->flags);

	rc = _suspend_v3_hw(device);
	if (rc)
		clear_bit(HISI_SAS_PM_BIT, &hisi_hba->flags);

	return rc;
}

static int __maybe_unused resume_v3_hw(struct device *device)
{
	struct pci_dev *pdev = to_pci_dev(device);
	struct sas_ha_struct *sha = pci_get_drvdata(pdev);
	struct hisi_hba *hisi_hba = sha->lldd_ha;
	int rc = _resume_v3_hw(device);

	clear_bit(HISI_SAS_PM_BIT, &hisi_hba->flags);

	return rc;
}

static const struct pci_device_id sas_v3_pci_table[] = {
	{ PCI_VDEVICE(HUAWEI, 0xa230), hip08 },
	{}
};
MODULE_DEVICE_TABLE(pci, sas_v3_pci_table);

static const struct pci_error_handlers hisi_sas_err_handler = {
	.reset_prepare	= hisi_sas_reset_prepare_v3_hw,
	.reset_done	= hisi_sas_reset_done_v3_hw,
};

static UNIVERSAL_DEV_PM_OPS(hisi_sas_v3_pm_ops,
			    suspend_v3_hw,
			    resume_v3_hw,
			    NULL);

static struct pci_driver sas_v3_pci_driver = {
	.name		= DRV_NAME,
	.id_table	= sas_v3_pci_table,
	.probe		= hisi_sas_v3_probe,
	.remove		= hisi_sas_v3_remove,
	.err_handler	= &hisi_sas_err_handler,
	.driver.pm	= &hisi_sas_v3_pm_ops,
};

module_pci_driver(sas_v3_pci_driver);
module_param_named(intr_conv, hisi_sas_intr_conv, bool, 0444);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("John Garry <john.garry@huawei.com>");
MODULE_DESCRIPTION("HISILICON SAS controller v3 hw driver based on pci device");
MODULE_ALIAS("pci:" DRV_NAME);