1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
|
[
{
"BriefDescription": "Count all other hardware assists or traps that are not necessarily architecturally exposed (through a software handler) beyond FP; SSE-AVX mix and A/D assists who are counted by dedicated sub-events.",
"Counter": "0,1,2,3,4,5,6,7,8,9",
"EventCode": "0xc1",
"EventName": "ASSISTS.HARDWARE",
"PublicDescription": "Count all other hardware assists or traps that are not necessarily architecturally exposed (through a software handler) beyond FP; SSE-AVX mix and A/D assists who are counted by dedicated sub-events. This includes, but not limited to, assists at EXE or MEM uop writeback like AVX* load/store/gather/scatter (non-FP GSSE-assist ) , assists generated by ROB like PEBS and RTIT, Uncore trap, RAR (Remote Action Request) and CET (Control flow Enforcement Technology) assists.",
"SampleAfterValue": "100003",
"UMask": "0x4",
"Unit": "cpu_core"
},
{
"BriefDescription": "ASSISTS.PAGE_FAULT",
"Counter": "0,1,2,3,4,5,6,7,8,9",
"EventCode": "0xc1",
"EventName": "ASSISTS.PAGE_FAULT",
"SampleAfterValue": "1000003",
"UMask": "0x8",
"Unit": "cpu_core"
},
{
"BriefDescription": "Counts cycles where the pipeline is stalled due to serializing operations.",
"Counter": "0,1,2,3,4,5,6,7,8,9",
"EventCode": "0xa2",
"EventName": "BE_STALLS.SCOREBOARD",
"SampleAfterValue": "100003",
"UMask": "0x2",
"Unit": "cpu_core"
},
{
"BriefDescription": "Counts the number of unhalted cycles a Core is blocked due to a lock In Progress issued by another core",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x63",
"EventName": "BUS_LOCK.BLOCKED_CYCLES",
"PublicDescription": "Counts the number of unhalted cycles a Core is blocked due to a lock In Progress issued by another core. Counts on a per core basis.",
"SampleAfterValue": "1000003",
"UMask": "0x1",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of unhalted cycles a Core is blocked due to an Accepted lock it issued, includes both split and non-split lock cycles.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x63",
"EventName": "BUS_LOCK.LOCK_CYCLES",
"PublicDescription": "Counts the number of unhalted cycles a Core is blocked due to an Accepted lock it issued, includes both split and non-split lock cycles. Counts on a per core basis.",
"SampleAfterValue": "1000003",
"UMask": "0x2",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of non-split locks such as UC locks issued by a Core (does not include cache locks)",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x63",
"EventName": "BUS_LOCK.NON_SPLIT_LOCKS",
"SampleAfterValue": "1000003",
"UMask": "0x4",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of split locks issued by a Core",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x63",
"EventName": "BUS_LOCK.SPLIT_LOCKS",
"SampleAfterValue": "1000003",
"UMask": "0x8",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Count number of times a load is depending on another load that had just write back its data or in previous or 2 cycles back. This event supports in-direct dependency through a single uop.",
"Counter": "0,1,2,3,4,5,6,7,8,9",
"EventCode": "0x02",
"EventName": "DEPENDENT_LOADS.ANY",
"SampleAfterValue": "1000003",
"UMask": "0x7",
"Unit": "cpu_core"
},
{
"BriefDescription": "Counts the number of cycles the L2 Prefetchers are at throttle level 0",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x32",
"EventName": "DYNAMIC_PREFETCH_THROTTLER.LEVEL0_SOC",
"SampleAfterValue": "1000003",
"UMask": "0x1",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of cycles the L2 Prefetcher throttle level is at 1",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x32",
"EventName": "DYNAMIC_PREFETCH_THROTTLER.LEVEL1_SOC",
"SampleAfterValue": "1000003",
"UMask": "0x2",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of cycles the L2 Prefetcher throttle level is at 2",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x32",
"EventName": "DYNAMIC_PREFETCH_THROTTLER.LEVEL2_SOC",
"SampleAfterValue": "1000003",
"UMask": "0x4",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of cycles the L2 Prefetcher throttle level is at 3",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x32",
"EventName": "DYNAMIC_PREFETCH_THROTTLER.LEVEL3_SOC",
"SampleAfterValue": "1000003",
"UMask": "0x8",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of cycles the L2 Prefetcher throttle level is at 4",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x32",
"EventName": "DYNAMIC_PREFETCH_THROTTLER.LEVEL4_SOC",
"SampleAfterValue": "1000003",
"UMask": "0x10",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of uops executed on all Integer ports.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xb3",
"EventName": "INT_UOPS_EXECUTED.ALL",
"SampleAfterValue": "1000003",
"UMask": "0xff",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of uops executed on a load port.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xb3",
"EventName": "INT_UOPS_EXECUTED.LD",
"PublicDescription": "Counts the number of uops executed on a load port. This event counts for integer uops even if the destination is FP/vector",
"SampleAfterValue": "1000003",
"UMask": "0x1",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of uops executed on integer port 0.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xb3",
"EventName": "INT_UOPS_EXECUTED.P0",
"SampleAfterValue": "1000003",
"UMask": "0x8",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of uops executed on integer port 1.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xb3",
"EventName": "INT_UOPS_EXECUTED.P1",
"SampleAfterValue": "1000003",
"UMask": "0x10",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of uops executed on integer port 2.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xb3",
"EventName": "INT_UOPS_EXECUTED.P2",
"SampleAfterValue": "1000003",
"UMask": "0x20",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of uops executed on integer port 3.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xb3",
"EventName": "INT_UOPS_EXECUTED.P3",
"SampleAfterValue": "1000003",
"UMask": "0x40",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of uops executed on integer port 0,1, 2, 3.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xb3",
"EventName": "INT_UOPS_EXECUTED.PRIMARY",
"SampleAfterValue": "1000003",
"UMask": "0x78",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of uops executed on a Store address port.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xb3",
"EventName": "INT_UOPS_EXECUTED.STA",
"PublicDescription": "Counts the number of uops executed on a Store address port. This event counts integer uops even if the data source is FP/vector",
"SampleAfterValue": "1000003",
"UMask": "0x2",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of uops executed on an integer store data and jump port.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xb3",
"EventName": "INT_UOPS_EXECUTED.STD_JMP",
"SampleAfterValue": "1000003",
"UMask": "0x4",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of LLC prefetches that were throttled due to Dynamic Prefetch Throttling. The throttle requestor/source could be from the uncore/SOC or the Dead Block Predictor. Counts on a per core basis.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x29",
"EventName": "LLC_PREFETCHES_THROTTLED.DPT",
"SampleAfterValue": "1000003",
"UMask": "0x1",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of LLC prefetches throttled due to Demand Throttle Prefetcher. DTP Global Triggered with no Local Override. Counts on a per core basis.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x29",
"EventName": "LLC_PREFETCHES_THROTTLED.DTP",
"SampleAfterValue": "1000003",
"UMask": "0x2",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of LLC prefetches not throttled by DTP due to local override. These prefetches may still be throttled due to another throttler mechanism. Counts on a per core basis.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x29",
"EventName": "LLC_PREFETCHES_THROTTLED.DTP_OVERRIDE",
"SampleAfterValue": "1000003",
"UMask": "0x4",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of LLC prefetches throttled due to LLC hit rate in <insert knob name here>. Counts on a per core basis.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x29",
"EventName": "LLC_PREFETCHES_THROTTLED.HIT_RATE",
"SampleAfterValue": "1000003",
"UMask": "0x10",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of LLC prefetches throttled due to exceeding the XQ threshold set by either XQ_THRESOLD_DTP or LLC_XQ_THRESHOLD. Counts on a per core basis.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x29",
"EventName": "LLC_PREFETCHES_THROTTLED.XQ_THRESH",
"SampleAfterValue": "1000003",
"UMask": "0x8",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts cycles where no execution is happening due to loads waiting for L1 cache (that is: no execution & load in flight & no load missed L1 cache)",
"Counter": "0,1,2,3,4,5,6,7,8,9",
"EventCode": "0x46",
"EventName": "MEMORY_STALLS.L1",
"SampleAfterValue": "1000003",
"UMask": "0x1",
"Unit": "cpu_core"
},
{
"BriefDescription": "Counts cycles where no execution is happening due to loads waiting for L2 cache (that is: no execution & load in flight & load missed L1 & no load missed L2 cache)",
"Counter": "0,1,2,3,4,5,6,7,8,9",
"EventCode": "0x46",
"EventName": "MEMORY_STALLS.L2",
"SampleAfterValue": "1000003",
"UMask": "0x2",
"Unit": "cpu_core"
},
{
"BriefDescription": "Counts cycles where no execution is happening due to loads waiting for L3 cache (that is: no execution & load in flight & load missed L1 & load missed L2 cache & no load missed L3 Cache)",
"Counter": "0,1,2,3,4,5,6,7,8,9",
"EventCode": "0x46",
"EventName": "MEMORY_STALLS.L3",
"SampleAfterValue": "1000003",
"UMask": "0x4",
"Unit": "cpu_core"
},
{
"BriefDescription": "Counts cycles where no execution is happening due to loads waiting for Memory (that is: no execution & load in flight & a load missed L3 cache)",
"Counter": "0,1,2,3,4,5,6,7,8,9",
"EventCode": "0x46",
"EventName": "MEMORY_STALLS.MEM",
"SampleAfterValue": "1000003",
"UMask": "0x8",
"Unit": "cpu_core"
},
{
"BriefDescription": "Counts all requests that have any type of response.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xB7",
"EventName": "OCR.ALL_REQUESTS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xFF0000001DFFF",
"SampleAfterValue": "100003",
"UMask": "0x1",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts writebacks of modified cachelines that have any type of response.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xB7",
"EventName": "OCR.COREWB_M.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10008",
"SampleAfterValue": "100003",
"UMask": "0x1",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts writebacks of non-modified cachelines that have any type of response.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xB7",
"EventName": "OCR.COREWB_NONM.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x11000",
"SampleAfterValue": "100003",
"UMask": "0x1",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that have any type of response.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xB7",
"EventName": "OCR.DEMAND_CODE_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10004",
"SampleAfterValue": "100003",
"UMask": "0x1",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xB7",
"EventName": "OCR.DEMAND_CODE_RD.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1FBC000004",
"SampleAfterValue": "100003",
"UMask": "0x1",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts demand data reads that have any type of response.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xB7",
"EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10001",
"SampleAfterValue": "100003",
"UMask": "0x1",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts demand data reads that have any type of response.",
"Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10001",
"SampleAfterValue": "100003",
"UMask": "0x1",
"Unit": "cpu_core"
},
{
"BriefDescription": "Counts demand data reads that were supplied by DRAM.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xB7",
"EventName": "OCR.DEMAND_DATA_RD.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1FBC000001",
"SampleAfterValue": "100003",
"UMask": "0x1",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts demand data reads that were supplied by DRAM.",
"Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_DATA_RD.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1E780000001",
"SampleAfterValue": "100003",
"UMask": "0x1",
"Unit": "cpu_core"
},
{
"BriefDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xB7",
"EventName": "OCR.DEMAND_RFO.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10002",
"SampleAfterValue": "100003",
"UMask": "0x1",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.",
"Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_RFO.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10002",
"SampleAfterValue": "100003",
"UMask": "0x1",
"Unit": "cpu_core"
},
{
"BriefDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xB7",
"EventName": "OCR.DEMAND_RFO.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1FBC000002",
"SampleAfterValue": "100003",
"UMask": "0x1",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts full streaming stores (64 bytes, WCiLF) that have any type of response.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xB7",
"EventName": "OCR.FULL_STREAMING_WR.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800000010000",
"SampleAfterValue": "100003",
"UMask": "0x1",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts partial streaming stores (less than 64 bytes, WCiL) that have any type of response.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xB7",
"EventName": "OCR.PARTIAL_STREAMING_WR.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400000010000",
"SampleAfterValue": "100003",
"UMask": "0x1",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts streaming stores that have any type of response.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xB7",
"EventName": "OCR.STREAMING_WR.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10800",
"SampleAfterValue": "100003",
"UMask": "0x1",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts streaming stores that have any type of response.",
"Counter": "0,1,2,3",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.STREAMING_WR.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10800",
"SampleAfterValue": "100003",
"UMask": "0x1",
"Unit": "cpu_core"
},
{
"BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread.",
"Counter": "0,1,2,3,4,5,6,7,8,9",
"EventCode": "0xa5",
"EventName": "RS.EMPTY",
"PublicDescription": "Counts cycles during which the reservation station (RS) is empty for this logical processor. This is usually caused when the front-end pipeline runs into starvation periods (e.g. branch mispredictions or i-cache misses)",
"SampleAfterValue": "1000003",
"UMask": "0x7",
"Unit": "cpu_core"
},
{
"BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty.",
"Counter": "0,1,2,3,4,5,6,7,8,9",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0xa5",
"EventName": "RS.EMPTY_COUNT",
"Invert": "1",
"PublicDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to closely sample on front-end latency issues (see the FRONTEND_RETIRED event of designated precise events)",
"SampleAfterValue": "100003",
"UMask": "0x7",
"Unit": "cpu_core"
},
{
"BriefDescription": "Cycles when RS was empty and a resource allocation stall is asserted",
"Counter": "0,1,2,3,4,5,6,7,8,9",
"EventCode": "0xa5",
"EventName": "RS.EMPTY_RESOURCE",
"SampleAfterValue": "1000003",
"UMask": "0x1",
"Unit": "cpu_core"
},
{
"BriefDescription": "Counts the number of issue slots in a UMWAIT or TPAUSE instruction where no uop issues due to the instruction putting the CPU into the C0.1 activity state.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x75",
"EventName": "SERIALIZATION.C01_MS_SCB",
"SampleAfterValue": "1000003",
"UMask": "0x4",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number issue slots not consumed due to a color request for an FCW or MXCSR control register when all 4 colors (copies) are already in use",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x75",
"EventName": "SERIALIZATION.COLOR_STALLS",
"SampleAfterValue": "1000003",
"UMask": "0x8",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Cycles the uncore cannot take further requests",
"Counter": "0,1,2,3,4,5,6,7,8,9",
"CounterMask": "1",
"EventCode": "0x2d",
"EventName": "XQ.FULL",
"PublicDescription": "number of cycles when the thread is active and the uncore cannot take any further requests (for example prefetches, loads or stores initiated by the Core that miss the L2 cache).",
"SampleAfterValue": "1000003",
"UMask": "0x1",
"Unit": "cpu_core"
},
{
"BriefDescription": "Counts the number of prefetch requests that were promoted in the XQ to a demand request.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xf4",
"EventName": "XQ_PROMOTION.ALL",
"SampleAfterValue": "1000003",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of prefetch requests that were promoted in the XQ to a demand code read.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xf4",
"EventName": "XQ_PROMOTION.CRDS",
"SampleAfterValue": "1000003",
"UMask": "0x4",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of prefetch requests that were promoted in the XQ to a demand read.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xf4",
"EventName": "XQ_PROMOTION.DRDS",
"SampleAfterValue": "1000003",
"UMask": "0x1",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of prefetch requests that were promoted in the XQ to a demand RFO.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xf4",
"EventName": "XQ_PROMOTION.RFOS",
"SampleAfterValue": "1000003",
"UMask": "0x2",
"Unit": "cpu_atom"
}
]
|
