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| author | Arnd Bergmann <arnd@arndb.de> | 2025-03-19 22:16:35 +0100 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2025-03-19 22:16:35 +0100 |
| commit | 2c5ef4e0b73a4bcca6192549358f7c68f5db91db (patch) | |
| tree | dce96092e3562965c1475092c412e755f1a60e92 | |
| parent | 519df17cb03eb2408c3053d6052548c92d19c9b7 (diff) | |
| parent | 8095a17b0ace09a280a5954096701b883dcaa135 (diff) | |
Merge tag 'hisi-arm64-dt-for-6.15' of https://github.com/hisilicon/linux-hisi into soc/dt
ARM64: DT: HiSilicon ARM64 DT updates for v6.15
- Add property to the ETM nodes for fixing CPU idle states
* tag 'hisi-arm64-dt-for-6.15' of https://github.com/hisilicon/linux-hisi:
arm64: dts: hi3660: Add property for fixing CPUIdle
Link: https://lore.kernel.org/r/67D968A9.7080504@hisilicon.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| -rw-r--r-- | arch/arm64/boot/dts/hisilicon/hi3660-coresight.dtsi | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-coresight.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660-coresight.dtsi index 79a55a0fa2f1..4c6a075908d1 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660-coresight.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660-coresight.dtsi @@ -17,6 +17,7 @@ clocks = <&crg_ctrl HI3660_PCLK>; clock-names = "apb_pclk"; cpu = <&cpu0>; + arm,coresight-loses-context-with-cpu; out-ports { port { @@ -34,6 +35,7 @@ clocks = <&crg_ctrl HI3660_PCLK>; clock-names = "apb_pclk"; cpu = <&cpu1>; + arm,coresight-loses-context-with-cpu; out-ports { port { @@ -51,6 +53,7 @@ clocks = <&crg_ctrl HI3660_PCLK>; clock-names = "apb_pclk"; cpu = <&cpu2>; + arm,coresight-loses-context-with-cpu; out-ports { port { @@ -68,6 +71,7 @@ clocks = <&crg_ctrl HI3660_PCLK>; clock-names = "apb_pclk"; cpu = <&cpu3>; + arm,coresight-loses-context-with-cpu; out-ports { port { @@ -160,6 +164,7 @@ clocks = <&crg_ctrl HI3660_PCLK>; clock-names = "apb_pclk"; cpu = <&cpu4>; + arm,coresight-loses-context-with-cpu; out-ports { port { @@ -177,6 +182,7 @@ clocks = <&crg_ctrl HI3660_PCLK>; clock-names = "apb_pclk"; cpu = <&cpu5>; + arm,coresight-loses-context-with-cpu; out-ports { port { @@ -194,6 +200,7 @@ clocks = <&crg_ctrl HI3660_PCLK>; clock-names = "apb_pclk"; cpu = <&cpu6>; + arm,coresight-loses-context-with-cpu; out-ports { port { @@ -211,6 +218,7 @@ clocks = <&crg_ctrl HI3660_PCLK>; clock-names = "apb_pclk"; cpu = <&cpu7>; + arm,coresight-loses-context-with-cpu; out-ports { port { |