diff options
| author | Andy Yan <andy.yan@rock-chips.com> | 2025-08-22 14:39:52 +0800 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2025-09-02 08:32:26 +0200 |
| commit | 64566e35757faded57a65d65e84b5ca95974ee19 (patch) | |
| tree | 4edb5373ed42d5c005f89cb81b599ebf781225b6 | |
| parent | 680826a5299bbb4cec839a04ac6032be719c4c05 (diff) | |
arm64: dts: rockchip: Add DP1 for rk3588
The DP1 is compliant with the DisplayPort Specification
Version 1.4, and share the USBDP combo PHY1 with USB 3.1
HOST1 controller.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Link: https://lore.kernel.org/r/20250822063959.692098-9-andyshrk@163.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| -rw-r--r-- | arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi index 90414486e466..6e5a58428bba 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi @@ -210,6 +210,36 @@ status = "disabled"; }; + dp1: dp@fde60000 { + compatible = "rockchip,rk3588-dp"; + reg = <0x0 0xfde60000 0x0 0x4000>; + interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH 0>; + assigned-clocks = <&cru CLK_AUX16M_1>; + assigned-clock-rates = <16000000>; + clocks = <&cru PCLK_DP1>, <&cru CLK_AUX16M_1>, + <&cru CLK_DP1>, <&cru MCLK_I2S8_8CH_TX>, + <&cru MCLK_SPDIF5_DP1>; + clock-names = "apb", "aux", "hdcp", "i2s", "spdif"; + phys = <&usbdp_phy1 PHY_TYPE_DP>; + power-domains = <&power RK3588_PD_VO0>; + resets = <&cru SRST_DP1>; + #sound-dai-cells = <0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + dp1_in: port@0 { + reg = <0>; + }; + + dp1_out: port@1 { + reg = <1>; + }; + }; + }; + hdmi1: hdmi@fdea0000 { compatible = "rockchip,rk3588-dw-hdmi-qp"; reg = <0x0 0xfdea0000 0x0 0x20000>; |