diff options
| author | Marek Vasut <marek.vasut@mailbox.org> | 2025-11-02 17:09:07 +0100 |
|---|---|---|
| committer | Liviu Dudau <liviu.dudau@arm.com> | 2025-11-03 14:25:22 +0000 |
| commit | 67934f248e64bdfb13f2a9091019a9d7d9b2980d (patch) | |
| tree | dbf77de8cd32e176a7c4019089faf217405d21c1 | |
| parent | 6918b7e8230f1331e1d7b89df7aa5888fdf217f5 (diff) | |
arm64: dts: imx95: Describe Mali G310 GPU
The instance of the GPU populated in i.MX95 is the G310, describe this
GPU in the DT. Include dummy GPU voltage regulator and OPP tables.
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
Link: https://patch.msgid.link/20251102160927.45157-2-marek.vasut@mailbox.org
Signed-off-by: Liviu Dudau <liviu.dudau@arm.com>
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx95.dtsi | 37 |
1 files changed, 37 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi index 1292677cbe4e..f94776a0e47b 100644 --- a/arch/arm64/boot/dts/freescale/imx95.dtsi +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi @@ -250,6 +250,28 @@ clock-output-names = "dummy"; }; + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-hz-real = /bits/ 64 <500000000>; + opp-microvolt = <920000>; + }; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-hz-real = /bits/ 64 <800000000>; + opp-microvolt = <920000>; + }; + + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-hz-real = /bits/ 64 <1000000000>; + opp-microvolt = <920000>; + }; + }; + clk_ext1: clock-ext1 { compatible = "fixed-clock"; #clock-cells = <0>; @@ -2138,6 +2160,21 @@ }; }; + gpu: gpu@4d900000 { + compatible = "nxp,imx95-mali", "arm,mali-valhall-csf"; + reg = <0 0x4d900000 0 0x480000>; + clocks = <&scmi_clk IMX95_CLK_GPU>, <&scmi_clk IMX95_CLK_GPUAPB>; + clock-names = "core", "coregroup"; + interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "job", "mmu", "gpu"; + operating-points-v2 = <&gpu_opp_table>; + power-domains = <&scmi_devpd IMX95_PD_GPU>; + #cooling-cells = <2>; + dynamic-power-coefficient = <1013>; + }; + ddr-pmu@4e090dc0 { compatible = "fsl,imx95-ddr-pmu", "fsl,imx93-ddr-pmu"; reg = <0x0 0x4e090dc0 0x0 0x200>; |