diff options
| author | E Shattow <e@freeshell.de> | 2025-08-23 03:01:42 -0700 |
|---|---|---|
| committer | Conor Dooley <conor.dooley@microchip.com> | 2025-09-04 18:57:30 +0100 |
| commit | 7114969021ec5c4c0f3df1da3a8790f75dda92e2 (patch) | |
| tree | 10ce4eddc395a7b8c395a1c5d833b4f9721e2cf3 | |
| parent | f5e36ecc9e4a2a4bcd942ad1e9947e018ffd15b5 (diff) | |
riscv: dts: starfive: jh7110: add DMC memory controller
Add JH7110 SoC DDR external memory controller.
Signed-off-by: E Shattow <e@freeshell.de>
Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
| -rw-r--r-- | arch/riscv/boot/dts/starfive/jh7110.dtsi | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index 0ba74ef04679..f3876660c07f 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -931,6 +931,18 @@ <&syscrg JH7110_SYSRST_WDT_CORE>; }; + memory-controller@15700000 { + compatible = "starfive,jh7110-dmc"; + reg = <0x0 0x15700000 0x0 0x10000>, + <0x0 0x13000000 0x0 0x10000>; + clocks = <&syscrg JH7110_PLLCLK_PLL1_OUT>; + clock-names = "pll"; + resets = <&syscrg JH7110_SYSRST_DDR_AXI>, + <&syscrg JH7110_SYSRST_DDR_OSC>, + <&syscrg JH7110_SYSRST_DDR_APB>; + reset-names = "axi", "osc", "apb"; + }; + crypto: crypto@16000000 { compatible = "starfive,jh7110-crypto"; reg = <0x0 0x16000000 0x0 0x4000>; |