diff options
| author | Junhui Liu <junhui.liu@pigmoral.tech> | 2025-10-21 17:41:43 +0800 |
|---|---|---|
| committer | Conor Dooley <conor.dooley@microchip.com> | 2025-11-12 17:06:56 +0000 |
| commit | a94f9be29464f85e97683901162ca236dde40dc7 (patch) | |
| tree | bd9bc9192026e746697de4745cb1aeb0c65d3cce | |
| parent | ccc3fd3ebeef2686f005733858c0a1b2cb89aaeb (diff) | |
dt-bindings: serial: snps-dw-apb-uart: Add Anlogic DR1V90 uart
The Anlogic DR1V90 SoC integrates a UART controller compatible with
snps,dw-apb-uart, operating at a 50 MHz clock.
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
| -rw-r--r-- | Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml index cb9da6c97afc..691bd0bac6be 100644 --- a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml +++ b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml @@ -51,6 +51,7 @@ properties: - const: renesas,rzn1-uart - items: - enum: + - anlogic,dr1v90-uart - brcm,bcm11351-dw-apb-uart - brcm,bcm21664-dw-apb-uart - rockchip,px30-uart |