diff options
| author | Andreas Schwab <schwab@suse.de> | 2025-07-10 15:32:18 +0200 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@dabbelt.com> | 2025-07-16 09:05:39 -0700 |
| commit | b3510183ab7d63c71a3f5c89043d31686a76a34c (patch) | |
| tree | 26513e5da93b95dc56de065eb73d0f4752f88684 | |
| parent | 969f028bf2c40573ef18061f702ede3ebfe12b42 (diff) | |
riscv: traps_misaligned: properly sign extend value in misaligned load handler
Add missing cast to signed long.
Signed-off-by: Andreas Schwab <schwab@suse.de>
Fixes: 956d705dd279 ("riscv: Unaligned load/store handling for M_MODE")
Tested-by: Clément Léger <cleger@rivosinc.com>
Link: https://lore.kernel.org/r/mvmikk0goil.fsf@suse.de
Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com>
| -rw-r--r-- | arch/riscv/kernel/traps_misaligned.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c index 93043924fe6c..f760e4fcc052 100644 --- a/arch/riscv/kernel/traps_misaligned.c +++ b/arch/riscv/kernel/traps_misaligned.c @@ -461,7 +461,7 @@ static int handle_scalar_misaligned_load(struct pt_regs *regs) } if (!fp) - SET_RD(insn, regs, val.data_ulong << shift >> shift); + SET_RD(insn, regs, (long)(val.data_ulong << shift) >> shift); else if (len == 8) set_f64_rd(insn, regs, val.data_u64); else |