diff options
| author | Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> | 2025-08-12 21:03:32 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2025-08-19 11:38:08 +0200 |
| commit | be5d60d94b982d46a734750d93624bd85a1c7089 (patch) | |
| tree | 9a2735af5fb4ea860b7bebb2e3c8093ededa3fda | |
| parent | 6fb1e70e7a918969573bc5258975456bb7165cc0 (diff) | |
arm64: dts: renesas: r9a09g077: Add DT nodes for SCI channels 1-5
The RZ/T2H SoC exposes six SCI controllers; sci0 was already present in
the SoC DTSI. Add the remaining SCI nodes (sci1-sci5).
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250812200344.3253781-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| -rw-r--r-- | arch/arm64/boot/dts/renesas/r9a09g077.dtsi | 70 |
1 files changed, 70 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi index b16fd9259d8d..8ee88b8e8f33 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi @@ -90,6 +90,76 @@ status = "disabled"; }; + sci1: serial@80005400 { + compatible = "renesas,r9a09g077-rsci"; + reg = <0 0x80005400 0 0x400>; + interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 595 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 596 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", "tei"; + clocks = <&cpg CPG_MOD 9>, <&cpg CPG_CORE R9A09G077_CLK_PCLKM>; + clock-names = "operation", "bus"; + power-domains = <&cpg>; + status = "disabled"; + }; + + sci2: serial@80005800 { + compatible = "renesas,r9a09g077-rsci"; + reg = <0 0x80005800 0 0x400>; + interrupts = <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 599 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 600 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", "tei"; + clocks = <&cpg CPG_MOD 10>, <&cpg CPG_CORE R9A09G077_CLK_PCLKM>; + clock-names = "operation", "bus"; + power-domains = <&cpg>; + status = "disabled"; + }; + + sci3: serial@80005c00 { + compatible = "renesas,r9a09g077-rsci"; + reg = <0 0x80005c00 0 0x400>; + interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 603 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 604 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", "tei"; + clocks = <&cpg CPG_MOD 11>, <&cpg CPG_CORE R9A09G077_CLK_PCLKM>; + clock-names = "operation", "bus"; + power-domains = <&cpg>; + status = "disabled"; + }; + + sci4: serial@80006000 { + compatible = "renesas,r9a09g077-rsci"; + reg = <0 0x80006000 0 0x400>; + interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 607 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 608 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 609 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", "tei"; + clocks = <&cpg CPG_MOD 12>, <&cpg CPG_CORE R9A09G077_CLK_PCLKM>; + clock-names = "operation", "bus"; + power-domains = <&cpg>; + status = "disabled"; + }; + + sci5: serial@81005000 { + compatible = "renesas,r9a09g077-rsci"; + reg = <0 0x81005000 0 0x400>; + interrupts = <GIC_SPI 610 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 611 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 612 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 613 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", "tei"; + clocks = <&cpg CPG_MOD 600>, <&cpg CPG_CORE R9A09G077_CLK_PCLKM>; + clock-names = "operation", "bus"; + power-domains = <&cpg>; + status = "disabled"; + }; + i2c0: i2c@80088000 { compatible = "renesas,riic-r9a09g077"; reg = <0 0x80088000 0 0x400>; |