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authorPierre-Henry Moussay <pierre-henry.moussay@microchip.com>2025-11-17 14:24:37 +0000
committerConor Dooley <conor.dooley@microchip.com>2025-11-17 23:44:12 +0000
commitd52341da4db0cd993d3549aa20cbdf063b412c3b (patch)
treeb9211751e1f58aa56aab91172ea61c2a25272242
parent941327ca5ddd45cfc4dd960cbbabed9e2b5cb1b0 (diff)
dt-bindings: cache: sifive,ccache0: add a pic64gx compatible
The pic64gx use the same IP than mpfs, therefore add compatibility with mpfs as fallback. Signed-off-by: Pierre-Henry Moussay <pierre-henry.moussay@microchip.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
-rw-r--r--Documentation/devicetree/bindings/cache/sifive,ccache0.yaml5
1 files changed, 5 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml b/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml
index 579bacb66f34..c0e5ebb1fa4c 100644
--- a/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml
+++ b/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml
@@ -48,6 +48,11 @@ properties:
- const: microchip,mpfs-ccache
- const: sifive,fu540-c000-ccache
- const: cache
+ - items:
+ - const: microchip,pic64gx-ccache
+ - const: microchip,mpfs-ccache
+ - const: sifive,fu540-c000-ccache
+ - const: cache
cache-block-size:
const: 64