diff options
| author | Nicolas Frattaroli <nicolas.frattaroli@collabora.com> | 2025-08-25 10:28:29 +0200 |
|---|---|---|
| committer | Yury Norov <yury.norov@gmail.com> | 2025-09-02 20:06:47 -0400 |
| commit | d6de45fd7f1c8ef9f03fd16a97959e42271c3f78 (patch) | |
| tree | b1264a4c8cce55b77c39032381a118904c745e9e | |
| parent | 9040ecd0bf9ba0045736525027e30bdf56705b01 (diff) | |
phy: rockchip-samsung-dcphy: switch to FIELD_PREP_WM16 macro
The era of hand-rolled HIWORD_UPDATE macros is over, at least for those
drivers that use constant masks.
phy-rockchip-samsung-dcphy is actually an exemplary example, where the
similarities to FIELD_PREP were spotted and the driver local macro has
the same semantics as the new FIELD_PREP_WM16 hw_bitfield.h macro.
Still, get rid of FIELD_PREP_HIWORD now that a shared implementation
exists, replacing the two instances of it with FIELD_PREP_WM16. This
gives us slightly better error checking; the value is now checked to fit
in 16 bits.
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Yury Norov (NVIDIA) <yury.norov@gmail.com>
| -rw-r--r-- | drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c | 11 |
1 files changed, 3 insertions, 8 deletions
diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c b/drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c index 28a052e17366..4508a3147272 100644 --- a/drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c +++ b/drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c @@ -8,6 +8,7 @@ #include <dt-bindings/phy/phy.h> #include <linux/bitfield.h> #include <linux/clk.h> +#include <linux/hw_bitfield.h> #include <linux/init.h> #include <linux/kernel.h> #include <linux/mfd/syscon.h> @@ -20,12 +21,6 @@ #include <linux/regmap.h> #include <linux/reset.h> -#define FIELD_PREP_HIWORD(_mask, _val) \ - ( \ - FIELD_PREP((_mask), (_val)) | \ - ((_mask) << 16) \ - ) - #define BIAS_CON0 0x0000 #define I_RES_CNTL_MASK GENMASK(6, 4) #define I_RES_CNTL(x) FIELD_PREP(I_RES_CNTL_MASK, x) @@ -252,8 +247,8 @@ /* MIPI_CDPHY_GRF registers */ #define MIPI_DCPHY_GRF_CON0 0x0000 -#define S_CPHY_MODE FIELD_PREP_HIWORD(BIT(3), 1) -#define M_CPHY_MODE FIELD_PREP_HIWORD(BIT(0), 1) +#define S_CPHY_MODE FIELD_PREP_WM16(BIT(3), 1) +#define M_CPHY_MODE FIELD_PREP_WM16(BIT(0), 1) enum hs_drv_res_ohm { STRENGTH_30_OHM = 0x8, |