diff options
| author | AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> | 2025-02-12 11:00:12 +0100 |
|---|---|---|
| committer | AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> | 2025-03-06 11:54:20 +0100 |
| commit | dfe4382b304a2108ce20090135123046cab00452 (patch) | |
| tree | 67c077b304cae8fd1c8d9647ec80842e33df6a51 | |
| parent | aa0f05dcf330154c233fb1c17a716cfbd7e2a9e4 (diff) | |
soc: mediatek: mt8188-mmsys: Add support for DSC on VDO0
Add routing paths to support Display Stream Compression on the
VDOSYS0 pipelines ending with DSI or DisplayPort (DP_INTF).
Link: https://lore.kernel.org/r/20250212100012.33001-9-angelogioacchino.delregno@collabora.com
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
| -rw-r--r-- | drivers/soc/mediatek/mt8188-mmsys.h | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/drivers/soc/mediatek/mt8188-mmsys.h b/drivers/soc/mediatek/mt8188-mmsys.h index befd293e86c3..99080afead7e 100644 --- a/drivers/soc/mediatek/mt8188-mmsys.h +++ b/drivers/soc/mediatek/mt8188-mmsys.h @@ -226,15 +226,24 @@ static const struct mtk_mmsys_routes mmsys_mt8188_routing_table[] = { MMSYS_ROUTE(DSC0, MERGE0, MT8188_VDO0_VPP_MERGE_SEL, MT8188_SEL_IN_VPP_MERGE_FROM_MASK, MT8188_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT), + MMSYS_ROUTE(MERGE0, DP_INTF0, + MT8188_VDO0_DP_INTF0_SEL_IN, MT8188_SEL_IN_DP_INTF0_FROM_MASK, + MT8188_SEL_IN_DP_INTF0_FROM_VPP_MERGE), MMSYS_ROUTE(DSC0, DSI0, MT8188_VDO0_DSI0_SEL_IN, MT8188_SEL_IN_DSI0_FROM_MASK, MT8188_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT), MMSYS_ROUTE(RDMA0, COLOR0, MT8188_VDO0_DISP_RDMA_SEL, GENMASK(1, 0), MT8188_SOUT_DISP_RDMA0_TO_DISP_COLOR0), + MMSYS_ROUTE(DITHER0, DSC0, + MT8188_VDO0_DISP_DITHER0_SEL_OUT, MT8188_SOUT_DISP_DITHER0_TO_MASK, + MT8188_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN), MMSYS_ROUTE(DITHER0, DSI0, MT8188_VDO0_DISP_DITHER0_SEL_OUT, MT8188_SOUT_DISP_DITHER0_TO_MASK, MT8188_SOUT_DISP_DITHER0_TO_DSI0), + MMSYS_ROUTE(DITHER0, MERGE0, + MT8188_VDO0_DISP_DITHER0_SEL_OUT, MT8188_SOUT_DISP_DITHER0_TO_MASK, + MT8188_SOUT_DISP_DITHER0_TO_VPP_MERGE0), MMSYS_ROUTE(DITHER0, DP_INTF0, MT8188_VDO0_DISP_DITHER0_SEL_OUT, MT8188_SOUT_DISP_DITHER0_TO_MASK, MT8188_SOUT_DISP_DITHER0_TO_DP_INTF0), |