diff options
| author | Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> | 2025-02-23 13:55:59 +0200 |
|---|---|---|
| committer | Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> | 2025-03-01 15:08:05 +0100 |
| commit | f33807c30664d2b134ba17f2ae0740acbe91986a (patch) | |
| tree | 0e5c2e82ab31e20b27346e8d3f8a64744745208b | |
| parent | d434e7851caf9352e014f6f527a32ff61b014cd7 (diff) | |
clk: samsung: clk-pll: add support for pll_4311
pll4311 (also known in the vendor kernel as frd_4311_rpll) is a PLL used
in the Exynos2200 SoC. It's an integer/fractional PLL with mid frequency
FVCO (650 to 3500Mhz).
The PLL is functionally similar enough to pll531x, so the same code can
handle both.
Locktime for pll4311 is 500 - the same as the pll531x lock factor. MDIV,
PDIV, SDIV and FDIV masks and bit shifts are also the same as pll531x.
When defining a PLL, the "con" parameter should be set to CON3
register, like this:
PLL(pll_4311, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0, NULL),
Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
Link: https://lore.kernel.org/r/20250223115601.723886-3-ivo.ivanov.ivanov1@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
| -rw-r--r-- | drivers/clk/samsung/clk-pll.c | 1 | ||||
| -rw-r--r-- | drivers/clk/samsung/clk-pll.h | 1 |
2 files changed, 2 insertions, 0 deletions
diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c index 2e94bba6c396..d2b5b525c560 100644 --- a/drivers/clk/samsung/clk-pll.c +++ b/drivers/clk/samsung/clk-pll.c @@ -1460,6 +1460,7 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, init.ops = &samsung_pll2650xx_clk_ops; break; case pll_531x: + case pll_4311: init.ops = &samsung_pll531x_clk_ops; break; default: diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h index 6ddc54d173a0..e9a5f8e0e0a3 100644 --- a/drivers/clk/samsung/clk-pll.h +++ b/drivers/clk/samsung/clk-pll.h @@ -48,6 +48,7 @@ enum samsung_pll_type { pll_0717x, pll_0718x, pll_0732x, + pll_4311, }; #define PLL_RATE(_fin, _m, _p, _s, _k, _ks) \ |