summaryrefslogtreecommitdiff
path: root/drivers/pinctrl/sunplus
diff options
context:
space:
mode:
authorLinus Torvalds <torvalds@linux-foundation.org>2025-08-02 12:07:09 -0700
committerLinus Torvalds <torvalds@linux-foundation.org>2025-08-02 12:07:09 -0700
commit186f3edfdd41f2ae87fc40a9ccba52a3bf930994 (patch)
treea429b2877cbd9651e3e4926f62bc53bbed36ac63 /drivers/pinctrl/sunplus
parenteacf91b0c78a7113844830ed65ebf543eb9052c5 (diff)
parenta3fe1324c3c5c292ec79bd756497c1c44ff247d2 (diff)
Merge tag 'pinctrl-v6.17-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrlHEADmaster
Pull pin control updates from Linus Walleij: "Nothing stands out, apart from maybe the interesting Eswin EIC7700, a RISC-V SoC I've never seen before. Core changes: - Open code PINCTRL_FUNCTION_DESC() instead of defining a complex macro only used in one place - Add pinmux_generic_add_pinfunction() helper and use this in a few drivers New drivers: - Amlogic S7, S7D and S6 pin control support - Eswin EIC7700 pin control support - Qualcomm PMIV0104, PM7550 and Milos pin control support Because of unhelpful numbering schemes, the Qualcomm driver now needs to start to rely on SoC codenames - STM32 HDP pin control support - Mediatek MT8189 pin control support Improvements: - Switch remaining pin control drivers over to the new GPIO set callback that provides a return value - Support RSVD (reserved) pins in the STM32 driver - Move many fixed assignments over to pinctrl_desc definitions - Handle multiple TLMM regions in the Qualcomm driver" * tag 'pinctrl-v6.17-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (105 commits) pinctrl: mediatek: Add pinctrl driver for mt8189 dt-bindings: pinctrl: mediatek: Add support for mt8189 pinctrl: aspeed-g6: Add PCIe RC PERST pin group pinctrl: ingenic: use pinmux_generic_add_pinfunction() pinctrl: keembay: use pinmux_generic_add_pinfunction() pinctrl: mediatek: moore: use pinmux_generic_add_pinfunction() pinctrl: airoha: use pinmux_generic_add_pinfunction() pinctrl: equilibrium: use pinmux_generic_add_pinfunction() pinctrl: provide pinmux_generic_add_pinfunction() pinctrl: pinmux: open-code PINCTRL_FUNCTION_DESC() pinctrl: ma35: use new GPIO line value setter callbacks MAINTAINERS: add Clément Le Goffic as STM32 HDP maintainer pinctrl: stm32: Introduce HDP driver dt-bindings: pinctrl: stm32: Introduce HDP pinctrl: qcom: Add Milos pinctrl driver dt-bindings: pinctrl: document the Milos Top Level Mode Multiplexer pinctrl: qcom: spmi: Add PM7550 dt-bindings: pinctrl: qcom,pmic-gpio: Add PM7550 support pinctrl: qcom: spmi: Add PMIV0104 dt-bindings: pinctrl: qcom,pmic-gpio: Add PMIV0104 support ...
Diffstat (limited to 'drivers/pinctrl/sunplus')
-rw-r--r--drivers/pinctrl/sunplus/sppctl.c6
1 files changed, 4 insertions, 2 deletions
diff --git a/drivers/pinctrl/sunplus/sppctl.c b/drivers/pinctrl/sunplus/sppctl.c
index ae156f779a16..3c3357f80889 100644
--- a/drivers/pinctrl/sunplus/sppctl.c
+++ b/drivers/pinctrl/sunplus/sppctl.c
@@ -461,13 +461,15 @@ static int sppctl_gpio_get(struct gpio_chip *chip, unsigned int offset)
return (reg & BIT(bit_off)) ? 1 : 0;
}
-static void sppctl_gpio_set(struct gpio_chip *chip, unsigned int offset, int val)
+static int sppctl_gpio_set(struct gpio_chip *chip, unsigned int offset, int val)
{
struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip);
u32 reg_off, reg;
reg = sppctl_prep_moon_reg_and_offset(offset, &reg_off, val);
sppctl_gpio_out_writel(spp_gchip, reg, reg_off);
+
+ return 0;
}
static int sppctl_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
@@ -545,7 +547,7 @@ static int sppctl_gpio_new(struct platform_device *pdev, struct sppctl_pdata *pc
gchip->direction_input = sppctl_gpio_direction_input;
gchip->direction_output = sppctl_gpio_direction_output;
gchip->get = sppctl_gpio_get;
- gchip->set = sppctl_gpio_set;
+ gchip->set_rv = sppctl_gpio_set;
gchip->set_config = sppctl_gpio_set_config;
gchip->dbg_show = IS_ENABLED(CONFIG_DEBUG_FS) ?
sppctl_gpio_dbg_show : NULL;