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authorMikko Perttunen <mperttunen@nvidia.com>2022-06-27 17:19:48 +0300
committerThierry Reding <treding@nvidia.com>2022-07-08 16:27:52 +0200
commit8aa5bcb61612060429223d1fbb7a1c30a579fc1f (patch)
tree2e09643084d8c033217ebc5c397a35ea450aefd7 /include/linux/host1x.h
parenta72d4b182f4e092573035fe6fa9402a14111fd64 (diff)
gpu: host1x: Add context device management code
Add code to register context devices from device tree, allocate them out and manage their refcounts. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'include/linux/host1x.h')
-rw-r--r--include/linux/host1x.h34
1 files changed, 34 insertions, 0 deletions
diff --git a/include/linux/host1x.h b/include/linux/host1x.h
index c0bf4e581fe9..32a82da13fed 100644
--- a/include/linux/host1x.h
+++ b/include/linux/host1x.h
@@ -446,4 +446,38 @@ int tegra_mipi_disable(struct tegra_mipi_device *device);
int tegra_mipi_start_calibration(struct tegra_mipi_device *device);
int tegra_mipi_finish_calibration(struct tegra_mipi_device *device);
+/* host1x memory contexts */
+
+struct host1x_memory_context {
+ struct host1x *host;
+
+ refcount_t ref;
+ struct pid *owner;
+
+ struct device dev;
+ u64 dma_mask;
+ u32 stream_id;
+};
+
+#ifdef CONFIG_IOMMU_API
+struct host1x_memory_context *host1x_memory_context_alloc(struct host1x *host1x,
+ struct pid *pid);
+void host1x_memory_context_get(struct host1x_memory_context *cd);
+void host1x_memory_context_put(struct host1x_memory_context *cd);
+#else
+static inline struct host1x_memory_context *host1x_memory_context_alloc(struct host1x *host1x,
+ struct pid *pid)
+{
+ return NULL;
+}
+
+static inline void host1x_memory_context_get(struct host1x_memory_context *cd)
+{
+}
+
+static inline void host1x_memory_context_put(struct host1x_memory_context *cd)
+{
+}
+#endif
+
#endif