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authorGeert Uytterhoeven <geert+renesas@glider.be>2020-10-28 15:51:17 +0100
committerLinus Walleij <linus.walleij@linaro.org>2020-11-05 14:56:50 +0100
commita4da45dda6475816f4c8b9e0d512261991ba31e5 (patch)
tree9261f8651e10998d3e822212961568e5cf7f24d4 /include/linux/pinctrl
parentb507cb92477ad85902783a183c5ce01d16296687 (diff)
pinctrl: Remove hole in pinctrl_gpio_range
On 64-bit platforms, pointer size and alignment are 64-bit, hence two 4-byte holes are present before the pins and gc members of the pinctrl_gpio_range structure. Get rid of these holes by moving the pins pointer. This reduces kernel size of an arm64 Rockchip kernel by ca. 512 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20201028145117.1731876-1-geert+renesas@glider.be Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'include/linux/pinctrl')
-rw-r--r--include/linux/pinctrl/pinctrl.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/include/linux/pinctrl/pinctrl.h b/include/linux/pinctrl/pinctrl.h
index 2aef59df93d7..70b45d28e7a9 100644
--- a/include/linux/pinctrl/pinctrl.h
+++ b/include/linux/pinctrl/pinctrl.h
@@ -51,8 +51,8 @@ struct pinctrl_pin_desc {
* @id: an ID number for the chip in this range
* @base: base offset of the GPIO range
* @pin_base: base pin number of the GPIO range if pins == NULL
- * @pins: enumeration of pins in GPIO range or NULL
* @npins: number of pins in the GPIO range, including the base number
+ * @pins: enumeration of pins in GPIO range or NULL
* @gc: an optional pointer to a gpio_chip
*/
struct pinctrl_gpio_range {
@@ -61,8 +61,8 @@ struct pinctrl_gpio_range {
unsigned int id;
unsigned int base;
unsigned int pin_base;
- unsigned const *pins;
unsigned int npins;
+ unsigned const *pins;
struct gpio_chip *gc;
};