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| author | Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com> | 2025-11-05 12:41:38 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2025-11-13 21:18:25 +0100 |
| commit | 5fb2f67341bd4b7c482f2bbda6b78244a51c3923 (patch) | |
| tree | e91d40eb0cca14162d8a6c77b0c6862f71879edf /tools/docs/parse-headers.py | |
| parent | 7efa3a6d96348bfbe02e330219b05ec922958fab (diff) | |
clk: renesas: r9a09g077: Add SPI module clocks
The Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs have four SPI
peripherals, each with their own clock divider, which divides PLL4 by
either 24, 25, 30 or 32, similar to the SCI peripheral.
The dividers feed into the usual module clocks.
Add them all.
Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251105104151.1489281-2-cosmin-gabriel.tanislav.xa@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/docs/parse-headers.py')
0 files changed, 0 insertions, 0 deletions