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| author | Luca Weiss <luca.weiss@fairphone.com> | 2025-10-21 20:08:54 +0200 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2025-10-22 16:59:49 -0500 |
| commit | ab0e13141d679fdffdd3463a272c5c1b10be1794 (patch) | |
| tree | 90651003fb22afaefa44ac62aee8c8f5ab2aabb8 /tools/docs/parse-headers.py | |
| parent | fd0b632efbbdf427678a7a880abeb828bc4633fe (diff) | |
clk: qcom: camcc-sm6350: Fix PLL config of PLL2
The 'Agera' PLLs (with clk_agera_pll_configure) do not take some of the
parameters that are provided in the vendor driver. Instead the upstream
configuration should provide the final user_ctl value that is written to
the USER_CTL register.
Fix the config so that the PLL is configured correctly, and fixes
CAMCC_MCLK* being stuck off.
Fixes: 80f5451d9a7c ("clk: qcom: Add camera clock controller driver for SM6350")
Suggested-by: Taniya Das <taniya.das@oss.qualcomm.com>
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Taniya Das <taniya.das@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20251021-agera-pll-fixups-v1-1-8c1d8aff4afc@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Diffstat (limited to 'tools/docs/parse-headers.py')
0 files changed, 0 insertions, 0 deletions