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authorMichael Walle <mwalle@kernel.org>2025-10-17 12:22:22 +0200
committerVignesh Raghavendra <vigneshr@ti.com>2025-10-30 19:13:25 +0530
commita3a74f9b15f020952a4c9e4eb3a0b44241827b73 (patch)
tree834f6ee00dd41a39b2d0b627d84ca16d823f7248 /tools/lib/python/kdoc/python_version.py
parentb2f45bdc185f687fbbfef838eb49320ad07602b4 (diff)
arm64: dts: ti: k3-j722s-main: fix the audio refclk source
At the moment the clock parent of the audio extclk output is PLL1_HSDIV6 of the main domain. This very clock output is also used among various IP cores, for example for the USB1 LPM clock. The audio extclock being an external clock output with a variable frequency, it is likely that a user of this clock will try to set it's frequency to a different value, i.e. an audio codec. Because that clock output is used also for other IP cores, bad things will happen. Instead of using PLL1_HSDIV6 use the PLL2_HSDIV8 as a sane default, as this output is exclusively used among other audio peripherals. Signed-off-by: Michael Walle <mwalle@kernel.org> Link: https://patch.msgid.link/20251017102228.530517-2-mwalle@kernel.org Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Diffstat (limited to 'tools/lib/python/kdoc/python_version.py')
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