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| author | Terry Bowman <terry.bowman@amd.com> | 2022-02-09 11:27:15 -0600 |
|---|---|---|
| committer | Wolfram Sang <wsa@kernel.org> | 2022-02-11 15:38:22 +0100 |
| commit | 46967bc1ee93acd1d8953c87dc16f43de4076f93 (patch) | |
| tree | edcba793a3cf017824f9622b0226117da45612bd /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | 7c148722d074c29fb998578eea5de3c14b9608c9 (diff) | |
i2c: piix4: Add EFCH MMIO support to SMBus base address detect
The EFCH SMBus controller's base address is determined using details in
FCH::PM::DECODEEN[smbusasfiobase] and FCH::PM::DECODEEN[smbusasfioen].These
register fields were accessed using cd6h/cd7h port I/O. cd6h/cd7h port I/O
is no longer available in later AMD processors. Change base address
detection to use MMIO instead of port I/O cd6h/cd7h.
Signed-off-by: Terry Bowman <terry.bowman@amd.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Reviewed-by: Jean Delvare <jdelvare@suse.de>
Signed-off-by: Wolfram Sang <wsa@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions