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| author | Anup Patel <apatel@ventanamicro.com> | 2025-06-18 17:05:24 +0530 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2025-07-28 22:27:13 +0530 |
| commit | 7584eb611e8ef22aca3b801f7fd8529892b70901 (patch) | |
| tree | e9e65f006cc2529186d17de01b85a7147611f3e0 /tools/perf/scripts/python/mem-phys-addr.py | |
| parent | b79bf2025dbc53e0cf834690fc90f11cf801657b (diff) | |
RISC-V: KVM: Replace KVM_REQ_HFENCE_GVMA_VMID_ALL with KVM_REQ_TLB_FLUSH
The KVM_REQ_HFENCE_GVMA_VMID_ALL is same as KVM_REQ_TLB_FLUSH so
to avoid confusion let's replace KVM_REQ_HFENCE_GVMA_VMID_ALL with
KVM_REQ_TLB_FLUSH. Also, rename kvm_riscv_hfence_gvma_vmid_all_process()
to kvm_riscv_tlb_flush_process().
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Tested-by: Atish Patra <atishp@rivosinc.com>
Reviewed-by: Nutty Liu <liujingqi@lanxincomputing.com>
Link: https://lore.kernel.org/r/20250618113532.471448-5-apatel@ventanamicro.com
Signed-off-by: Anup Patel <anup@brainfault.org>
Diffstat (limited to 'tools/perf/scripts/python/mem-phys-addr.py')
0 files changed, 0 insertions, 0 deletions