diff options
| author | Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> | 2025-06-04 00:23:38 +0530 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2025-06-19 12:25:50 +0200 |
| commit | 1f25307c90dcadde6fa9d6f1faf23731f6931fd5 (patch) | |
| tree | 7a1a08c7d07bf675b583138ea997920ae87a0c9a /tools/perf/scripts/python/stackcollapse.py | |
| parent | 70627bf82e36e61c40c3315e1206e4ea4c02e668 (diff) | |
usb: dwc3: xilinx: set coherency mode for AMD versal adaptive platform
If device is coherent or if DMA (direct memory access) is translated by
an IOMMU then program USB2.0 IP to route transactions through the CCI for
coherency even if the target of transaction is in low power domain (LPD).
Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
Acked-by: Thinh Nguyen <Thinh.Nguyen@synopsys.com>
Link: https://lore.kernel.org/r/1748976818-710088-1-git-send-email-radhey.shyam.pandey@amd.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions