diff options
| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2025-06-12 17:50:13 +0300 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2025-06-17 19:12:03 +0300 |
| commit | ed9434c6b4f3d9aa89c9ba6853849b9751a2b1f3 (patch) | |
| tree | 375a7b3894f0f85f8502655c8d206837f14b7cea /tools/perf/util/scripting-engines/trace-event-python.c | |
| parent | 762ccc195bfe399199f9da89aade8177826451a4 (diff) | |
drm/i915/dsb: Use intel_dsb_ins_align() in intel_dsb_align_tail()
If the free_post is not QW aligned we don't have to memset the
extra DW needed to make it so, as the only way that can happen
is via intel_dsb_reg_write_indexed() which already makes sure
the next DW is zeroed.
Not a big deal, but this is more consistent how all the other
stuff operates that puts instructions into the DSB buffer, and
we'll get a few more of those soon.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250612145018.8735-2-ville.syrjala@linux.intel.com
Diffstat (limited to 'tools/perf/util/scripting-engines/trace-event-python.c')
0 files changed, 0 insertions, 0 deletions