diff options
| -rw-r--r-- | drivers/iio/adc/ad7124.c | 26 |
1 files changed, 20 insertions, 6 deletions
diff --git a/drivers/iio/adc/ad7124.c b/drivers/iio/adc/ad7124.c index d5bb0faf9111..6f4629c4a2f0 100644 --- a/drivers/iio/adc/ad7124.c +++ b/drivers/iio/adc/ad7124.c @@ -93,10 +93,11 @@ #define AD7124_CONFIG_PGA GENMASK(2, 0) /* AD7124_FILTER_X */ -#define AD7124_FILTER_FS GENMASK(10, 0) #define AD7124_FILTER_FILTER GENMASK(23, 21) #define AD7124_FILTER_FILTER_SINC4 0 #define AD7124_FILTER_FILTER_SINC3 2 +#define AD7124_FILTER_SINGLE_CYCLE BIT(16) +#define AD7124_FILTER_FS GENMASK(10, 0) #define AD7124_MAX_CONFIGS 8 #define AD7124_MAX_CHANNELS 16 @@ -285,18 +286,20 @@ static u32 ad7124_get_fclk_hz(struct ad7124_state *st) static void ad7124_set_channel_odr(struct ad7124_state *st, unsigned int channel, unsigned int odr) { - unsigned int fclk, odr_sel_bits; + unsigned int fclk, factor, odr_sel_bits; fclk = ad7124_get_fclk_hz(st); /* - * FS[10:0] = fCLK / (fADC x 32) where: + * FS[10:0] = fCLK / (fADC x 32 * N) where: * fADC is the output data rate * fCLK is the master clock frequency + * N is number of conversions per sample (depends on filter type) * FS[10:0] are the bits in the filter register * FS[10:0] can have a value from 1 to 2047 */ - odr_sel_bits = DIV_ROUND_CLOSEST(fclk, odr * 32); + factor = 32 * 4; /* N = 4 for default sinc4 filter. */ + odr_sel_bits = DIV_ROUND_CLOSEST(fclk, odr * factor); if (odr_sel_bits < 1) odr_sel_bits = 1; else if (odr_sel_bits > 2047) @@ -306,7 +309,8 @@ static void ad7124_set_channel_odr(struct ad7124_state *st, unsigned int channel st->channels[channel].cfg.live = false; /* fADC = fCLK / (FS[10:0] x 32) */ - st->channels[channel].cfg.odr = DIV_ROUND_CLOSEST(fclk, odr_sel_bits * 32); + st->channels[channel].cfg.odr = DIV_ROUND_CLOSEST(fclk, odr_sel_bits * + factor); st->channels[channel].cfg.odr_sel_bits = odr_sel_bits; } @@ -439,10 +443,20 @@ static int ad7124_write_config(struct ad7124_state *st, struct ad7124_channel_co if (ret < 0) return ret; + /* + * NB: AD7124_FILTER_SINGLE_CYCLE is always set so that we get the same + * sampling frequency even when only one channel is enabled in a + * buffered read. If it was not set, the N in ad7124_set_channel_odr() + * would be 1 and we would get a faster sampling frequency than what + * was requested. + */ tmp = FIELD_PREP(AD7124_FILTER_FILTER, cfg->filter_type) | + AD7124_FILTER_SINGLE_CYCLE | FIELD_PREP(AD7124_FILTER_FS, cfg->odr_sel_bits); return ad7124_spi_write_mask(st, AD7124_FILTER(cfg->cfg_slot), - AD7124_FILTER_FILTER | AD7124_FILTER_FS, + AD7124_FILTER_FILTER | + AD7124_FILTER_SINGLE_CYCLE | + AD7124_FILTER_FS, tmp, 3); } |