diff options
| -rw-r--r-- | arch/mips/boot/dts/mobileye/eyeq5.dtsi | 75 |
1 files changed, 75 insertions, 0 deletions
diff --git a/arch/mips/boot/dts/mobileye/eyeq5.dtsi b/arch/mips/boot/dts/mobileye/eyeq5.dtsi index e15d9ce0bdf4..a838e33a2a05 100644 --- a/arch/mips/boot/dts/mobileye/eyeq5.dtsi +++ b/arch/mips/boot/dts/mobileye/eyeq5.dtsi @@ -110,6 +110,81 @@ ranges; compatible = "simple-bus"; + i2c0: i2c@300000 { + compatible = "mobileye,eyeq5-i2c", "arm,primecell"; + reg = <0 0x300000 0x0 0x1000>; + interrupt-parent = <&gic>; + interrupts = <GIC_SHARED 1 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <400000>; /* Fast mode */ + #address-cells = <1>; + #size-cells = <0>; + clocks = <&olb 35>, <&olb EQ5C_PER_I2C>; + clock-names = "i2cclk", "apb_pclk"; + resets = <&olb 0 13>; + i2c-transfer-timeout-us = <10000>; + mobileye,olb = <&olb 0>; + }; + + i2c1: i2c@400000 { + compatible = "mobileye,eyeq5-i2c", "arm,primecell"; + reg = <0 0x400000 0x0 0x1000>; + interrupt-parent = <&gic>; + interrupts = <GIC_SHARED 2 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <400000>; /* Fast mode */ + #address-cells = <1>; + #size-cells = <0>; + clocks = <&olb 35>, <&olb EQ5C_PER_I2C>; + clock-names = "i2cclk", "apb_pclk"; + resets = <&olb 0 14>; + i2c-transfer-timeout-us = <10000>; + mobileye,olb = <&olb 1>; + }; + + i2c2: i2c@500000 { + compatible = "mobileye,eyeq5-i2c", "arm,primecell"; + reg = <0 0x500000 0x0 0x1000>; + interrupt-parent = <&gic>; + interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <400000>; /* Fast mode */ + #address-cells = <1>; + #size-cells = <0>; + clocks = <&olb 35>, <&olb EQ5C_PER_I2C>; + clock-names = "i2cclk", "apb_pclk"; + resets = <&olb 0 15>; + i2c-transfer-timeout-us = <10000>; + mobileye,olb = <&olb 2>; + }; + + i2c3: i2c@600000 { + compatible = "mobileye,eyeq5-i2c", "arm,primecell"; + reg = <0 0x600000 0x0 0x1000>; + interrupt-parent = <&gic>; + interrupts = <GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <400000>; /* Fast mode */ + #address-cells = <1>; + #size-cells = <0>; + clocks = <&olb 35>, <&olb EQ5C_PER_I2C>; + clock-names = "i2cclk", "apb_pclk"; + resets = <&olb 0 16>; + i2c-transfer-timeout-us = <10000>; + mobileye,olb = <&olb 3>; + }; + + i2c4: i2c@700000 { + compatible = "mobileye,eyeq5-i2c", "arm,primecell"; + reg = <0 0x700000 0x0 0x1000>; + interrupt-parent = <&gic>; + interrupts = <GIC_SHARED 5 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <400000>; /* Fast mode */ + #address-cells = <1>; + #size-cells = <0>; + clocks = <&olb 35>, <&olb EQ5C_PER_I2C>; + clock-names = "i2cclk", "apb_pclk"; + resets = <&olb 0 17>; + i2c-transfer-timeout-us = <10000>; + mobileye,olb = <&olb 4>; + }; + uart0: serial@800000 { compatible = "arm,pl011", "arm,primecell"; reg = <0 0x800000 0x0 0x1000>; |