diff options
Diffstat (limited to 'arch/arm/boot/dts/st')
31 files changed, 1829 insertions, 62 deletions
diff --git a/arch/arm/boot/dts/st/Makefile b/arch/arm/boot/dts/st/Makefile index 60d55516f723..66d4f96da5dd 100644 --- a/arch/arm/boot/dts/st/Makefile +++ b/arch/arm/boot/dts/st/Makefile @@ -28,6 +28,7 @@ dtb-$(CONFIG_ARCH_STM32) += \ stm32746g-eval.dtb \ stm32h743i-eval.dtb \ stm32h743i-disco.dtb \ + stm32h747i-disco.dtb \ stm32h750i-art-pi.dtb \ stm32mp133c-prihmb.dtb \ stm32mp135f-dhcor-dhsbc.dtb \ @@ -70,7 +71,9 @@ dtb-$(CONFIG_ARCH_STM32) += \ stm32mp157c-lxa-tac-gen2.dtb \ stm32mp157c-odyssey.dtb \ stm32mp157c-osd32mp1-red.dtb \ - stm32mp157c-phycore-stm32mp1-3.dtb + stm32mp157c-phycore-stm32mp1-3.dtb \ + stm32mp157c-ultra-fly-sbc.dtb \ + stm32mp157f-dk2.dtb dtb-$(CONFIG_ARCH_U8500) += \ ste-snowball.dtb \ ste-hrefprev60-stuib.dtb \ diff --git a/arch/arm/boot/dts/st/spear1310-evb.dts b/arch/arm/boot/dts/st/spear1310-evb.dts index ad216571ba57..417a064db11e 100644 --- a/arch/arm/boot/dts/st/spear1310-evb.dts +++ b/arch/arm/boot/dts/st/spear1310-evb.dts @@ -159,7 +159,7 @@ }; }; - gmac0: eth@e2000000 { + gmac0: ethernet@e2000000 { phy-mode = "gmii"; status = "okay"; }; @@ -205,19 +205,19 @@ }; }; - ehci@e4800000 { + usb@e4800000 { status = "okay"; }; - ehci@e5800000 { + usb@e5800000 { status = "okay"; }; - ohci@e4000000 { + usb@e4000000 { status = "okay"; }; - ohci@e5000000 { + usb@e5000000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/st/spear1310.dtsi b/arch/arm/boot/dts/st/spear1310.dtsi index ba827d60bf07..1498996be14e 100644 --- a/arch/arm/boot/dts/st/spear1310.dtsi +++ b/arch/arm/boot/dts/st/spear1310.dtsi @@ -128,7 +128,7 @@ status = "disabled"; }; - gmac1: eth@5c400000 { + gmac1: ethernet@5c400000 { compatible = "st,spear600-gmac"; reg = <0x5c400000 0x8000>; interrupts = <0 95 0x4>; @@ -137,7 +137,7 @@ status = "disabled"; }; - gmac2: eth@5c500000 { + gmac2: ethernet@5c500000 { compatible = "st,spear600-gmac"; reg = <0x5c500000 0x8000>; interrupts = <0 96 0x4>; @@ -146,7 +146,7 @@ status = "disabled"; }; - gmac3: eth@5c600000 { + gmac3: ethernet@5c600000 { compatible = "st,spear600-gmac"; reg = <0x5c600000 0x8000>; interrupts = <0 97 0x4>; @@ -155,7 +155,7 @@ status = "disabled"; }; - gmac4: eth@5c700000 { + gmac4: ethernet@5c700000 { compatible = "st,spear600-gmac"; reg = <0x5c700000 0x8000>; interrupts = <0 98 0x4>; diff --git a/arch/arm/boot/dts/st/spear1340-evb.dts b/arch/arm/boot/dts/st/spear1340-evb.dts index 9b515b21a633..9e7c356b1d9e 100644 --- a/arch/arm/boot/dts/st/spear1340-evb.dts +++ b/arch/arm/boot/dts/st/spear1340-evb.dts @@ -157,7 +157,7 @@ }; }; - gmac0: eth@e2000000 { + gmac0: ethernet@e2000000 { phy-mode = "rgmii"; status = "okay"; }; @@ -203,7 +203,7 @@ }; }; - ehci@e4800000 { + usb@e4800000 { status = "okay"; }; @@ -221,7 +221,7 @@ }; }; - ehci@e5800000 { + usb@e5800000 { status = "okay"; }; @@ -238,11 +238,11 @@ status = "okay"; }; - ohci@e4000000 { + usb@e4000000 { status = "okay"; }; - ohci@e5000000 { + usb@e5000000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/st/spear13xx.dtsi b/arch/arm/boot/dts/st/spear13xx.dtsi index 3b6897084e26..159e941708ca 100644 --- a/arch/arm/boot/dts/st/spear13xx.dtsi +++ b/arch/arm/boot/dts/st/spear13xx.dtsi @@ -149,7 +149,7 @@ status = "disabled"; }; - gmac0: eth@e2000000 { + gmac0: ethernet@e2000000 { compatible = "st,spear600-gmac"; reg = <0xe2000000 0x8000>; interrupts = <0 33 0x4>, @@ -174,7 +174,7 @@ status = "disabled"; }; - ehci@e4800000 { + usb@e4800000 { compatible = "st,spear600-ehci", "usb-ehci"; reg = <0xe4800000 0x1000>; interrupts = <0 64 0x4>; @@ -182,7 +182,7 @@ status = "disabled"; }; - ehci@e5800000 { + usb@e5800000 { compatible = "st,spear600-ehci", "usb-ehci"; reg = <0xe5800000 0x1000>; interrupts = <0 66 0x4>; @@ -190,7 +190,7 @@ status = "disabled"; }; - ohci@e4000000 { + usb@e4000000 { compatible = "st,spear600-ohci", "usb-ohci"; reg = <0xe4000000 0x1000>; interrupts = <0 65 0x4>; @@ -198,7 +198,7 @@ status = "disabled"; }; - ohci@e5000000 { + usb@e5000000 { compatible = "st,spear600-ohci", "usb-ohci"; reg = <0xe5000000 0x1000>; interrupts = <0 67 0x4>; diff --git a/arch/arm/boot/dts/st/spear300-evb.dts b/arch/arm/boot/dts/st/spear300-evb.dts index 303ef29fb805..80fae76d4610 100644 --- a/arch/arm/boot/dts/st/spear300-evb.dts +++ b/arch/arm/boot/dts/st/spear300-evb.dts @@ -69,7 +69,7 @@ status = "okay"; }; - gmac: eth@e0800000 { + gmac: ethernet@e0800000 { status = "okay"; }; @@ -119,15 +119,15 @@ status = "okay"; }; - ehci@e1800000 { + usb@e1800000 { status = "okay"; }; - ohci@e1900000 { + usb@e1900000 { status = "okay"; }; - ohci@e2100000 { + usb@e2100000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/st/spear310-evb.dts b/arch/arm/boot/dts/st/spear310-evb.dts index ea0b53036f7b..a3449eb7e59b 100644 --- a/arch/arm/boot/dts/st/spear310-evb.dts +++ b/arch/arm/boot/dts/st/spear310-evb.dts @@ -88,7 +88,7 @@ status = "okay"; }; - gmac: eth@e0800000 { + gmac: ethernet@e0800000 { status = "okay"; }; @@ -133,15 +133,15 @@ status = "okay"; }; - ehci@e1800000 { + usb@e1800000 { status = "okay"; }; - ohci@e1900000 { + usb@e1900000 { status = "okay"; }; - ohci@e2100000 { + usb@e2100000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/st/spear320-evb.dts b/arch/arm/boot/dts/st/spear320-evb.dts index 3c026d021c92..984075e60634 100644 --- a/arch/arm/boot/dts/st/spear320-evb.dts +++ b/arch/arm/boot/dts/st/spear320-evb.dts @@ -84,7 +84,7 @@ status = "okay"; }; - gmac: eth@e0800000 { + gmac: ethernet@e0800000 { status = "okay"; }; @@ -142,15 +142,15 @@ status = "okay"; }; - ehci@e1800000 { + usb@e1800000 { status = "okay"; }; - ohci@e1900000 { + usb@e1900000 { status = "okay"; }; - ohci@e2100000 { + usb@e2100000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/st/spear320-hmi.dts b/arch/arm/boot/dts/st/spear320-hmi.dts index 721e5ee7b680..8010918e5257 100644 --- a/arch/arm/boot/dts/st/spear320-hmi.dts +++ b/arch/arm/boot/dts/st/spear320-hmi.dts @@ -92,7 +92,7 @@ status = "okay"; }; - ehci@e1800000 { + usb@e1800000 { status = "okay"; }; @@ -147,11 +147,11 @@ }; }; - ohci@e1900000 { + usb@e1900000 { status = "okay"; }; - ohci@e2100000 { + usb@e2100000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/st/spear3xx.dtsi b/arch/arm/boot/dts/st/spear3xx.dtsi index cc88ebe7a60c..54e87ac98164 100644 --- a/arch/arm/boot/dts/st/spear3xx.dtsi +++ b/arch/arm/boot/dts/st/spear3xx.dtsi @@ -46,7 +46,7 @@ status = "disabled"; }; - gmac: eth@e0800000 { + gmac: ethernet@e0800000 { compatible = "snps,dwmac-3.40a"; reg = <0xe0800000 0x8000>; interrupts = <23 22>; @@ -73,21 +73,21 @@ status = "disabled"; }; - ehci@e1800000 { + usb@e1800000 { compatible = "st,spear600-ehci", "usb-ehci"; reg = <0xe1800000 0x1000>; interrupts = <26>; status = "disabled"; }; - ohci@e1900000 { + usb@e1900000 { compatible = "st,spear600-ohci", "usb-ohci"; reg = <0xe1900000 0x1000>; interrupts = <25>; status = "disabled"; }; - ohci@e2100000 { + usb@e2100000 { compatible = "st,spear600-ohci", "usb-ohci"; reg = <0xe2100000 0x1000>; interrupts = <27>; diff --git a/arch/arm/boot/dts/st/spear600.dtsi b/arch/arm/boot/dts/st/spear600.dtsi index 6b67c0ceaed9..9a93367445ca 100644 --- a/arch/arm/boot/dts/st/spear600.dtsi +++ b/arch/arm/boot/dts/st/spear600.dtsi @@ -91,7 +91,7 @@ status = "disabled"; }; - ehci_usb0: ehci@e1800000 { + ehci_usb0: usb@e1800000 { compatible = "st,spear600-ehci", "usb-ehci"; reg = <0xe1800000 0x1000>; interrupt-parent = <&vic1>; @@ -99,7 +99,7 @@ status = "disabled"; }; - ehci_usb1: ehci@e2000000 { + ehci_usb1: usb@e2000000 { compatible = "st,spear600-ehci", "usb-ehci"; reg = <0xe2000000 0x1000>; interrupt-parent = <&vic1>; @@ -107,7 +107,7 @@ status = "disabled"; }; - ohci_usb0: ohci@e1900000 { + ohci_usb0: usb@e1900000 { compatible = "st,spear600-ohci", "usb-ohci"; reg = <0xe1900000 0x1000>; interrupt-parent = <&vic1>; @@ -115,7 +115,7 @@ status = "disabled"; }; - ohci_usb1: ohci@e2100000 { + ohci_usb1: usb@e2100000 { compatible = "st,spear600-ohci", "usb-ohci"; reg = <0xe2100000 0x1000>; interrupt-parent = <&vic1>; diff --git a/arch/arm/boot/dts/st/stm32f746.dtsi b/arch/arm/boot/dts/st/stm32f746.dtsi index 2537b3d47e6f..208f8c6dfc9d 100644 --- a/arch/arm/boot/dts/st/stm32f746.dtsi +++ b/arch/arm/boot/dts/st/stm32f746.dtsi @@ -43,6 +43,7 @@ #include "../armv7-m.dtsi" #include <dt-bindings/clock/stm32fx-clock.h> #include <dt-bindings/mfd/stm32f7-rcc.h> +#include <dt-bindings/interrupt-controller/irq.h> / { #address-cells = <1>; @@ -245,6 +246,39 @@ }; }; + lptimer1: timer@40002400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-lptimer"; + reg = <0x40002400 0x400>; + interrupts-extended = <&exti 23 IRQ_TYPE_EDGE_RISING>; + clocks = <&rcc 1 CLK_LPTIMER>; + clock-names = "mux"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm-lp"; + #pwm-cells = <3>; + status = "disabled"; + }; + + trigger@0 { + compatible = "st,stm32-lptimer-trigger"; + reg = <0>; + status = "disabled"; + }; + + counter { + compatible = "st,stm32-lptimer-counter"; + status = "disabled"; + }; + + timer { + compatible = "st,stm32-lptimer-timer"; + status = "disabled"; + }; + }; + rtc: rtc@40002800 { compatible = "st,stm32-rtc"; reg = <0x40002800 0x400>; diff --git a/arch/arm/boot/dts/st/stm32h7-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32h7-pinctrl.dtsi index 7f1d234e1024..8a6db484383d 100644 --- a/arch/arm/boot/dts/st/stm32h7-pinctrl.dtsi +++ b/arch/arm/boot/dts/st/stm32h7-pinctrl.dtsi @@ -198,7 +198,7 @@ }; }; - uart4_pins: uart4-0 { + uart4_pins_a: uart4-0 { pins1 { pinmux = <STM32_PINMUX('A', 0, AF8)>; /* UART4_TX */ bias-disable; @@ -211,7 +211,20 @@ }; }; - usart1_pins: usart1-0 { + uart8_pins_a: uart8-0 { + pins1 { + pinmux = <STM32_PINMUX('J', 8, AF8)>; /* UART8_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('J', 9, AF8)>; /* UART8_RX */ + bias-disable; + }; + }; + + usart1_pins_a: usart1-0 { pins1 { pinmux = <STM32_PINMUX('B', 14, AF4)>; /* USART1_TX */ bias-disable; @@ -224,7 +237,20 @@ }; }; - usart2_pins: usart2-0 { + usart1_pins_b: usart1-1 { + pins1 { + pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('A', 10, AF7)>; /* USART1_RX */ + bias-disable; + }; + }; + + usart2_pins_a: usart2-0 { pins1 { pinmux = <STM32_PINMUX('D', 5, AF7)>; /* USART2_TX */ bias-disable; @@ -237,7 +263,7 @@ }; }; - usart3_pins: usart3-0 { + usart3_pins_a: usart3-0 { pins1 { pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */ <STM32_PINMUX('D', 12, AF7)>; /* USART3_RTS_DE */ diff --git a/arch/arm/boot/dts/st/stm32h743.dtsi b/arch/arm/boot/dts/st/stm32h743.dtsi index b8d4c44c8a82..2f19cfbc57ad 100644 --- a/arch/arm/boot/dts/st/stm32h743.dtsi +++ b/arch/arm/boot/dts/st/stm32h743.dtsi @@ -211,6 +211,14 @@ }; }; + uart8: serial@40007c00 { + compatible = "st,stm32h7-uart"; + reg = <0x40007c00 0x400>; + interrupts = <83>; + status = "disabled"; + clocks = <&rcc UART8_CK>; + }; + usart1: serial@40011000 { compatible = "st,stm32h7-uart"; reg = <0x40011000 0x400>; diff --git a/arch/arm/boot/dts/st/stm32h743i-disco.dts b/arch/arm/boot/dts/st/stm32h743i-disco.dts index 2b452883a708..8451a54a9a08 100644 --- a/arch/arm/boot/dts/st/stm32h743i-disco.dts +++ b/arch/arm/boot/dts/st/stm32h743i-disco.dts @@ -105,7 +105,7 @@ }; &usart2 { - pinctrl-0 = <&usart2_pins>; + pinctrl-0 = <&usart2_pins_a>; pinctrl-names = "default"; status = "okay"; }; diff --git a/arch/arm/boot/dts/st/stm32h743i-eval.dts b/arch/arm/boot/dts/st/stm32h743i-eval.dts index 5c5d8059bdc7..4b0ced27b80e 100644 --- a/arch/arm/boot/dts/st/stm32h743i-eval.dts +++ b/arch/arm/boot/dts/st/stm32h743i-eval.dts @@ -145,7 +145,7 @@ }; &usart1 { - pinctrl-0 = <&usart1_pins>; + pinctrl-0 = <&usart1_pins_a>; pinctrl-names = "default"; status = "okay"; }; diff --git a/arch/arm/boot/dts/st/stm32h747i-disco.dts b/arch/arm/boot/dts/st/stm32h747i-disco.dts new file mode 100644 index 000000000000..99f0255dae8e --- /dev/null +++ b/arch/arm/boot/dts/st/stm32h747i-disco.dts @@ -0,0 +1,136 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 Amarula Solutions, Dario Binacchi <dario.binacchi@amarulasolutions.com> + */ + +/dts-v1/; +#include "stm32h743.dtsi" +#include "stm32h7-pinctrl.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> + +/ { + model = "STMicroelectronics STM32H747i-Discovery board"; + compatible = "st,stm32h747i-disco", "st,stm32h747"; + + chosen { + bootargs = "root=/dev/ram"; + stdout-path = "serial0:115200n8"; + }; + + memory@d0000000 { + device_type = "memory"; + reg = <0xd0000000 0x2000000>; + }; + + aliases { + serial0 = &usart1; + serial1 = &uart8; + }; + + v3v3: regulator-v3v3 { + compatible = "regulator-fixed"; + regulator-name = "v3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + leds { + compatible = "gpio-leds"; + led-green { + gpios = <&gpioi 12 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + led-orange { + gpios = <&gpioi 13 GPIO_ACTIVE_LOW>; + }; + led-red { + gpios = <&gpioi 14 GPIO_ACTIVE_LOW>; + }; + led-blue { + gpios = <&gpioi 15 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + button-0 { + label = "User"; + linux,code = <KEY_WAKEUP>; + gpios = <&gpioc 13 GPIO_ACTIVE_HIGH>; + }; + button-1 { + label = "JoySel"; + linux,code = <KEY_ENTER>; + gpios = <&gpiok 2 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + }; + button-2 { + label = "JoyDown"; + linux,code = <KEY_DOWN>; + gpios = <&gpiok 3 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + }; + button-3 { + label = "JoyUp"; + linux,code = <KEY_UP>; + gpios = <&gpiok 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + }; + button-4 { + label = "JoyLeft"; + linux,code = <KEY_LEFT>; + gpios = <&gpiok 4 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + }; + button-5 { + label = "JoyRight"; + linux,code = <KEY_RIGHT>; + gpios = <&gpiok 5 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + }; + }; +}; + +&clk_hse { + clock-frequency = <25000000>; +}; + +&mac { + status = "disabled"; + pinctrl-0 = <ðernet_rmii>; + pinctrl-names = "default"; + phy-mode = "rmii"; + phy-handle = <&phy0>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + phy0: ethernet-phy@0 { + reg = <0>; + }; + }; +}; + +&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; + cd-gpios = <&gpioi 8 GPIO_ACTIVE_LOW>; + broken-cd; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&v3v3>; + status = "okay"; +}; + +&usart1 { + pinctrl-0 = <&usart1_pins_b>; + pinctrl-names = "default"; + status = "okay"; +}; + +&uart8 { + pinctrl-0 = <&uart8_pins_a>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/st/stm32h750i-art-pi.dts b/arch/arm/boot/dts/st/stm32h750i-art-pi.dts index 44c307f8b09c..56c53e262da7 100644 --- a/arch/arm/boot/dts/st/stm32h750i-art-pi.dts +++ b/arch/arm/boot/dts/st/stm32h750i-art-pi.dts @@ -167,7 +167,7 @@ #address-cells = <1>; #size-cells = <0>; - brcmf: bcrmf@1 { + brcmf: wifi@1 { reg = <1>; compatible = "brcm,bcm4329-fmac"; }; @@ -197,14 +197,14 @@ }; &usart2 { - pinctrl-0 = <&usart2_pins>; + pinctrl-0 = <&usart2_pins_a>; pinctrl-names = "default"; status = "disabled"; }; &usart3 { pinctrl-names = "default"; - pinctrl-0 = <&usart3_pins>; + pinctrl-0 = <&usart3_pins_a>; dmas = <&dmamux1 45 0x400 0x05>, <&dmamux1 46 0x400 0x05>; dma-names = "rx", "tx"; @@ -221,7 +221,7 @@ }; &uart4 { - pinctrl-0 = <&uart4_pins>; + pinctrl-0 = <&uart4_pins_a>; pinctrl-names = "default"; status = "okay"; }; diff --git a/arch/arm/boot/dts/st/stm32mp131.dtsi b/arch/arm/boot/dts/st/stm32mp131.dtsi index 8512a6e46b33..ace9495b9b06 100644 --- a/arch/arm/boot/dts/st/stm32mp131.dtsi +++ b/arch/arm/boot/dts/st/stm32mp131.dtsi @@ -1018,6 +1018,9 @@ reg = <0x4 0x2>; bits = <0 12>; }; + vrefint: vrefin-cal@52 { + reg = <0x52 0x2>; + }; ts_cal1: calib@5c { reg = <0x5c 0x2>; }; @@ -1063,6 +1066,8 @@ interrupts = <0>; dmas = <&dmamux1 10 0x400 0x80000001>; dma-names = "rx"; + nvmem-cells = <&vrefint>; + nvmem-cell-names = "vrefint"; status = "disabled"; channel@13 { @@ -1609,6 +1614,8 @@ snps,axi-config = <&stmmac_axi_config_1>; snps,tso; access-controllers = <&etzpc 48>; + nvmem-cells = <ðernet_mac1_address>; + nvmem-cell-names = "mac-address"; status = "disabled"; stmmac_axi_config_1: stmmac-axi-config { diff --git a/arch/arm/boot/dts/st/stm32mp133.dtsi b/arch/arm/boot/dts/st/stm32mp133.dtsi index 73e470019ce4..49583137b597 100644 --- a/arch/arm/boot/dts/st/stm32mp133.dtsi +++ b/arch/arm/boot/dts/st/stm32mp133.dtsi @@ -60,6 +60,8 @@ interrupts = <0>; dmas = <&dmamux1 9 0x400 0x80000001>; dma-names = "rx"; + nvmem-cells = <&vrefint>; + nvmem-cell-names = "vrefint"; status = "disabled"; channel@18 { @@ -91,6 +93,8 @@ snps,axi-config = <&stmmac_axi_config_2>; snps,tso; access-controllers = <&etzpc 49>; + nvmem-cells = <ðernet_mac2_address>; + nvmem-cell-names = "mac-address"; status = "disabled"; stmmac_axi_config_2: stmmac-axi-config { diff --git a/arch/arm/boot/dts/st/stm32mp135f-dk.dts b/arch/arm/boot/dts/st/stm32mp135f-dk.dts index 19a32f7d4d7d..9764a6bfa5b4 100644 --- a/arch/arm/boot/dts/st/stm32mp135f-dk.dts +++ b/arch/arm/boot/dts/st/stm32mp135f-dk.dts @@ -421,7 +421,7 @@ #size-cells = <0>; status = "okay"; - brcmf: bcrmf@1 { + brcmf: wifi@1 { reg = <1>; compatible = "brcm,bcm4329-fmac"; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/st/stm32mp13xx-dhcor-som.dtsi b/arch/arm/boot/dts/st/stm32mp13xx-dhcor-som.dtsi index 6236ce2a6968..c18156807027 100644 --- a/arch/arm/boot/dts/st/stm32mp13xx-dhcor-som.dtsi +++ b/arch/arm/boot/dts/st/stm32mp13xx-dhcor-som.dtsi @@ -287,7 +287,7 @@ #address-cells = <1>; #size-cells = <0>; - brcmf: bcrmf@1 { /* muRata 1YN */ + brcmf: wifi@1 { /* muRata 1YN */ reg = <1>; compatible = "infineon,cyw43439-fmac", "brcm,bcm4329-fmac"; interrupt-parent = <&gpioe>; diff --git a/arch/arm/boot/dts/st/stm32mp15-scmi.dtsi b/arch/arm/boot/dts/st/stm32mp15-scmi.dtsi index dc3b09f2f2af..98552fe45d4e 100644 --- a/arch/arm/boot/dts/st/stm32mp15-scmi.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15-scmi.dtsi @@ -4,11 +4,15 @@ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. */ +#include <dt-bindings/regulator/st,stm32mp15-regulator.h> + / { firmware { optee: optee { compatible = "linaro,optee-tz"; method = "smc"; + interrupt-parent = <&intc>; + interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; }; scmi: scmi { @@ -35,21 +39,21 @@ #size-cells = <0>; scmi_reg11: regulator@0 { - reg = <0>; + reg = <VOLTD_SCMI_REG11>; regulator-name = "reg11"; regulator-min-microvolt = <1100000>; regulator-max-microvolt = <1100000>; }; scmi_reg18: regulator@1 { - reg = <1>; + reg = <VOLTD_SCMI_REG18>; regulator-name = "reg18"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; scmi_usb33: regulator@2 { - reg = <2>; + reg = <VOLTD_SCMI_USB33>; regulator-name = "usb33"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; diff --git a/arch/arm/boot/dts/st/stm32mp157a-iot-box.dts b/arch/arm/boot/dts/st/stm32mp157a-iot-box.dts index 6a5a4af25bd9..84497026a106 100644 --- a/arch/arm/boot/dts/st/stm32mp157a-iot-box.dts +++ b/arch/arm/boot/dts/st/stm32mp157a-iot-box.dts @@ -46,7 +46,7 @@ #address-cells = <1>; #size-cells = <0>; - brcmf: bcrmf@1 { + brcmf: wifi@1 { reg = <1>; compatible = "brcm,bcm4329-fmac"; }; diff --git a/arch/arm/boot/dts/st/stm32mp157c-dk2.dts b/arch/arm/boot/dts/st/stm32mp157c-dk2.dts index 324f7bb988d1..1b34fbe10b4f 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-dk2.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-dk2.dts @@ -115,7 +115,7 @@ #size-cells = <0>; status = "okay"; - brcmf: bcrmf@1 { + brcmf: wifi@1 { reg = <1>; compatible = "brcm,bcm4329-fmac"; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/st/stm32mp157c-ultra-fly-sbc.dts b/arch/arm/boot/dts/st/stm32mp157c-ultra-fly-sbc.dts new file mode 100644 index 000000000000..ac42d462d449 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp157c-ultra-fly-sbc.dts @@ -0,0 +1,1152 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) Ultratronik GmbH 2024-2025 - All Rights Reserved + */ + +/dts-v1/; +#include "stm32mp157.dtsi" +#include "stm32mp15xc.dtsi" +#include "stm32mp15-pinctrl.dtsi" +#include "stm32mp15xxac-pinctrl.dtsi" +#include <dt-bindings/pinctrl/stm32-pinfunc.h> +#include <dt-bindings/mfd/st,stpmic1.h> +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "STM STM32MP15x Ultratronik MMI_A7 board"; + compatible = "ultratronik,stm32mp157c-ultra-fly-sbc", "st,stm32mp157"; + + aliases { + ethernet0 = ðernet0; + serial0 = &uart4; + serial1 = &uart5; + serial2 = &uart7; + serial3 = &usart1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@c0000000 { + device_type = "memory"; + reg = <0xC0000000 0x40000000>; + }; + + usb_otg_vbus: regulator-0 { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpioh 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + retram: retram@38000000 { + compatible = "shared-dma-pool"; + reg = <0x38000000 0x10000>; + no-map; + }; + + mcuram: mcuram@30000000 { + compatible = "shared-dma-pool"; + reg = <0x30000000 0x40000>; + no-map; + }; + + mcuram2: mcuram2@10000000 { + compatible = "shared-dma-pool"; + reg = <0x10000000 0x40000>; + no-map; + }; + + vdev0vring0: vdev0vring0@10040000 { + compatible = "shared-dma-pool"; + reg = <0x10040000 0x2000>; + no-map; + }; + + vdev0vring1: vdev0vring1@10042000 { + compatible = "shared-dma-pool"; + reg = <0x10042000 0x2000>; + no-map; + }; + + vdev0buffer: vdev0buffer@10044000 { + compatible = "shared-dma-pool"; + reg = <0x10044000 0x4000>; + no-map; + }; + + gpu_reserved: gpu@f8000000 { + reg = <0xf8000000 0x8000000>; + no-map; + }; + }; + + leds: leds { + compatible = "gpio-leds"; + + led0{ + label = "buzzer"; + gpios = <&gpiof 2 GPIO_ACTIVE_HIGH>; + default-state = "off"; + linux,default-trigger = "none"; + }; + + led1 { + label = "led1"; + gpios = <&gpioa 12 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led2 { + label = "led2"; + gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led3 { + label = "led3"; + gpios = <&gpioa 14 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + + key-1 { + label = "KEY1"; + gpios = <&gpiod 1 GPIO_ACTIVE_HIGH>; + wakeup-source; + linux,code = <2>; + }; + + key-2 { + label = "KEY2"; + gpios = <&gpiod 7 GPIO_ACTIVE_HIGH>; + wakeup-source; + linux,code = <3>; + }; + }; +}; + +&adc { + pinctrl-names = "default"; + pinctrl-0 = <&adc1_ux_ain_pins_a>; + vdd-supply = <&vdd>; + vdda-supply = <&vdd>; + vref-supply = <&vrefbuf>; + status = "okay"; + + adc1: adc@0 { + st,min-sample-time-nsecs = <5000>; + st,adc-channels = <0 1 6 13>; /* ANA0 ANA1 PF12 PC3 */ + status = "okay"; + }; + + adc2: adc@100 { + st,adc-channels = <0 1 12>; /* ANA0 ANA1 INT_TEMP*/ + st,min-sample-time-nsecs = <10000>; + status = "okay"; + + channel@12 { + reg = <12>; /* Channel 12 = internal temperature sensor */ + label = "internal_temp"; + }; + }; +}; + +&dac { + pinctrl-names = "default"; + pinctrl-0 = <&dac_ux_ch1_pins_a &dac_ux_ch2_pins_a>; + vref-supply = <&vrefbuf>; + status = "okay"; + + dac1: dac@1 { + status = "okay"; + }; + + dac2: dac@2 { + status = "okay"; + }; +}; + +&dts { + compatible = "st,stm32-thermal"; + status = "okay"; +}; + +ðernet0 { + status = "okay"; + pinctrl-0 = <ðernet0_ux_rgmii_pins_a>; + pinctrl-1 = <ðernet0_ux_rgmii_pins_sleep_a>; + pinctrl-names = "default", "sleep"; + phy-mode = "rgmii-id"; + phy-handle = <&phy1>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + phy1: ethernet-phy@1 { + reg = <1>; + }; + }; +}; + +&gpioa { + gpio-line-names = + "#PMIC_IRQ", "", "", "", "DAC1", "DAC2", "", "", + "", "", "OTG_ID", "TIM1_4", "#LED1", "#LED2", "#LED3", ""; +}; + +&gpiob { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpioc { + gpio-line-names = + "#AMP_SD", "", "", "ANA5", "", "", "", "", + "", "", "", "", "", "PMIC_WAKEUP", "", ""; +}; + +&gpiod { + gpio-line-names = + "#G_INT", "#TASTER1", "", "", "GPIO1", "GPIO2", "", "#TASTER2", + "", "", "", "", "", "", "TIM4_3", "TIM4_4"; +}; + +&gpioe { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "PWM2", "", "", "", "", ""; +}; + +&gpiof { + gpio-line-names = + "#SD1_CD", "SD1_WP", "BUZZER", "#DISP_POW", "BKL_POW", "#CAM_RES", "", "", + "", "TIM17_1N", "", "CAM_PWDN", "ANA6", "ENA_USB", "", ""; +}; + +&gpiog { + gpio-line-names = + "#ESP_RES", "#ESP_BOOT", "GPIO3", "GPIO4", "", "", "", "", + "", "#TOUCH_IRQ", "", "", "", "", "", "#PCAP_RES"; +}; + +&gpioh { + gpio-line-names = + "", "CAM_LED", "", "USB_OTG_PWR", "", "USB_OTG_OC", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpioi { + gpio-line-names = + "BKL_PWM", "", "", "", "", "", "", "", + "#SPI_CS0", "", "", "#SPI_CS1", "", "", "", ""; +}; + +&gpioj { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpiok { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpioz { + gpio-line-names = + "", "", "", "#SPI_CS2", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpu { + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c1_ux_pins_a>; + pinctrl-1 = <&i2c1_ux_pins_sleep_a>; + i2c-scl-rising-time-ns = <100>; + i2c-scl-falling-time-ns = <7>; + status = "okay"; + /delete-property/dmas; + /delete-property/dma-names; + + rtc@32 { + compatible = "epson,rx8900"; + reg = <0x32>; + epson,vdet-disable; + trickle-diode-disable; + }; +}; + +&i2c4 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c4_ux_pins_a>; + pinctrl-1 = <&i2c4_ux_pins_sleep_a>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + /delete-property/dmas; + /delete-property/dma-names; + + pmic: pmic@33 { + compatible = "st,stpmic1"; + reg = <0x33>; + interrupts-extended = <&exti 0 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + + regulators { + compatible = "st,stpmic1-regulators"; + + ldo1-supply = <&v3v3>; + ldo3-supply = <&vdd_ddr>; + ldo6-supply = <&v3v3>; + pwr_sw1-supply = <&bst_out>; + pwr_sw2-supply = <&bst_out>; + + vddcore: buck1 { + regulator-name = "vddcore"; + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vdd_ddr: buck2 { + regulator-name = "vdd_ddr"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vdd: buck3 { + regulator-name = "vdd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + st,mask-reset; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + v3v3: buck4 { + regulator-name = "v3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-over-current-protection; + regulator-initial-mode = <0>; + }; + + vtt_ddr: ldo3 { + regulator-name = "vtt_ddr"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <750000>; + regulator-always-on; + regulator-over-current-protection; + }; + + vdd_usb: ldo4 { + regulator-name = "vdd_usb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + interrupts = <IT_CURLIM_LDO4 0>; + }; + + v1v8: ldo6 { + regulator-name = "v1v8"; + regulator-min-microvolt = <1600000>;/* offset +200 mv ??? */ + regulator-max-microvolt = <1600000>;/* real 1800000 */ + regulator-always-on; + interrupts = <IT_CURLIM_LDO6 0>; + }; + + vref_ddr: vref_ddr { + regulator-name = "vref_ddr"; + regulator-always-on; + }; + + bst_out: boost { + regulator-name = "bst_out"; + interrupts = <IT_OCP_BOOST 0>; + }; + + vbus_otg: pwr_sw1 { + regulator-name = "vbus_otg"; + interrupts = <IT_OCP_OTG 0>; + regulator-active-discharge = <1>; + }; + + vbus_sw: pwr_sw2 { + regulator-name = "vbus_sw"; + interrupts = <IT_OCP_SWOUT 0>; + regulator-active-discharge = <1>; + }; + }; + }; +}; + +&iwdg2 { + timeout-sec = <32>; + status = "okay"; +}; + +&m_can2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&m_can2_ux_pins_a>; + pinctrl-1 = <&m_can2_ux_sleep_pins_a>; + status = "okay"; +}; + +&pinctrl { + + adc1_ux_ain_pins_a: adc1-ux-ain-0 { + pins { + pinmux = <STM32_PINMUX('F',12, ANALOG)>, /* ADC1 in6 */ + <STM32_PINMUX('C', 3, ANALOG)>; /* ADC2 in13 */ + }; + }; + + dac_ux_ch1_pins_a: dac-ux-ch1-0 { + pins { + pinmux = <STM32_PINMUX('A', 4, ANALOG)>; + }; + }; + + dac_ux_ch2_pins_a: dac-ux-ch2-0 { + pins { + pinmux = <STM32_PINMUX('A', 5, ANALOG)>; + }; + }; + + ethernet0_ux_rgmii_pins_a: rgmii-ux-0 { + pins1 { + pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */ + <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */ + <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */ + <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */ + <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */ + <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */ + <STM32_PINMUX('B', 11, AF11)>; /* ETH_RGMII_TX_CTL */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + pins2 { + pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */ + <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */ + <STM32_PINMUX('B', 0, AF11)>, /* ETH_RGMII_RXD2 */ + <STM32_PINMUX('H', 7, AF11)>, /* ETH_RGMII_RXD3 */ + <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */ + <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */ + bias-disable; + }; + pins3 { + pinmux = <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins4 { + pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH_MDIO */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + ethernet0_ux_rgmii_pins_sleep_a: rgmii-ux-sleep-0 { + pins1 { + pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */ + <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */ + <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */ + <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */ + <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */ + <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */ + <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */ + <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */ + <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */ + <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */ + <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */ + <STM32_PINMUX('B', 0, ANALOG)>, /* ETH_RGMII_RXD2 */ + <STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD3 */ + <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */ + <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */ + }; + }; + + i2c1_ux_pins_a: i2c1-0 { + pins { + pinmux = <STM32_PINMUX('F', 14, AF5)>, /* I2C1_SCL */ + <STM32_PINMUX('F', 15, AF5)>; /* I2C1_SDA */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + i2c1_ux_pins_sleep_a: i2c1-1 { + pins { + pinmux = <STM32_PINMUX('F', 14, ANALOG)>, /* I2C1_SCL */ + <STM32_PINMUX('F', 15, ANALOG)>; /* I2C1_SDA */ + }; + }; + + m_can2_ux_pins_a: m-can2-ux-0 { + pins1 { + pinmux = <STM32_PINMUX('B', 6, AF9)>; /* CAN1_TX */ + slew-rate = <0>; + drive-push-pull; + bias-disable; + }; + + pins2 { + pinmux = <STM32_PINMUX('B', 5, AF9)>; /* CAN1_RX */ + bias-disable; + }; + }; + + m_can2_ux_sleep_pins_a: m-can2-ux-sleep-0 { + pins { + pinmux = <STM32_PINMUX('B', 6, ANALOG)>, /* CAN1_TX */ + <STM32_PINMUX('B', 5, ANALOG)>; /* CAN1_RX */ + }; + }; + pwm1_ux_pins_a: pwm1-0 { + pins { + pinmux = <STM32_PINMUX('A',11, AF1)>, /* TIM1_CH4 */ + <STM32_PINMUX('E',10, AF1)>; /* TIM1_CH2N */ + bias-pull-down; + drive-push-pull; + slew-rate = <0>; + }; + }; + + pwm1_ux_sleep_pins_a: pwm1-sleep-0 { + pins { + pinmux = <STM32_PINMUX('A',11, ANALOG)>, /* TIM1_CH4 */ + <STM32_PINMUX('E',10, ANALOG)>; /* TIM1_CH2N */ + }; + }; + + pwm4_ux_pins_a: pwm4-0 { + pins { + pinmux = <STM32_PINMUX('D', 14, AF2)>, /* TIM4_CH3 */ + <STM32_PINMUX('D', 15, AF2)>; /* TIM4_CH4 */ + bias-disable; + }; + }; + + pwm4_ux_sleep_pins_a: pwm4-sleep-0 { + pins { + pinmux = <STM32_PINMUX('D', 14, ANALOG)>, /* TIM4_CH3 */ + <STM32_PINMUX('D', 15, ANALOG)>; /* TIM4_CH4 */ + }; + }; + + pwm5_ux_pins_a: pwm5-0 { + pins { + pinmux = <STM32_PINMUX('I', 0, AF2)>; /* TIM5_CH4 */ + bias-pull-down; + drive-push-pull; + slew-rate = <0>; + }; + }; + + pwm5_ux_sleep_pins_a: pwm5-sleep-0 { + pins { + pinmux = <STM32_PINMUX('I', 0, ANALOG)>; /* TIM5_CH4 */ + }; + }; + + pwm17_ux_pins_a: pwm17-0 { + pins { + pinmux = <STM32_PINMUX('F', 9, AF1)>; /* TIM17_CH1N */ + bias-pull-down; + drive-push-pull; + slew-rate = <0>; + }; + }; + + pwm17_ux_sleep_pins_a: pwm17-sleep-0 { + pins { + pinmux = <STM32_PINMUX('F', 9, ANALOG)>; /* TIM17_CH1N */ + }; + }; + + qspi_bk1_ux_pins_a: qspi-bk1-ux-0 { + pins1 { + pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */ + <STM32_PINMUX('D',12, AF9)>, /* QSPI_BK1_IO1 */ + <STM32_PINMUX('F', 7, AF9)>, /* QSPI_BK1_IO2 */ + <STM32_PINMUX('F', 6, AF9)>; /* QSPI_BK1_IO3 */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + + pins2 { + pinmux = <STM32_PINMUX('B',10, AF9)>; /* QSPI_BK1_NCS */ + bias-pull-up; + drive-push-pull; + slew-rate = <1>; + }; + }; + + qspi_bk1_ux_sleep_pins_a: qspi-bk1-ux-sleep-0 { + pins { + pinmux = <STM32_PINMUX('F', 8, ANALOG)>, /* QSPI_BK1_IO0 */ + <STM32_PINMUX('D',12, ANALOG)>, /* QSPI_BK1_IO1 */ + <STM32_PINMUX('F', 7, ANALOG)>, /* QSPI_BK1_IO2 */ + <STM32_PINMUX('F', 6, ANALOG)>, /* QSPI_BK1_IO3 */ + <STM32_PINMUX('B',10, ANALOG)>; /* QSPI_BK1_NCS */ + }; + }; + + qspi_clk_ux_pins_a: qspi-clk_ux-0 { + pins { + pinmux = <STM32_PINMUX('G', 7, AF9)>; /* QSPI_CLK */ + bias-disable; + drive-push-pull; + slew-rate = <3>; + }; + }; + + qspi_clk_ux_sleep_pins_a: qspi-clk-ux-sleep-0 { + pins { + pinmux = <STM32_PINMUX('G', 7, ANALOG)>; /* QSPI_CLK */ + }; + }; + + sai2a_ux_pins_a: sai2a-0 { + pins { + pinmux = <STM32_PINMUX('I', 5, AF10)>, /* SAI2_SCK_A */ + <STM32_PINMUX('D',11, AF10)>, /* SAI2_SD_A */ + <STM32_PINMUX('I', 7, AF10)>, /* SAI2_FS_A */ + <STM32_PINMUX('E', 0, AF10)>; /* SAI2_MCLK_A */ + slew-rate = <0>; + drive-push-pull; + bias-disable; + }; + }; + + sai2a_ux_sleep_pins_a: sai2a-1 { + pins { + pinmux = <STM32_PINMUX('I', 5, ANALOG)>, /* SAI2_SCK_A */ + <STM32_PINMUX('D',11, ANALOG)>, /* SAI2_SD_A */ + <STM32_PINMUX('I', 7, ANALOG)>, /* SAI2_FS_A */ + <STM32_PINMUX('E', 0, ANALOG)>; /* SAI2_MCLK_A */ + }; + }; + + sdmmc1_ux_b4_pins_a: sdmmc1-ux-b4-0 { + pins1 { + pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */ + <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */ + <STM32_PINMUX('C',10, AF12)>, /* SDMMC1_D2 */ + <STM32_PINMUX('C',11, AF12)>, /* SDMMC1_D3 */ + <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */ + slew-rate = <1>; + drive-push-pull; + bias-disable; + }; + pins2 { + pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */ + slew-rate = <2>; + drive-push-pull; + bias-disable; + }; + }; + + sdmmc1_ux_b4_od_pins_a: sdmmc1-b4-od-0 { + pins1 { + pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */ + <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */ + <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */ + <STM32_PINMUX('C', 11, AF12)>; /* SDMMC1_D3 */ + slew-rate = <1>; + drive-push-pull; + bias-disable; + }; + pins2 { + pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */ + slew-rate = <2>; + drive-push-pull; + bias-disable; + }; + pins3 { + pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */ + slew-rate = <1>; + drive-open-drain; + bias-disable; + }; + }; + + sdmmc1_ux_b4_sleep_pins_a: sdmmc1-b4-sleep-0 { + pins { + pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */ + <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */ + <STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1_D2 */ + <STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */ + <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */ + <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */ + }; + }; + + sdmmc2_ux_b4_pins_a: sdmmc2-ux-b4-0 { + pins1 { + pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */ + <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */ + <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */ + <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */ + <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + pins2 { + pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */ + slew-rate = <2>; + drive-push-pull; + bias-pull-up; + }; + }; + + sdmmc2_ux_b4_od_pins_a: sdmmc2-ux-b4-od-0 { + pins1 { + pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */ + <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */ + <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */ + <STM32_PINMUX('B', 4, AF9)>; /* SDMMC2_D3 */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + pins2 { + pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */ + slew-rate = <2>; + drive-push-pull; + bias-pull-up; + }; + pins3 { + pinmux = <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */ + slew-rate = <1>; + drive-open-drain; + bias-pull-up; + }; + }; + + sdmmc2_ux_b4_sleep_pins_a: sdmmc2-ux-b4-sleep-0 { + pins { + pinmux = <STM32_PINMUX('B', 14, ANALOG)>, /* SDMMC2_D0 */ + <STM32_PINMUX('B', 15, ANALOG)>, /* SDMMC2_D1 */ + <STM32_PINMUX('B', 3, ANALOG)>, /* SDMMC2_D2 */ + <STM32_PINMUX('B', 4, ANALOG)>, /* SDMMC2_D3 */ + <STM32_PINMUX('E', 3, ANALOG)>, /* SDMMC2_CK */ + <STM32_PINMUX('G', 6, ANALOG)>; /* SDMMC2_CMD */ + }; + }; + + sdmmc2_ux_d47_pins_a: sdmmc2-ux-d47-0 { + pins { + pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */ + <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */ + <STM32_PINMUX('E', 5, AF9)>, /* SDMMC2_D6 */ + <STM32_PINMUX('D', 3, AF9)>; /* SDMMC2_D7 */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + }; + + sdmmc2_ux_d47_sleep_pins_a: sdmmc2-ux-d47-sleep-0 { + pins { + pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */ + <STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */ + <STM32_PINMUX('E', 5, ANALOG)>, /* SDMMC2_D6 */ + <STM32_PINMUX('D', 3, ANALOG)>; /* SDMMC2_D7 */ + }; + }; + + uart4_ux_pins_a: uart4-ux-0 { + pins1 { + pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */ + bias-disable; + }; + }; + + uart4_ux_idle_pins_a: uart4-ux-idle-0 { + pins1 { + pinmux = <STM32_PINMUX('G', 11, ANALOG)>; /* UART4_TX */ + }; + pins2 { + pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */ + bias-disable; + }; + }; + + uart4_ux_sleep_pins_a: uart4-ux-sleep-0 { + pins { + pinmux = <STM32_PINMUX('G', 11, ANALOG)>, /* UART4_TX */ + <STM32_PINMUX('B', 2, ANALOG)>; /* UART4_RX */ + }; + }; + + uart5_ux_pins_a: uart5-0 { + pins1 { + pinmux = <STM32_PINMUX('B', 13, AF14)>; /* UART5_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('B', 12, AF14)>; /* UART5_RX */ + bias-disable; + }; + }; + + uart5_ux_idle_pins_a: uart5-idle-0 { + pins1 { + pinmux = <STM32_PINMUX('B', 13, ANALOG)>; /* UART5_TX */ + }; + pins2 { + pinmux = <STM32_PINMUX('B', 12, AF14)>; /* UART5_RX*/ + bias-disable; + }; + }; + + uart5_ux_sleep_pins_a: uart5-sleep-0 { + pins { + pinmux = <STM32_PINMUX('B', 13, ANALOG)>, /* UART5_TX */ + <STM32_PINMUX('B', 12, ANALOG)>; /* UART5_RX */ + }; + }; + + uart7_ux_pins_a: uart7-0 { + pins1 { + pinmux = <STM32_PINMUX('E', 8, AF7)>; /* USART7_TX */ + bias-pull-up; + drive-push-pull; + slew-rate = <0>; + }; + + pins2 { + pinmux = <STM32_PINMUX('E', 7, AF7)>; /* USART7_RX */ + bias-pull-up; + }; + pins3 { + pinmux = <STM32_PINMUX('E', 9, AF7)>; /* USART7_RTS/DE */ + }; + }; + + uart7_ux_idle_pins_a: uart7-idle-0 { + pins1 { + pinmux = <STM32_PINMUX('E', 8, ANALOG)>, /* USART7_TX */ + <STM32_PINMUX('E', 9, AF7)>; /* USART7_RTS/DE */ + }; + pins2 { + pinmux = <STM32_PINMUX('E', 7, AF7)>; /* USART7_RX */ + bias-disable; + }; + }; + + uart7_ux_sleep_pins_a: uart7-sleep-0 { + pins { + pinmux = <STM32_PINMUX('E', 8, ANALOG)>, /* USART7_TX */ + <STM32_PINMUX('E', 9, AF7)>, /* USART7_RTS/DE */ + <STM32_PINMUX('E', 7, ANALOG)>; /* USART7_RX */ + }; + }; +}; + +&pinctrl_z { + + i2c4_ux_pins_a: i2c4-ux-0 { + pins { + pinmux = <STM32_PINMUX('Z', 4, AF6)>, /* I2C4_SCL */ + <STM32_PINMUX('Z', 5, AF6)>; /* I2C4_SDA */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + i2c4_ux_pins_sleep_a: i2c4-1 { + pins { + pinmux = <STM32_PINMUX('Z', 4, ANALOG)>, /* I2C4_SCL */ + <STM32_PINMUX('Z', 5, ANALOG)>; /* I2C4_SDA */ + }; + }; + + spi1_ux_pins_a: spi1-ux-0 { + pins1 { + pinmux = <STM32_PINMUX('Z', 0, AF5)>, /* SPI1_SCK */ + <STM32_PINMUX('Z', 2, AF5)>; /* SPI1_MOSI */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + + pins2 { + pinmux = <STM32_PINMUX('Z', 1, AF5)>; /* SPI1_MISO */ + bias-disable; + }; + }; + + spi1_ux_sleep_pins_a: spi1-ux-sleep-0 { + pins { + pinmux = <STM32_PINMUX('Z', 0, ANALOG)>, /* SPI1_SCK */ + <STM32_PINMUX('Z', 1, ANALOG)>, /* SPI1_MISO */ + <STM32_PINMUX('Z', 2, ANALOG)>; /* SPI1_MOSI */ + }; + }; +}; + +&pwr_regulators { + vdd-supply = <&vdd>; + vdd_3v3_usbfs-supply = <&vdd_usb>; +}; + +&qspi { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qspi_clk_ux_pins_a &qspi_bk1_ux_pins_a>; + pinctrl-1 = <&qspi_clk_ux_sleep_pins_a &qspi_bk1_ux_sleep_pins_a>; + reg = <0x58003000 0x1000>, <0x70000000 0x1000000>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + flash0: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-rx-bus-width = <4>; + spi-max-frequency = <133000000>; + #address-cells = <1>; + #size-cells = <1>; + }; +}; + +&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_ux_b4_pins_a>; + pinctrl-1 = <&sdmmc1_ux_b4_od_pins_a>; + pinctrl-2 = <&sdmmc1_ux_b4_sleep_pins_a>; + broken-cd; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&v3v3>; + no-1-8-v; + status = "okay"; +}; + +&sdmmc2 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc2_ux_b4_pins_a &sdmmc2_ux_d47_pins_a>; + pinctrl-1 = <&sdmmc2_ux_b4_od_pins_a &sdmmc2_ux_d47_pins_a>; + pinctrl-2 = <&sdmmc2_ux_b4_sleep_pins_a &sdmmc2_ux_d47_sleep_pins_a>; + non-removable; + no-sd; + no-sdio; + st,neg-edge; + bus-width = <8>; + vmmc-supply = <&v3v3>; + vqmmc-supply = <&v3v3>; + mmc-ddr-3_3v; + status = "okay"; +}; + +&spi1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&spi1_ux_pins_a>; + pinctrl-1 = <&spi1_ux_sleep_pins_a>; + status = "okay"; + cs-gpios = <&gpioi 8 0>, <&gpioi 11 0>, <&gpioz 3 0>; + + flash: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&timers1 { + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; + + pwm { + pinctrl-0 = <&pwm1_ux_pins_a>; + pinctrl-1 = <&pwm1_ux_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + status = "okay"; + }; + + timer@0 { + status = "okay"; + }; +}; + +&timers4 { + dmas = <&dmamux1 31 0x400 0x5>; + dma-names = "ch3"; + status = "okay"; + + pwm4_4: pwm { + pinctrl-0 = <&pwm4_ux_pins_a>; + pinctrl-1 = <&pwm4_ux_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + status = "okay"; + }; +}; + +&timers5 { + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; + + pwm5_4: pwm { + pinctrl-0 = <&pwm5_ux_pins_a>; + pinctrl-1 = <&pwm5_ux_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + status = "okay"; + }; + + timer@4 { + status = "okay"; + }; +}; + +&timers17 { + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; + + pwm17_4: pwm { + pinctrl-0 = <&pwm17_ux_pins_a>; + pinctrl-1 = <&pwm17_ux_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + status = "okay"; + }; + + timer@16 { + status = "okay"; + }; +}; + +&uart4 { + /delete-property/dmas; + /delete-property/dma-names; + pinctrl-names = "default", "sleep", "idle", "no_console_suspend"; + pinctrl-0 = <&uart4_ux_pins_a>; + pinctrl-1 = <&uart4_ux_sleep_pins_a>; + pinctrl-2 = <&uart4_ux_idle_pins_a>; + pinctrl-3 = <&uart4_ux_pins_a>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&uart5_ux_pins_a>; + pinctrl-1 = <&uart5_ux_sleep_pins_a>; + pinctrl-2 = <&uart5_ux_idle_pins_a>; + status = "okay"; +}; + +&uart7 { + /delete-property/dmas; + /delete-property/dma-names; + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&uart7_ux_pins_a>; + pinctrl-1 = <&uart7_ux_sleep_pins_a>; + pinctrl-2 = <&uart7_ux_idle_pins_a>; + status = "okay"; +}; + +&usart1 { + /*Muxing happens in uboot*/ + status = "okay"; +}; + +&usbh_ehci { + phys = <&usbphyc_port0>; + phy-names = "usb"; + status = "okay"; +}; + +&usbh_ohci { + phys = <&usbphyc_port0>; + phy-names = "usb"; + status = "okay"; +}; + +&usbotg_hs { + phys = <&usbphyc_port1 0>; + phy-names = "usb2-phy"; + vbus-supply = <&usb_otg_vbus>; + status = "okay"; +}; + +&usbphyc { + status = "okay"; +}; + +&usbphyc_port0 { + phy-supply = <&vdd_usb>; + st,tune-hs-dc-level = <2>; + st,enable-fs-rftime-tuning; + st,enable-hs-rftime-reduction; + st,trim-hs-current = <15>; + st,trim-hs-impedance = <1>; + st,tune-squelch-level = <3>; + st,tune-hs-rx-offset = <2>; + st,no-lsfs-sc; +}; + +&usbphyc_port1 { + phy-supply = <&vdd_usb>; + st,tune-hs-dc-level = <2>; + st,enable-fs-rftime-tuning; + st,enable-hs-rftime-reduction; + st,trim-hs-current = <15>; + st,trim-hs-impedance = <1>; + st,tune-squelch-level = <3>; + st,tune-hs-rx-offset = <2>; + st,no-lsfs-sc; +}; + +&vrefbuf { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + vdda-supply = <&vdd>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/st/stm32mp157f-dk2-scmi.dtsi b/arch/arm/boot/dts/st/stm32mp157f-dk2-scmi.dtsi new file mode 100644 index 000000000000..89de85a2eff3 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp157f-dk2-scmi.dtsi @@ -0,0 +1,196 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2025 - All Rights Reserved + * Author: Amelie Delaunay <amelie.delaunay@foss.st.com> for STMicroelectronics. + */ + +#include "stm32mp15-scmi.dtsi" + +/ { + reserved-memory { + optee@de000000 { + reg = <0xde000000 0x2000000>; + no-map; + }; + }; + + arm_wdt: watchdog { + compatible = "arm,smc-wdt"; + arm,smc-id = <0xbc000000>; + status = "disabled"; + }; + +}; + +&adc { + vdd-supply = <&scmi_vdd>; + vdda-supply = <&scmi_vdd>; +}; + +&cpu0 { + clocks = <&scmi_clk CK_SCMI_MPU>; +}; + +&cpu1 { + clocks = <&scmi_clk CK_SCMI_MPU>; +}; + +&cryp1 { + clocks = <&scmi_clk CK_SCMI_CRYP1>; + resets = <&scmi_reset RST_SCMI_CRYP1>; +}; + +&cs42l51 { + VL-supply = <&scmi_v3v3>; + VD-supply = <&scmi_v1v8_audio>; + VA-supply = <&scmi_v1v8_audio>; + VAHP-supply = <&scmi_v1v8_audio>; +}; + +&dsi { + phy-dsi-supply = <&scmi_reg18>; + clocks = <&rcc DSI>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>; +}; + +&gpioz { + clocks = <&scmi_clk CK_SCMI_GPIOZ>; +}; + +&hash1 { + clocks = <&scmi_clk CK_SCMI_HASH1>; + resets = <&scmi_reset RST_SCMI_HASH1>; +}; + +&i2c1 { + hdmi-transmitter@39 { + iovcc-supply = <&scmi_v3v3_hdmi>; + cvcc12-supply = <&scmi_v1v2_hdmi>; + }; +}; + +&iwdg2 { + clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>; + status = "disabled"; +}; + +&m4_rproc { + /delete-property/ st,syscfg-holdboot; + resets = <&scmi_reset RST_SCMI_MCU>, + <&scmi_reset RST_SCMI_MCU_HOLD_BOOT>; + reset-names = "mcu_rst", "hold_boot"; +}; + +&mdma1 { + resets = <&scmi_reset RST_SCMI_MDMA>; +}; + +&optee { + interrupt-parent = <&intc>; + interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; +}; + +&pwr_regulators { + vdd-supply = <&scmi_vdd>; + vdd_3v3_usbfs-supply = <&scmi_vdd_usb>; + status = "disabled"; +}; + +&rcc { + compatible = "st,stm32mp1-rcc-secure", "syscon"; + clock-names = "hse", "hsi", "csi", "lse", "lsi"; + clocks = <&scmi_clk CK_SCMI_HSE>, + <&scmi_clk CK_SCMI_HSI>, + <&scmi_clk CK_SCMI_CSI>, + <&scmi_clk CK_SCMI_LSE>, + <&scmi_clk CK_SCMI_LSI>; +}; + +&rng1 { + clocks = <&scmi_clk CK_SCMI_RNG1>; + resets = <&scmi_reset RST_SCMI_RNG1>; +}; + +&rtc { + clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>; +}; + +&scmi_reguls { + scmi_vddcore: regulator@3 { + reg = <VOLTD_SCMI_STPMIC1_BUCK1>; + regulator-name = "vddcore"; + }; + + scmi_vdd: regulator@5 { + reg = <VOLTD_SCMI_STPMIC1_BUCK3>; + regulator-name = "vdd"; + }; + + scmi_v3v3: regulator@6 { + reg = <VOLTD_SCMI_STPMIC1_BUCK4>; + regulator-name = "v3v3"; + }; + + scmi_v1v8_audio: regulator@7 { + reg = <VOLTD_SCMI_STPMIC1_LDO1>; + regulator-name = "v1v8_audio"; + }; + + scmi_v3v3_hdmi: regulator@8 { + reg = <VOLTD_SCMI_STPMIC1_LDO2>; + regulator-name = "v3v3_hdmi"; + }; + + scmi_vdd_usb: regulator@a { + reg = <VOLTD_SCMI_STPMIC1_LDO4>; + regulator-name = "vdd_usb"; + }; + + scmi_vdda: regulator@b { + reg = <VOLTD_SCMI_STPMIC1_LDO5>; + regulator-name = "vdda"; + }; + + scmi_v1v2_hdmi: regulator@c { + reg = <VOLTD_SCMI_STPMIC1_LDO6>; + regulator-name = "v1v2_hdmi"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + scmi_vbus_otg: regulator@f { + reg = <VOLTD_SCMI_STPMIC1_PWR_SW1>; + regulator-name = "vbus_otg"; + }; + + scmi_vbus_sw: regulator@10 { + reg = <VOLTD_SCMI_STPMIC1_PWR_SW2>; + regulator-name = "vbus_sw"; + }; +}; + +&sdmmc1 { + vmmc-supply = <&scmi_v3v3>; +}; + +&sdmmc3 { + vmmc-supply = <&scmi_v3v3>; +}; + +&usbh_ehci { + hub@1 { + vdd-supply = <&scmi_v3v3>; + }; +}; + +&usbphyc_port0 { + phy-supply = <&scmi_vdd_usb>; +}; + +&usbphyc_port1 { + phy-supply = <&scmi_vdd_usb>; +}; + +&vrefbuf { + vdda-supply = <&scmi_vdd>; +}; diff --git a/arch/arm/boot/dts/st/stm32mp157f-dk2.dts b/arch/arm/boot/dts/st/stm32mp157f-dk2.dts new file mode 100644 index 000000000000..43375c4d62a3 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp157f-dk2.dts @@ -0,0 +1,179 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2025 - All Rights Reserved + * Author: Amelie Delaunay <amelie.delaunay@foss.st.com> for STMicroelectronics. + */ + +/dts-v1/; + +#include "stm32mp157.dtsi" +#include "stm32mp15xf.dtsi" +#include "stm32mp15-pinctrl.dtsi" +#include "stm32mp15xxac-pinctrl.dtsi" +#include "stm32mp15xx-dkx.dtsi" +#include "stm32mp157f-dk2-scmi.dtsi" + +/ { + model = "STMicroelectronics STM32MP157F-DK2 Discovery Board"; + compatible = "st,stm32mp157f-dk2", "st,stm32mp157"; + + aliases { + ethernet0 = ðernet0; + serial3 = &usart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpioh 4 GPIO_ACTIVE_LOW>; + }; +}; + +&arm_wdt { + timeout-sec = <32>; + status = "okay"; +}; + +&cryp1 { + status = "okay"; +}; + +&dsi { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + panel@0 { + compatible = "orisetech,otm8009a"; + reg = <0>; + reset-gpios = <&gpioe 4 GPIO_ACTIVE_LOW>; + power-supply = <&scmi_v3v3>; + status = "okay"; + + port { + panel_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + }; +}; + +&dsi_in { + remote-endpoint = <<dc_ep1_out>; +}; + +&dsi_out { + remote-endpoint = <&panel_in>; +}; + +&i2c1 { + touchscreen@38 { + compatible = "focaltech,ft6236"; + reg = <0x38>; + interrupts = <2 IRQ_TYPE_EDGE_FALLING>; + interrupt-parent = <&gpiof>; + touchscreen-size-x = <480>; + touchscreen-size-y = <800>; + status = "okay"; + }; +}; + +/* I2C4 is managed by OP-TEE */ +&i2c4 { + status = "disabled"; + + /* i2c4 subnodes, which won't be managed by Linux */ + typec@28 { + status = "disabled"; + connector { + status = "disabled"; + }; + }; + + stpmic@33 { + status = "disabled"; + }; +}; + +<dc { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + ltdc_ep1_out: endpoint@1 { + reg = <1>; + remote-endpoint = <&dsi_in>; + }; + }; +}; + +&rtc { + pinctrl-names = "default"; + pinctrl-0 = <&rtc_rsvd_pins_a>; + + rtc_lsco_pins_a: rtc-lsco-0 { + pins = "out2_rmp"; + function = "lsco"; + }; +}; + +/* Wifi */ +&sdmmc2 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc2_b4_pins_a>; + pinctrl-1 = <&sdmmc2_b4_od_pins_a>; + pinctrl-2 = <&sdmmc2_b4_sleep_pins_a>; + non-removable; + cap-sdio-irq; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&scmi_v3v3>; + mmc-pwrseq = <&wifi_pwrseq>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + pinctrl-names = "default"; + pinctrl-0 = <&rtc_lsco_pins_a>; + }; +}; + +/* Bluetooth */ +&usart2 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&usart2_pins_c>; + pinctrl-1 = <&usart2_sleep_pins_c>; + pinctrl-2 = <&usart2_idle_pins_c>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + shutdown-gpios = <&gpioz 6 GPIO_ACTIVE_HIGH>; + compatible = "brcm,bcm43438-bt"; + max-speed = <3000000>; + vbat-supply = <&scmi_v3v3>; + vddio-supply = <&scmi_v3v3>; + }; +}; + +/* Since I2C4 is disabled, STUSB1600 is also disabled so there is no Type-C support */ +&usbotg_hs { + dr_mode = "peripheral"; + role-switch-default-mode = "peripheral"; + /* + * Forcing dr_mode = "peripheral"/"role-switch-default-mode = "peripheral"; + * will cause the pull-up on D+/D- to be raised as soon as the OTG is configured at runtime, + * regardless of the presence of VBUS. Notice that on self-powered devices like + * stm32mp157f-dk2, this isn't compliant with the USB standard. That's why usbotg_hs is kept + * disabled here. + */ + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/st/stm32mp15xf.dtsi b/arch/arm/boot/dts/st/stm32mp15xf.dtsi new file mode 100644 index 000000000000..ffa55d64bea3 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp15xf.dtsi @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2025 - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. + */ + +&etzpc { + cryp1: cryp@54001000 { + compatible = "st,stm32mp1-cryp"; + reg = <0x54001000 0x400>; + interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc CRYP1>; + resets = <&rcc CRYP1_R>; + access-controllers = <&etzpc 9>; + status = "disabled"; + }; +}; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcor-avenger96.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-dhcor-avenger96.dtsi index 343a4613dfca..aceeff6c38ba 100644 --- a/arch/arm/boot/dts/st/stm32mp15xx-dhcor-avenger96.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcor-avenger96.dtsi @@ -435,7 +435,7 @@ #address-cells = <1>; #size-cells = <0>; - brcmf: bcrmf@1 { + brcmf: wifi@1 { reg = <1>; compatible = "brcm,bcm4329-fmac"; }; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi index a5511b1f0ce3..46692d8f566a 100644 --- a/arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi @@ -254,7 +254,7 @@ /delete-property/dmas; /delete-property/dma-names; - stusb1600@28 { + stusb1600: typec@28 { compatible = "st,stusb1600"; reg = <0x28>; interrupts = <11 IRQ_TYPE_LEVEL_LOW>; @@ -515,6 +515,7 @@ remote-endpoint = <&cs42l51_tx_endpoint>; dai-format = "i2s"; mclk-fs = <256>; + system-clock-direction-out; dai-tdm-slot-num = <2>; dai-tdm-slot-width = <32>; }; |