diff options
Diffstat (limited to 'arch/arm64/boot/dts/arm/fvp-base-revc.dts')
| -rw-r--r-- | arch/arm64/boot/dts/arm/fvp-base-revc.dts | 101 |
1 files changed, 100 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/arm/fvp-base-revc.dts b/arch/arm64/boot/dts/arm/fvp-base-revc.dts index 9e10d7a6b5a2..68a69f17e93d 100644 --- a/arch/arm64/boot/dts/arm/fvp-base-revc.dts +++ b/arch/arm64/boot/dts/arm/fvp-base-revc.dts @@ -44,6 +44,30 @@ #address-cells = <2>; #size-cells = <0>; + idle-states { + entry-method = "psci"; + + CPU_SLEEP_0: cpu-sleep-0 { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x0010000>; + entry-latency-us = <40>; + exit-latency-us = <100>; + min-residency-us = <150>; + status = "disabled"; + }; + + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x1010000>; + entry-latency-us = <500>; + exit-latency-us = <1000>; + min-residency-us = <2500>; + status = "disabled"; + }; + }; + cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,armv8"; @@ -56,6 +80,7 @@ d-cache-line-size = <64>; d-cache-sets = <256>; next-level-cache = <&C0_L2>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; cpu1: cpu@100 { device_type = "cpu"; @@ -69,6 +94,7 @@ d-cache-line-size = <64>; d-cache-sets = <256>; next-level-cache = <&C0_L2>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; cpu2: cpu@200 { device_type = "cpu"; @@ -82,6 +108,7 @@ d-cache-line-size = <64>; d-cache-sets = <256>; next-level-cache = <&C0_L2>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; cpu3: cpu@300 { device_type = "cpu"; @@ -95,6 +122,7 @@ d-cache-line-size = <64>; d-cache-sets = <256>; next-level-cache = <&C0_L2>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; cpu4: cpu@10000 { device_type = "cpu"; @@ -108,6 +136,7 @@ d-cache-line-size = <64>; d-cache-sets = <256>; next-level-cache = <&C1_L2>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; cpu5: cpu@10100 { device_type = "cpu"; @@ -121,6 +150,7 @@ d-cache-line-size = <64>; d-cache-sets = <256>; next-level-cache = <&C1_L2>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; cpu6: cpu@10200 { device_type = "cpu"; @@ -134,6 +164,7 @@ d-cache-line-size = <64>; d-cache-sets = <256>; next-level-cache = <&C1_L2>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; cpu7: cpu@10300 { device_type = "cpu"; @@ -147,6 +178,7 @@ d-cache-line-size = <64>; d-cache-sets = <256>; next-level-cache = <&C1_L2>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; C0_L2: l2-cache0 { compatible = "cache"; @@ -169,7 +201,7 @@ memory@80000000 { device_type = "memory"; - reg = <0x00000000 0x80000000 0 0x80000000>, + reg = <0x00000000 0x80000000 0 0x7c000000>, <0x00000008 0x80000000 0 0x80000000>; }; @@ -217,6 +249,19 @@ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; }; + timer@2a810000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x0 0x2a810000 0x0 0x10000>; + ranges = <0 0x0 0x2a820000 0x20000>; + #address-cells = <1>; + #size-cells = <1>; + frame@2a830000 { + frame-number = <1>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x10000 0x10000>; + }; + }; + pmu { compatible = "arm,armv8-pmuv3"; interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; @@ -227,6 +272,60 @@ interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; }; + ete-0 { + compatible = "arm,embedded-trace-extension"; + cpu = <&cpu0>; + status = "disabled"; + }; + + ete-1 { + compatible = "arm,embedded-trace-extension"; + cpu = <&cpu1>; + status = "disabled"; + }; + + ete-2 { + compatible = "arm,embedded-trace-extension"; + cpu = <&cpu2>; + status = "disabled"; + }; + + ete-3 { + compatible = "arm,embedded-trace-extension"; + cpu = <&cpu3>; + status = "disabled"; + }; + + ete-4 { + compatible = "arm,embedded-trace-extension"; + cpu = <&cpu4>; + status = "disabled"; + }; + + ete-5 { + compatible = "arm,embedded-trace-extension"; + cpu = <&cpu5>; + status = "disabled"; + }; + + ete-6 { + compatible = "arm,embedded-trace-extension"; + cpu = <&cpu6>; + status = "disabled"; + }; + + ete-7 { + compatible = "arm,embedded-trace-extension"; + cpu = <&cpu7>; + status = "disabled"; + }; + + trbe { + compatible = "arm,trace-buffer-extension"; + interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_LOW>; + status = "disabled"; + }; + pci: pci@40000000 { #address-cells = <0x3>; #size-cells = <0x2>; |