diff options
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx95.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx95.dtsi | 69 |
1 files changed, 62 insertions, 7 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi index 632631a29112..4ca6a7ea586e 100644 --- a/arch/arm64/boot/dts/freescale/imx95.dtsi +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi @@ -3,6 +3,7 @@ * Copyright 2024 NXP */ +#include <dt-bindings/clock/nxp,imx95-clock.h> #include <dt-bindings/dma/fsl-edma.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> @@ -688,15 +689,14 @@ }; i3c2: i3c@42520000 { - compatible = "silvaco,i3c-master-v1"; + compatible = "nxp,imx95-i3c", "silvaco,i3c-master-v1"; reg = <0x42520000 0x10000>; interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <3>; #size-cells = <0>; clocks = <&scmi_clk IMX95_CLK_BUSAON>, - <&scmi_clk IMX95_CLK_I3C2>, <&scmi_clk IMX95_CLK_I3C2SLOW>; - clock-names = "pclk", "fast_clk", "slow_clk"; + clock-names = "pclk", "fast_clk"; status = "disabled"; }; @@ -1152,6 +1152,7 @@ <&scmi_clk IMX95_CLK_BUSWAKEUP>; clock-names = "gpio", "port"; gpio-ranges = <&scmi_iomuxc 0 4 32>; + ngpios = <32>; }; gpio3: gpio@43820000 { @@ -1168,6 +1169,7 @@ clock-names = "gpio", "port"; gpio-ranges = <&scmi_iomuxc 0 104 8>, <&scmi_iomuxc 8 74 18>, <&scmi_iomuxc 26 42 2>, <&scmi_iomuxc 28 0 4>; + ngpios = <32>; }; gpio4: gpio@43840000 { @@ -1183,6 +1185,7 @@ <&scmi_clk IMX95_CLK_BUSWAKEUP>; clock-names = "gpio", "port"; gpio-ranges = <&scmi_iomuxc 0 46 28>, <&scmi_iomuxc 28 44 2>; + ngpios = <30>; }; gpio5: gpio@43850000 { @@ -1198,6 +1201,7 @@ <&scmi_clk IMX95_CLK_BUSWAKEUP>; clock-names = "gpio", "port"; gpio-ranges = <&scmi_iomuxc 0 92 12>, <&scmi_iomuxc 12 36 6>; + ngpios = <18>; }; aips1: bus@44000000 { @@ -1273,15 +1277,14 @@ }; i3c1: i3c@44330000 { - compatible = "silvaco,i3c-master-v1"; + compatible = "nxp,imx95-i3c", "silvaco,i3c-master-v1"; reg = <0x44330000 0x10000>; interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <3>; #size-cells = <0>; clocks = <&scmi_clk IMX95_CLK_BUSAON>, - <&scmi_clk IMX95_CLK_I3C1>, <&scmi_clk IMX95_CLK_I3C1SLOW>; - clock-names = "pclk", "fast_clk", "slow_clk"; + clock-names = "pclk", "fast_clk"; status = "disabled"; }; @@ -1508,6 +1511,7 @@ <&scmi_clk IMX95_CLK_M33>; clock-names = "gpio", "port"; gpio-ranges = <&scmi_iomuxc 0 112 16>; + ngpios = <16>; status = "disabled"; }; @@ -1708,7 +1712,7 @@ <0x9 0 1 0>; reg-names = "dbi","atu", "dbi2", "app", "dma", "addr_space"; num-lanes = <1>; - interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "dma"; clocks = <&scmi_clk IMX95_CLK_HSIO>, <&scmi_clk IMX95_CLK_HSIOPLL>, @@ -1801,6 +1805,49 @@ status = "disabled"; }; + vpu_blk_ctrl: clock-controller@4c410000 { + compatible = "nxp,imx95-vpu-csr", "syscon"; + reg = <0x0 0x4c410000 0x0 0x10000>; + #clock-cells = <1>; + clocks = <&scmi_clk IMX95_CLK_VPUAPB>; + power-domains = <&scmi_devpd IMX95_PD_VPU>; + assigned-clocks = <&scmi_clk IMX95_CLK_VPUAPB>, + <&scmi_clk IMX95_CLK_VPU>, + <&scmi_clk IMX95_CLK_VPUJPEG>; + assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>, + <&scmi_clk IMX95_CLK_SYSPLL1_PFD2>, + <&scmi_clk IMX95_CLK_SYSPLL1_PFD0>; + assigned-clock-rates = <133333333>, <667000000>, <500000000>; + }; + + jpegdec: jpegdec@4c500000 { + compatible = "nxp,imx95-jpgdec", "nxp,imx8qxp-jpgdec"; + reg = <0x0 0x4C500000 0x0 0x00050000>; + interrupts = <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&scmi_clk IMX95_CLK_VPU>, + <&vpu_blk_ctrl IMX95_CLK_VPUBLK_JPEG_DEC>; + assigned-clocks = <&vpu_blk_ctrl IMX95_CLK_VPUBLK_JPEG_DEC>; + assigned-clock-parents = <&scmi_clk IMX95_CLK_VPUJPEG>; + power-domains = <&scmi_devpd IMX95_PD_VPU>; + }; + + jpegenc: jpegenc@4c550000 { + compatible = "nxp,imx95-jpgenc", "nxp,imx8qxp-jpgenc"; + reg = <0x0 0x4C550000 0x0 0x00050000>; + interrupts = <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&scmi_clk IMX95_CLK_VPU>, + <&vpu_blk_ctrl IMX95_CLK_VPUBLK_JPEG_ENC>; + assigned-clocks = <&vpu_blk_ctrl IMX95_CLK_VPUBLK_JPEG_DEC>; + assigned-clock-parents = <&scmi_clk IMX95_CLK_VPUJPEG>; + power-domains = <&scmi_devpd IMX95_PD_VPU>; + }; + netcmix_blk_ctrl: syscon@4c810000 { compatible = "nxp,imx95-netcmix-blk-ctrl", "syscon"; reg = <0x0 0x4c810000 0x0 0x8>; @@ -1861,6 +1908,14 @@ <0x90 &its 0x65 0x1>, //ENETC2 VF0 <0xa0 &its 0x66 0x1>, //ENETC2 VF1 <0xc0 &its 0x67 0x1>; //NETC Timer + iommu-map = <0x0 &smmu 0x20 0x1>, + <0x10 &smmu 0x21 0x1>, + <0x20 &smmu 0x22 0x1>, + <0x40 &smmu 0x23 0x1>, + <0x80 &smmu 0x24 0x1>, + <0x90 &smmu 0x25 0x1>, + <0xa0 &smmu 0x26 0x1>, + <0xc0 &smmu 0x27 0x1>; /* ENETC0~2 and Timer BAR0 - non-prefetchable memory */ ranges = <0x82000000 0x0 0x4cc00000 0x0 0x4cc00000 0x0 0xe0000 /* Timer BAR2 - prefetchable memory */ |