summaryrefslogtreecommitdiff
path: root/arch/arm64/boot/dts/qcom/sm6115.dtsi
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm64/boot/dts/qcom/sm6115.dtsi')
-rw-r--r--arch/arm64/boot/dts/qcom/sm6115.dtsi10
1 files changed, 6 insertions, 4 deletions
diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi
index 94c081bf7a89..c8865779173e 100644
--- a/arch/arm64/boot/dts/qcom/sm6115.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi
@@ -3,6 +3,7 @@
* Copyright (c) 2021, Iskren Chernev <iskren.chernev@gmail.com>
*/
+#include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
#include <dt-bindings/clock/qcom,gcc-sm6115.h>
#include <dt-bindings/clock/qcom,sm6115-dispcc.h>
#include <dt-bindings/clock/qcom,sm6115-gpucc.h>
@@ -1873,7 +1874,7 @@
mdp: display-controller@5e01000 {
compatible = "qcom,sm6115-dpu";
reg = <0x0 0x05e01000 0x0 0x8f000>,
- <0x0 0x05eb0000 0x0 0x2008>;
+ <0x0 0x05eb0000 0x0 0x3000>;
reg-names = "mdp", "vbif";
clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
@@ -1960,7 +1961,8 @@
assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
<&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
- assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
+ assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
+ <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>;
operating-points-v2 = <&dsi_opp_table>;
power-domains = <&rpmpd SM6115_VDDCX>;
@@ -2034,8 +2036,8 @@
reg = <0x0 0x05f00000 0 0x20000>;
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
<&sleep_clk>,
- <&mdss_dsi0_phy 0>,
- <&mdss_dsi0_phy 1>,
+ <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
+ <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>,
<&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>;
#clock-cells = <1>;
#reset-cells = <1>;