diff options
Diffstat (limited to 'arch/arm64/boot/dts/ti/k3-am62a7-sk.dts')
| -rw-r--r-- | arch/arm64/boot/dts/ti/k3-am62a7-sk.dts | 212 |
1 files changed, 203 insertions, 9 deletions
diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts index 1c9d95696c83..bceead5e288e 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts @@ -36,6 +36,7 @@ /* 4G RAM */ reg = <0x00000000 0x80000000 0x00000000 0x80000000>, <0x00000008 0x80000000 0x00000000 0x80000000>; + bootph-all; }; reserved-memory { @@ -52,6 +53,42 @@ linux,cma-default; }; + c7x_0_dma_memory_region: c7x-dma-memory@99800000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x99800000 0x00 0x100000>; + no-map; + }; + + c7x_0_memory_region: c7x-memory@99900000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x99900000 0x00 0xf00000>; + no-map; + }; + + mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@9b800000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9b800000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core0_memory_region: r5f-dma-memory@9b900000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9b900000 0x00 0xf00000>; + no-map; + }; + + wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9c800000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9c800000 0x00 0x100000>; + no-map; + }; + + wkup_r5fss0_core0_memory_region: r5f-dma-memory@9c900000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9c900000 0x00 0xf00000>; + no-map; + }; + secure_tfa_ddr: tfa@9e780000 { reg = <0x00 0x9e780000 0x00 0x80000>; alignment = <0x1000>; @@ -63,12 +100,6 @@ alignment = <0x1000>; no-map; }; - - wkup_r5fss0_core0_memory_region: r5f-dma-memory@9c900000 { - compatible = "shared-dma-pool"; - reg = <0x00 0x9c900000 0x00 0x01e00000>; - no-map; - }; }; opp-table { @@ -121,6 +152,7 @@ regulator-boot-on; enable-active-high; gpio = <&exp1 3 GPIO_ACTIVE_HIGH>; + bootph-all; }; vcc_3v3_sys: regulator-4 { @@ -267,12 +299,13 @@ AM62AX_IOPAD(0x1c8, PIN_INPUT, 0) /* (E14) UART0_RXD */ AM62AX_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (D15) UART0_TXD */ >; + bootph-all; }; main_uart1_pins_default: main-uart1-default-pins { pinctrl-single,pins = < - AM62AX_IOPAD(0x01e8, PIN_INPUT, 1) /* (C17) I2C1_SCL.UART1_RXD */ - AM62AX_IOPAD(0x01ec, PIN_OUTPUT, 1) /* (E17) I2C1_SDA.UART1_TXD */ + AM62AX_IOPAD(0x01ac, PIN_INPUT, 2) /* (B21) MCASP0_AFSR.UART1_RXD */ + AM62AX_IOPAD(0x01b0, PIN_OUTPUT, 2) /* (A21) MCASP0_ACLKR.UART1_TXD */ AM62AX_IOPAD(0x0194, PIN_INPUT, 2) /* (C19) MCASP0_AXR3.UART1_CTSn */ AM62AX_IOPAD(0x0198, PIN_OUTPUT, 2) /* (B19) MCASP0_AXR2.UART1_RTSn */ >; @@ -290,6 +323,7 @@ AM62AX_IOPAD(0x1e8, PIN_INPUT_PULLUP, 0) /* (B17) I2C1_SCL */ AM62AX_IOPAD(0x1ec, PIN_INPUT_PULLUP, 0) /* (A17) I2C1_SDA */ >; + bootph-all; }; main_i2c2_pins_default: main-i2c2-default-pins { @@ -313,6 +347,7 @@ AM62AX_IOPAD(0x1fc, PIN_INPUT_PULLUP, 0) /* (AD2) MMC0_DAT6 */ AM62AX_IOPAD(0x1f8, PIN_INPUT_PULLUP, 0) /* (AC2) MMC0_DAT7 */ >; + bootph-all; }; main_mmc1_pins_default: main-mmc1-default-pins { @@ -325,6 +360,7 @@ AM62AX_IOPAD(0x224, PIN_INPUT, 0) /* (D22) MMC1_DAT3 */ AM62AX_IOPAD(0x240, PIN_INPUT, 0) /* (D17) MMC1_SDCD */ >; + bootph-all; }; usr_led_pins_default: usr-led-default-pins { @@ -344,6 +380,7 @@ AM62AX_IOPAD(0x160, PIN_OUTPUT, 0) /* (V12) MDIO0_MDC */ AM62AX_IOPAD(0x15c, PIN_INPUT, 0) /* (V13) MDIO0_MDIO */ >; + bootph-all; }; main_rgmii1_pins_default: main-rgmii1-default-pins { @@ -361,6 +398,7 @@ AM62AX_IOPAD(0x130, PIN_INPUT, 0) /* (AB17) RGMII1_TXC */ AM62AX_IOPAD(0x12c, PIN_INPUT, 0) /* (W16) RGMII1_TX_CTL */ >; + bootph-all; }; main_mcasp1_pins_default: main-mcasp1-default-pins { @@ -383,6 +421,25 @@ AM62AX_IOPAD(0x07c, PIN_OUTPUT, 7) /* (M19) GPMC0_CLK.GPIO0_31 */ >; }; + + main_ecap0_pins_default: main-ecap0-default-pins { + pinctrl-single,pins = < + AM62AX_IOPAD(0x01b8, PIN_OUTPUT, 3) /* (C16) SPI0_CS1.ECAP0_IN_APWM_OUT */ + >; + }; + + main_ecap2_pins_default: main-ecap2-default-pins { + pinctrl-single,pins = < + AM62AX_IOPAD(0x01a4, PIN_OUTPUT, 2) /* (A19) MCASP0_ACLKX.ECAP2_IN_APWM_OUT */ + >; + }; + + main_epwm1_pins_default: main-epwm1-default-pins { + pinctrl-single,pins = < + AM62AX_IOPAD(0x019c, PIN_OUTPUT, 6) /* (B18) MCASP0_AXR1.EHRPWM1_A */ + AM62AX_IOPAD(0x01a0, PIN_OUTPUT, 6) /* (B20) MCASP0_AXR0.EHRPWM1_B */ + >; + }; }; &mcu_pmx0 { @@ -522,6 +579,7 @@ #interrupt-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&main_gpio1_ioexp_intr_pins_default>; + bootph-all; gpio-line-names = "GPIO_CPSW2_RST", "GPIO_CPSW1_RST", "BT_EN_SOC", "MMC1_SD_EN", @@ -614,7 +672,7 @@ non-removable; pinctrl-names = "default"; pinctrl-0 = <&main_mmc0_pins_default>; - disable-wp; + bootph-all; }; &sdhci1 { @@ -625,10 +683,12 @@ pinctrl-names = "default"; pinctrl-0 = <&main_mmc1_pins_default>; disable-wp; + bootph-all; }; &main_gpio0 { status = "okay"; + bootph-all; }; &main_gpio1 { @@ -643,6 +703,7 @@ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_uart0_pins_default>; + bootph-all; }; /* Main UART1 is used for TIFS firmware logs */ @@ -652,6 +713,11 @@ status = "reserved"; }; +/* main_timer2 is used by C7x DSP */ +&main_timer2 { + status = "reserved"; +}; + &usbss0 { status = "okay"; ti,vbus-divider; @@ -684,10 +750,15 @@ pinctrl-0 = <&main_rgmii1_pins_default>; }; +&phy_gmii_sel { + bootph-all; +}; + &cpsw_port1 { status = "okay"; phy-mode = "rgmii-rxid"; phy-handle = <&cpsw3g_phy0>; + bootph-all; }; &cpsw_port2 { @@ -704,6 +775,7 @@ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; ti,min-output-impedance; + bootph-all; }; }; @@ -741,3 +813,125 @@ }; }; }; + +&ecap0 { + /* P26 of J3 */ + pinctrl-names = "default"; + pinctrl-0 = <&main_ecap0_pins_default>; + status = "okay"; +}; + +&ecap2 { + /* P11 of J3 */ + pinctrl-names = "default"; + pinctrl-0 = <&main_ecap2_pins_default>; + status = "okay"; +}; + +&epwm1 { + /* P36/P33 of J3 */ + pinctrl-names = "default"; + pinctrl-0 = <&main_epwm1_pins_default>; + status = "okay"; +}; + +&mailbox0_cluster0 { + status = "okay"; + + mbox_r5_0: mbox-r5-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; +}; + +&mailbox0_cluster1 { + status = "okay"; + + mbox_c7x_0: mbox-c7x-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; +}; + +&mailbox0_cluster2 { + status = "okay"; + + mbox_mcu_r5_0: mbox-mcu-r5-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; +}; + +&wkup_r5fss0 { + status = "okay"; +}; + +&wkup_r5fss0_core0 { + mboxes = <&mailbox0_cluster0>, <&mbox_r5_0>; + memory-region = <&wkup_r5fss0_core0_dma_memory_region>, + <&wkup_r5fss0_core0_memory_region>; +}; + +&mcu_r5fss0 { + status = "okay"; +}; + +&mcu_r5fss0_core0 { + mboxes = <&mailbox0_cluster2>, <&mbox_mcu_r5_0>; + memory-region = <&mcu_r5fss0_core0_dma_memory_region>, + <&mcu_r5fss0_core0_memory_region>; +}; + +&c7x_0 { + mboxes = <&mailbox0_cluster1>, <&mbox_c7x_0>; + memory-region = <&c7x_0_dma_memory_region>, + <&c7x_0_memory_region>; + status = "okay"; +}; + +/* main_rti4 is used by C7x DSP */ +&main_rti4 { + status = "reserved"; +}; + +&fss { + status = "okay"; +}; + +&ospi0 { + pinctrl-names = "default"; + pinctrl-0 = <&ospi0_pins_default>; + + flash@0 { + compatible = "spi-nand"; + reg = <0>; + spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; + spi-max-frequency = <25000000>; + cdns,tshsl-ns = <60>; + cdns,tsd2d-ns = <60>; + cdns,tchsh-ns = <60>; + cdns,tslch-ns = <60>; + cdns,read-delay = <2>; + bootph-all; + }; +}; + +&main_pmx0 { + ospi0_pins_default: ospi0-default-pins { + bootph-all; + pinctrl-single,pins = < + AM62AX_IOPAD(0x000, PIN_OUTPUT, 0) /* (H24) OSPI0_CLK */ + AM62AX_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F23) OSPI0_CSn0 */ + AM62AX_IOPAD(0x00c, PIN_INPUT, 0) /* (E25) OSPI0_D0 */ + AM62AX_IOPAD(0x010, PIN_INPUT, 0) /* (G24) OSPI0_D1 */ + AM62AX_IOPAD(0x014, PIN_INPUT, 0) /* (F25) OSPI0_D2 */ + AM62AX_IOPAD(0x018, PIN_INPUT, 0) /* (F24) OSPI0_D3 */ + AM62AX_IOPAD(0x01c, PIN_INPUT, 0) /* (J23) OSPI0_D4 */ + AM62AX_IOPAD(0x020, PIN_INPUT, 0) /* (J25) OSPI0_D5 */ + AM62AX_IOPAD(0x024, PIN_INPUT, 0) /* (H25) OSPI0_D6 */ + AM62AX_IOPAD(0x028, PIN_INPUT, 0) /* (J22) OSPI0_D7 */ + AM62AX_IOPAD(0x008, PIN_INPUT, 0) /* (J24) OSPI0_DQS */ + >; + }; +}; |