diff options
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn35')
21 files changed, 0 insertions, 4732 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/Makefile b/drivers/gpu/drm/amd/display/dc/dcn35/Makefile deleted file mode 100644 index 0e317e0c36a0..000000000000 --- a/drivers/gpu/drm/amd/display/dc/dcn35/Makefile +++ /dev/null @@ -1,20 +0,0 @@ -# -# (c) Copyright 2022 Advanced Micro Devices, Inc. All the rights reserved -# -# All rights reserved. This notice is intended as a precaution against -# inadvertent publication and does not imply publication or any waiver -# of confidentiality. The year included in the foregoing notice is the -# year of creation of the work. -# -# Authors: AMD -# -# Makefile for DCN35. - -DCN35 = dcn35_dio_stream_encoder.o \ - dcn35_dio_link_encoder.o dcn35_dccg.o \ - dcn35_hubp.o dcn35_hubbub.o \ - dcn35_mmhubbub.o dcn35_opp.o dcn35_dpp.o dcn35_pg_cntl.o dcn35_dwb.o - -AMD_DAL_DCN35 = $(addprefix $(AMDDALPATH)/dc/dcn35/,$(DCN35)) - -AMD_DISPLAY_FILES += $(AMD_DAL_DCN35) diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dccg.c b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dccg.c deleted file mode 100644 index f1ba7bb792ea..000000000000 --- a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dccg.c +++ /dev/null @@ -1,893 +0,0 @@ -/* SPDX-License-Identifier: MIT */ -/* - * Copyright 2023 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#include "reg_helper.h" -#include "core_types.h" -#include "dcn35_dccg.h" - -#define TO_DCN_DCCG(dccg)\ - container_of(dccg, struct dcn_dccg, base) - -#define REG(reg) \ - (dccg_dcn->regs->reg) - -#undef FN -#define FN(reg_name, field_name) \ - dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name - -#define CTX \ - dccg_dcn->base.ctx -#define DC_LOGGER \ - dccg->ctx->logger - -static void dcn35_set_dppclk_enable(struct dccg *dccg, - uint32_t dpp_inst, uint32_t enable) -{ - struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); - - switch (dpp_inst) { - case 0: - REG_UPDATE(DPPCLK_CTRL, DPPCLK0_EN, enable); - break; - case 1: - REG_UPDATE(DPPCLK_CTRL, DPPCLK1_EN, enable); - break; - case 2: - REG_UPDATE(DPPCLK_CTRL, DPPCLK2_EN, enable); - break; - case 3: - REG_UPDATE(DPPCLK_CTRL, DPPCLK3_EN, enable); - break; - default: - break; - } - -} - -static void dccg35_update_dpp_dto(struct dccg *dccg, int dpp_inst, - int req_dppclk) -{ - struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); - - if (dccg->dpp_clock_gated[dpp_inst]) { - /* - * Do not update the DPPCLK DTO if the clock is stopped. - */ - return; - } - - if (dccg->ref_dppclk && req_dppclk) { - int ref_dppclk = dccg->ref_dppclk; - int modulo, phase; - - // phase / modulo = dpp pipe clk / dpp global clk - modulo = 0xff; // use FF at the end - phase = ((modulo * req_dppclk) + ref_dppclk - 1) / ref_dppclk; - - if (phase > 0xff) { - ASSERT(false); - phase = 0xff; - } - - REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0, - DPPCLK0_DTO_PHASE, phase, - DPPCLK0_DTO_MODULO, modulo); - - dcn35_set_dppclk_enable(dccg, dpp_inst, true); - } else - dcn35_set_dppclk_enable(dccg, dpp_inst, false); - dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk; -} - -static void dccg35_get_pixel_rate_div( - struct dccg *dccg, - uint32_t otg_inst, - enum pixel_rate_div *k1, - enum pixel_rate_div *k2) -{ - struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); - uint32_t val_k1 = PIXEL_RATE_DIV_NA, val_k2 = PIXEL_RATE_DIV_NA; - - *k1 = PIXEL_RATE_DIV_NA; - *k2 = PIXEL_RATE_DIV_NA; - - switch (otg_inst) { - case 0: - REG_GET_2(OTG_PIXEL_RATE_DIV, - OTG0_PIXEL_RATE_DIVK1, &val_k1, - OTG0_PIXEL_RATE_DIVK2, &val_k2); - break; - case 1: - REG_GET_2(OTG_PIXEL_RATE_DIV, - OTG1_PIXEL_RATE_DIVK1, &val_k1, - OTG1_PIXEL_RATE_DIVK2, &val_k2); - break; - case 2: - REG_GET_2(OTG_PIXEL_RATE_DIV, - OTG2_PIXEL_RATE_DIVK1, &val_k1, - OTG2_PIXEL_RATE_DIVK2, &val_k2); - break; - case 3: - REG_GET_2(OTG_PIXEL_RATE_DIV, - OTG3_PIXEL_RATE_DIVK1, &val_k1, - OTG3_PIXEL_RATE_DIVK2, &val_k2); - break; - default: - BREAK_TO_DEBUGGER(); - return; - } - - *k1 = (enum pixel_rate_div)val_k1; - *k2 = (enum pixel_rate_div)val_k2; -} - -static void dccg35_set_pixel_rate_div( - struct dccg *dccg, - uint32_t otg_inst, - enum pixel_rate_div k1, - enum pixel_rate_div k2) -{ - struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); - enum pixel_rate_div cur_k1 = PIXEL_RATE_DIV_NA, cur_k2 = PIXEL_RATE_DIV_NA; - - // Don't program 0xF into the register field. Not valid since - // K1 / K2 field is only 1 / 2 bits wide - if (k1 == PIXEL_RATE_DIV_NA || k2 == PIXEL_RATE_DIV_NA) { - BREAK_TO_DEBUGGER(); - return; - } - - dccg35_get_pixel_rate_div(dccg, otg_inst, &cur_k1, &cur_k2); - if (k1 == cur_k1 && k2 == cur_k2) - return; - - switch (otg_inst) { - case 0: - REG_UPDATE_2(OTG_PIXEL_RATE_DIV, - OTG0_PIXEL_RATE_DIVK1, k1, - OTG0_PIXEL_RATE_DIVK2, k2); - break; - case 1: - REG_UPDATE_2(OTG_PIXEL_RATE_DIV, - OTG1_PIXEL_RATE_DIVK1, k1, - OTG1_PIXEL_RATE_DIVK2, k2); - break; - case 2: - REG_UPDATE_2(OTG_PIXEL_RATE_DIV, - OTG2_PIXEL_RATE_DIVK1, k1, - OTG2_PIXEL_RATE_DIVK2, k2); - break; - case 3: - REG_UPDATE_2(OTG_PIXEL_RATE_DIV, - OTG3_PIXEL_RATE_DIVK1, k1, - OTG3_PIXEL_RATE_DIVK2, k2); - break; - default: - BREAK_TO_DEBUGGER(); - return; - } -} - -static void dccg35_set_dtbclk_p_src( - struct dccg *dccg, - enum streamclk_source src, - uint32_t otg_inst) -{ - struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); - - uint32_t p_src_sel = 0; /* selects dprefclk */ - if (src == DTBCLK0) - p_src_sel = 2; /* selects dtbclk0 */ - - switch (otg_inst) { - case 0: - if (src == REFCLK) - REG_UPDATE(DTBCLK_P_CNTL, - DTBCLK_P0_EN, 0); - else - REG_UPDATE_2(DTBCLK_P_CNTL, - DTBCLK_P0_SRC_SEL, p_src_sel, - DTBCLK_P0_EN, 1); - break; - case 1: - if (src == REFCLK) - REG_UPDATE(DTBCLK_P_CNTL, - DTBCLK_P1_EN, 0); - else - REG_UPDATE_2(DTBCLK_P_CNTL, - DTBCLK_P1_SRC_SEL, p_src_sel, - DTBCLK_P1_EN, 1); - break; - case 2: - if (src == REFCLK) - REG_UPDATE(DTBCLK_P_CNTL, - DTBCLK_P2_EN, 0); - else - REG_UPDATE_2(DTBCLK_P_CNTL, - DTBCLK_P2_SRC_SEL, p_src_sel, - DTBCLK_P2_EN, 1); - break; - case 3: - if (src == REFCLK) - REG_UPDATE(DTBCLK_P_CNTL, - DTBCLK_P3_EN, 0); - else - REG_UPDATE_2(DTBCLK_P_CNTL, - DTBCLK_P3_SRC_SEL, p_src_sel, - DTBCLK_P3_EN, 1); - break; - default: - BREAK_TO_DEBUGGER(); - return; - } - -} - -/* Controls the generation of pixel valid for OTG in (OTG -> HPO case) */ -static void dccg35_set_dtbclk_dto( - struct dccg *dccg, - const struct dtbclk_dto_params *params) -{ - struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); - /* DTO Output Rate / Pixel Rate = 1/4 */ - int req_dtbclk_khz = params->pixclk_khz / 4; - - if (params->ref_dtbclk_khz && req_dtbclk_khz) { - uint32_t modulo, phase; - - switch (params->otg_inst) { - case 0: - REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P0_GATE_DISABLE, 1); - break; - case 1: - REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P1_GATE_DISABLE, 1); - break; - case 2: - REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P2_GATE_DISABLE, 1); - break; - case 3: - REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P3_GATE_DISABLE, 1); - break; - } - - // phase / modulo = dtbclk / dtbclk ref - modulo = params->ref_dtbclk_khz * 1000; - phase = req_dtbclk_khz * 1000; - - REG_WRITE(DTBCLK_DTO_MODULO[params->otg_inst], modulo); - REG_WRITE(DTBCLK_DTO_PHASE[params->otg_inst], phase); - - REG_UPDATE(OTG_PIXEL_RATE_CNTL[params->otg_inst], - DTBCLK_DTO_ENABLE[params->otg_inst], 1); - - REG_WAIT(OTG_PIXEL_RATE_CNTL[params->otg_inst], - DTBCLKDTO_ENABLE_STATUS[params->otg_inst], 1, - 1, 100); - - /* program OTG_PIXEL_RATE_DIV for DIVK1 and DIVK2 fields */ - dccg35_set_pixel_rate_div(dccg, params->otg_inst, PIXEL_RATE_DIV_BY_1, PIXEL_RATE_DIV_BY_1); - - /* The recommended programming sequence to enable DTBCLK DTO to generate - * valid pixel HPO DPSTREAM ENCODER, specifies that DTO source select should - * be set only after DTO is enabled - */ - REG_UPDATE(OTG_PIXEL_RATE_CNTL[params->otg_inst], - PIPE_DTO_SRC_SEL[params->otg_inst], 2); - } else { - switch (params->otg_inst) { - case 0: - REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P0_GATE_DISABLE, 0); - break; - case 1: - REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P1_GATE_DISABLE, 0); - break; - case 2: - REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P2_GATE_DISABLE, 0); - break; - case 3: - REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P3_GATE_DISABLE, 0); - break; - } - - REG_UPDATE_2(OTG_PIXEL_RATE_CNTL[params->otg_inst], - DTBCLK_DTO_ENABLE[params->otg_inst], 0, - PIPE_DTO_SRC_SEL[params->otg_inst], params->is_hdmi ? 0 : 1); - - REG_WRITE(DTBCLK_DTO_MODULO[params->otg_inst], 0); - REG_WRITE(DTBCLK_DTO_PHASE[params->otg_inst], 0); - } -} - -static void dccg35_set_dpstreamclk( - struct dccg *dccg, - enum streamclk_source src, - int otg_inst, - int dp_hpo_inst) -{ - struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); - - /* set the dtbclk_p source */ - dccg35_set_dtbclk_p_src(dccg, src, otg_inst); - - /* enabled to select one of the DTBCLKs for pipe */ - switch (dp_hpo_inst) { - case 0: - REG_UPDATE_2(DPSTREAMCLK_CNTL, - DPSTREAMCLK0_EN, - (src == REFCLK) ? 0 : 1, DPSTREAMCLK0_SRC_SEL, otg_inst); - break; - case 1: - REG_UPDATE_2(DPSTREAMCLK_CNTL, DPSTREAMCLK1_EN, - (src == REFCLK) ? 0 : 1, DPSTREAMCLK1_SRC_SEL, otg_inst); - break; - case 2: - REG_UPDATE_2(DPSTREAMCLK_CNTL, DPSTREAMCLK2_EN, - (src == REFCLK) ? 0 : 1, DPSTREAMCLK2_SRC_SEL, otg_inst); - break; - case 3: - REG_UPDATE_2(DPSTREAMCLK_CNTL, DPSTREAMCLK3_EN, - (src == REFCLK) ? 0 : 1, DPSTREAMCLK3_SRC_SEL, otg_inst); - break; - default: - BREAK_TO_DEBUGGER(); - return; - } -} - -static void dccg35_set_physymclk_root_clock_gating( - struct dccg *dccg, - int phy_inst, - bool enable) -{ - struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); - - if (!dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk) - return; - - switch (phy_inst) { - case 0: - REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, - PHYASYMCLK_ROOT_GATE_DISABLE, enable ? 1 : 0); - break; - case 1: - REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, - PHYBSYMCLK_ROOT_GATE_DISABLE, enable ? 1 : 0); - break; - case 2: - REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, - PHYCSYMCLK_ROOT_GATE_DISABLE, enable ? 1 : 0); - break; - case 3: - REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, - PHYDSYMCLK_ROOT_GATE_DISABLE, enable ? 1 : 0); - break; - case 4: - REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, - PHYESYMCLK_ROOT_GATE_DISABLE, enable ? 1 : 0); - break; - default: - BREAK_TO_DEBUGGER(); - return; - } -} - -static void dccg35_set_physymclk( - struct dccg *dccg, - int phy_inst, - enum physymclk_clock_source clk_src, - bool force_enable) -{ - struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); - - /* Force PHYSYMCLK on and Select phyd32clk as the source of clock which is output to PHY through DCIO */ - switch (phy_inst) { - case 0: - if (force_enable) { - REG_UPDATE_2(PHYASYMCLK_CLOCK_CNTL, - PHYASYMCLK_EN, 1, - PHYASYMCLK_SRC_SEL, clk_src); - } else { - REG_UPDATE_2(PHYASYMCLK_CLOCK_CNTL, - PHYASYMCLK_EN, 0, - PHYASYMCLK_SRC_SEL, 0); - } - break; - case 1: - if (force_enable) { - REG_UPDATE_2(PHYBSYMCLK_CLOCK_CNTL, - PHYBSYMCLK_EN, 1, - PHYBSYMCLK_SRC_SEL, clk_src); - } else { - REG_UPDATE_2(PHYBSYMCLK_CLOCK_CNTL, - PHYBSYMCLK_EN, 0, - PHYBSYMCLK_SRC_SEL, 0); - } - break; - case 2: - if (force_enable) { - REG_UPDATE_2(PHYCSYMCLK_CLOCK_CNTL, - PHYCSYMCLK_EN, 1, - PHYCSYMCLK_SRC_SEL, clk_src); - } else { - REG_UPDATE_2(PHYCSYMCLK_CLOCK_CNTL, - PHYCSYMCLK_EN, 0, - PHYCSYMCLK_SRC_SEL, 0); - } - break; - case 3: - if (force_enable) { - REG_UPDATE_2(PHYDSYMCLK_CLOCK_CNTL, - PHYDSYMCLK_EN, 1, - PHYDSYMCLK_SRC_SEL, clk_src); - } else { - REG_UPDATE_2(PHYDSYMCLK_CLOCK_CNTL, - PHYDSYMCLK_EN, 0, - PHYDSYMCLK_SRC_SEL, 0); - } - break; - case 4: - if (force_enable) { - REG_UPDATE_2(PHYESYMCLK_CLOCK_CNTL, - PHYESYMCLK_EN, 1, - PHYESYMCLK_SRC_SEL, clk_src); - } else { - REG_UPDATE_2(PHYESYMCLK_CLOCK_CNTL, - PHYESYMCLK_EN, 0, - PHYESYMCLK_SRC_SEL, 0); - } - break; - default: - BREAK_TO_DEBUGGER(); - return; - } -} - -static void dccg35_set_valid_pixel_rate( - struct dccg *dccg, - int ref_dtbclk_khz, - int otg_inst, - int pixclk_khz) -{ - struct dtbclk_dto_params dto_params = {0}; - - dto_params.ref_dtbclk_khz = ref_dtbclk_khz; - dto_params.otg_inst = otg_inst; - dto_params.pixclk_khz = pixclk_khz; - dto_params.is_hdmi = true; - - dccg35_set_dtbclk_dto(dccg, &dto_params); -} - -static void dccg35_dpp_root_clock_control( - struct dccg *dccg, - unsigned int dpp_inst, - bool clock_on) -{ - struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); - - if (dccg->dpp_clock_gated[dpp_inst] == clock_on) - return; - - if (clock_on) { - /* turn off the DTO and leave phase/modulo at max */ - dcn35_set_dppclk_enable(dccg, dpp_inst, 0); - REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0, - DPPCLK0_DTO_PHASE, 0xFF, - DPPCLK0_DTO_MODULO, 0xFF); - } else { - dcn35_set_dppclk_enable(dccg, dpp_inst, 1); - /* turn on the DTO to generate a 0hz clock */ - REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0, - DPPCLK0_DTO_PHASE, 0, - DPPCLK0_DTO_MODULO, 1); - } - - dccg->dpp_clock_gated[dpp_inst] = !clock_on; -} - -static void dccg35_disable_symclk32_se( - struct dccg *dccg, - int hpo_se_inst) -{ - struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); - - /* set refclk as the source for symclk32_se */ - switch (hpo_se_inst) { - case 0: - REG_UPDATE_2(SYMCLK32_SE_CNTL, - SYMCLK32_SE0_SRC_SEL, 0, - SYMCLK32_SE0_EN, 0); - if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se) { - REG_UPDATE(DCCG_GATE_DISABLE_CNTL3, - SYMCLK32_SE0_GATE_DISABLE, 0); -// REG_UPDATE(DCCG_GATE_DISABLE_CNTL3, -// SYMCLK32_ROOT_SE0_GATE_DISABLE, 0); - } - break; - case 1: - REG_UPDATE_2(SYMCLK32_SE_CNTL, - SYMCLK32_SE1_SRC_SEL, 0, - SYMCLK32_SE1_EN, 0); - if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se) { - REG_UPDATE(DCCG_GATE_DISABLE_CNTL3, - SYMCLK32_SE1_GATE_DISABLE, 0); -// REG_UPDATE(DCCG_GATE_DISABLE_CNTL3, -// SYMCLK32_ROOT_SE1_GATE_DISABLE, 0); - } - break; - case 2: - REG_UPDATE_2(SYMCLK32_SE_CNTL, - SYMCLK32_SE2_SRC_SEL, 0, - SYMCLK32_SE2_EN, 0); - if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se) { - REG_UPDATE(DCCG_GATE_DISABLE_CNTL3, - SYMCLK32_SE2_GATE_DISABLE, 0); -// REG_UPDATE(DCCG_GATE_DISABLE_CNTL3, -// SYMCLK32_ROOT_SE2_GATE_DISABLE, 0); - } - break; - case 3: - REG_UPDATE_2(SYMCLK32_SE_CNTL, - SYMCLK32_SE3_SRC_SEL, 0, - SYMCLK32_SE3_EN, 0); - if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se) { - REG_UPDATE(DCCG_GATE_DISABLE_CNTL3, - SYMCLK32_SE3_GATE_DISABLE, 0); -// REG_UPDATE(DCCG_GATE_DISABLE_CNTL3, -// SYMCLK32_ROOT_SE3_GATE_DISABLE, 0); - } - break; - default: - BREAK_TO_DEBUGGER(); - return; - } -} - -void dccg35_init(struct dccg *dccg) -{ - int otg_inst; - /* Set HPO stream encoder to use refclk to avoid case where PHY is - * disabled and SYMCLK32 for HPO SE is sourced from PHYD32CLK which - * will cause DCN to hang. - */ - for (otg_inst = 0; otg_inst < 4; otg_inst++) - dccg35_disable_symclk32_se(dccg, otg_inst); - - if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le) - for (otg_inst = 0; otg_inst < 2; otg_inst++) - dccg31_disable_symclk32_le(dccg, otg_inst); - - if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream) - for (otg_inst = 0; otg_inst < 4; otg_inst++) - dccg314_set_dpstreamclk(dccg, REFCLK, otg_inst, - otg_inst); - - if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk) - for (otg_inst = 0; otg_inst < 5; otg_inst++) - dccg35_set_physymclk_root_clock_gating(dccg, otg_inst, - false); -/* - dccg35_enable_global_fgcg_rep( - dccg, dccg->ctx->dc->debug.enable_fine_grain_clock_gating.bits - .dccg_global_fgcg_rep);*/ -} - -void dccg35_enable_global_fgcg_rep(struct dccg *dccg, bool value) -{ - struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); - - REG_UPDATE(DCCG_GLOBAL_FGCG_REP_CNTL, DCCG_GLOBAL_FGCG_REP_DIS, !value); -} - -static void dccg35_enable_dscclk(struct dccg *dccg, int inst) -{ - struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); - - //Disable DTO - switch (inst) { - case 0: - REG_UPDATE_2(DSCCLK0_DTO_PARAM, - DSCCLK0_DTO_PHASE, 0, - DSCCLK0_DTO_MODULO, 0); - REG_UPDATE(DSCCLK_DTO_CTRL, DSCCLK0_EN, 1); - break; - case 1: - REG_UPDATE_2(DSCCLK1_DTO_PARAM, - DSCCLK1_DTO_PHASE, 0, - DSCCLK1_DTO_MODULO, 0); - REG_UPDATE(DSCCLK_DTO_CTRL, DSCCLK1_EN, 1); - break; - case 2: - REG_UPDATE_2(DSCCLK2_DTO_PARAM, - DSCCLK2_DTO_PHASE, 0, - DSCCLK2_DTO_MODULO, 0); - REG_UPDATE(DSCCLK_DTO_CTRL, DSCCLK2_EN, 1); - break; - case 3: - REG_UPDATE_2(DSCCLK3_DTO_PARAM, - DSCCLK3_DTO_PHASE, 0, - DSCCLK3_DTO_MODULO, 0); - REG_UPDATE(DSCCLK_DTO_CTRL, DSCCLK3_EN, 1); - break; - default: - BREAK_TO_DEBUGGER(); - return; - } -} - -static void dccg35_disable_dscclk(struct dccg *dccg, - int inst) -{ - struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); - - if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dsc) - return; - - switch (inst) { - case 0: - REG_UPDATE(DSCCLK_DTO_CTRL, DSCCLK0_EN, 0); - REG_UPDATE_2(DSCCLK0_DTO_PARAM, - DSCCLK0_DTO_PHASE, 0, - DSCCLK0_DTO_MODULO, 1); - break; - case 1: - REG_UPDATE(DSCCLK_DTO_CTRL, DSCCLK1_EN, 0); - REG_UPDATE_2(DSCCLK1_DTO_PARAM, - DSCCLK1_DTO_PHASE, 0, - DSCCLK1_DTO_MODULO, 1); - break; - case 2: - REG_UPDATE(DSCCLK_DTO_CTRL, DSCCLK2_EN, 0); - REG_UPDATE_2(DSCCLK2_DTO_PARAM, - DSCCLK2_DTO_PHASE, 0, - DSCCLK2_DTO_MODULO, 1); - break; - case 3: - REG_UPDATE(DSCCLK_DTO_CTRL, DSCCLK3_EN, 0); - REG_UPDATE_2(DSCCLK3_DTO_PARAM, - DSCCLK3_DTO_PHASE, 0, - DSCCLK3_DTO_MODULO, 1); - break; - default: - return; - } -} - -static void dccg35_enable_symclk_se(struct dccg *dccg, uint32_t stream_enc_inst, uint32_t link_enc_inst) -{ - struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); - - switch (link_enc_inst) { - case 0: - REG_UPDATE(SYMCLKA_CLOCK_ENABLE, - SYMCLKA_CLOCK_ENABLE, 1); - break; - case 1: - REG_UPDATE(SYMCLKB_CLOCK_ENABLE, - SYMCLKB_CLOCK_ENABLE, 1); - break; - case 2: - REG_UPDATE(SYMCLKC_CLOCK_ENABLE, - SYMCLKC_CLOCK_ENABLE, 1); - break; - case 3: - REG_UPDATE(SYMCLKD_CLOCK_ENABLE, - SYMCLKD_CLOCK_ENABLE, 1); - break; - case 4: - REG_UPDATE(SYMCLKE_CLOCK_ENABLE, - SYMCLKE_CLOCK_ENABLE, 1); - break; - } - - switch (stream_enc_inst) { - case 0: - REG_UPDATE_2(SYMCLKA_CLOCK_ENABLE, - SYMCLKA_FE_EN, 1, - SYMCLKA_FE_SRC_SEL, link_enc_inst); - break; - case 1: - REG_UPDATE_2(SYMCLKB_CLOCK_ENABLE, - SYMCLKB_FE_EN, 1, - SYMCLKB_FE_SRC_SEL, link_enc_inst); - break; - case 2: - REG_UPDATE_2(SYMCLKC_CLOCK_ENABLE, - SYMCLKC_FE_EN, 1, - SYMCLKC_FE_SRC_SEL, link_enc_inst); - break; - case 3: - REG_UPDATE_2(SYMCLKD_CLOCK_ENABLE, - SYMCLKD_FE_EN, 1, - SYMCLKD_FE_SRC_SEL, link_enc_inst); - break; - case 4: - REG_UPDATE_2(SYMCLKE_CLOCK_ENABLE, - SYMCLKE_FE_EN, 1, - SYMCLKE_FE_SRC_SEL, link_enc_inst); - break; - } -} - -/*get other front end connected to this backend*/ -static uint8_t dccg35_get_other_enabled_symclk_fe(struct dccg *dccg, uint32_t stream_enc_inst, uint32_t link_enc_inst) -{ - uint8_t num_enabled_symclk_fe = 0; - uint32_t be_clk_en = 0, fe_clk_en[5] = {0}, be_clk_sel[5] = {0}; - struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); - - switch (link_enc_inst) { - case 0: - REG_GET_3(SYMCLKA_CLOCK_ENABLE, SYMCLKA_CLOCK_ENABLE, &be_clk_en, - SYMCLKA_FE_EN, &fe_clk_en[0], - SYMCLKA_FE_SRC_SEL, &be_clk_sel[0]); - break; - case 1: - REG_GET_3(SYMCLKB_CLOCK_ENABLE, SYMCLKB_CLOCK_ENABLE, &be_clk_en, - SYMCLKB_FE_EN, &fe_clk_en[1], - SYMCLKB_FE_SRC_SEL, &be_clk_sel[1]); - break; - case 2: - REG_GET_3(SYMCLKC_CLOCK_ENABLE, SYMCLKC_CLOCK_ENABLE, &be_clk_en, - SYMCLKC_FE_EN, &fe_clk_en[2], - SYMCLKC_FE_SRC_SEL, &be_clk_sel[2]); - break; - case 3: - REG_GET_3(SYMCLKD_CLOCK_ENABLE, SYMCLKD_CLOCK_ENABLE, &be_clk_en, - SYMCLKD_FE_EN, &fe_clk_en[3], - SYMCLKD_FE_SRC_SEL, &be_clk_sel[3]); - break; - case 4: - REG_GET_3(SYMCLKE_CLOCK_ENABLE, SYMCLKE_CLOCK_ENABLE, &be_clk_en, - SYMCLKE_FE_EN, &fe_clk_en[4], - SYMCLKE_FE_SRC_SEL, &be_clk_sel[4]); - break; - } - if (be_clk_en) { - /* for DPMST, this backend could be used by multiple front end. - only disable the backend if this stream_enc_ins is the last active stream enc connected to this back_end*/ - uint8_t i; - for (i = 0; i != link_enc_inst && i < sizeof(fe_clk_en); i++) { - if (fe_clk_en[i] && be_clk_sel[i] == link_enc_inst) - num_enabled_symclk_fe++; - } - } - return num_enabled_symclk_fe; -} - -static void dccg35_disable_symclk_se(struct dccg *dccg, uint32_t stream_enc_inst, uint32_t link_enc_inst) -{ - uint8_t num_enabled_symclk_fe = 0; - struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); - - switch (stream_enc_inst) { - case 0: - REG_UPDATE_2(SYMCLKA_CLOCK_ENABLE, - SYMCLKA_FE_EN, 0, - SYMCLKA_FE_SRC_SEL, 0); - break; - case 1: - REG_UPDATE_2(SYMCLKB_CLOCK_ENABLE, - SYMCLKB_FE_EN, 0, - SYMCLKB_FE_SRC_SEL, 0); - break; - case 2: - REG_UPDATE_2(SYMCLKC_CLOCK_ENABLE, - SYMCLKC_FE_EN, 0, - SYMCLKC_FE_SRC_SEL, 0); - break; - case 3: - REG_UPDATE_2(SYMCLKD_CLOCK_ENABLE, - SYMCLKD_FE_EN, 0, - SYMCLKD_FE_SRC_SEL, 0); - break; - case 4: - REG_UPDATE_2(SYMCLKE_CLOCK_ENABLE, - SYMCLKE_FE_EN, 0, - SYMCLKE_FE_SRC_SEL, 0); - break; - } - - /*check other enabled symclk fe */ - num_enabled_symclk_fe = dccg35_get_other_enabled_symclk_fe(dccg, stream_enc_inst, link_enc_inst); - /*only turn off backend clk if other front end attachecd to this backend are all off, - for mst, only turn off the backend if this is the last front end*/ - if (num_enabled_symclk_fe == 0) { - switch (link_enc_inst) { - case 0: - REG_UPDATE(SYMCLKA_CLOCK_ENABLE, - SYMCLKA_CLOCK_ENABLE, 0); - break; - case 1: - REG_UPDATE(SYMCLKB_CLOCK_ENABLE, - SYMCLKB_CLOCK_ENABLE, 0); - break; - case 2: - REG_UPDATE(SYMCLKC_CLOCK_ENABLE, - SYMCLKC_CLOCK_ENABLE, 0); - break; - case 3: - REG_UPDATE(SYMCLKD_CLOCK_ENABLE, - SYMCLKD_CLOCK_ENABLE, 0); - break; - case 4: - REG_UPDATE(SYMCLKE_CLOCK_ENABLE, - SYMCLKE_CLOCK_ENABLE, 0); - break; - } - } -} - -static const struct dccg_funcs dccg35_funcs = { - .update_dpp_dto = dccg35_update_dpp_dto, - .dpp_root_clock_control = dccg35_dpp_root_clock_control, - .get_dccg_ref_freq = dccg31_get_dccg_ref_freq, - .dccg_init = dccg35_init, - .set_dpstreamclk = dccg35_set_dpstreamclk, - .enable_symclk32_se = dccg31_enable_symclk32_se, - .disable_symclk32_se = dccg35_disable_symclk32_se, - .enable_symclk32_le = dccg31_enable_symclk32_le, - .disable_symclk32_le = dccg31_disable_symclk32_le, - .set_symclk32_le_root_clock_gating = dccg31_set_symclk32_le_root_clock_gating, - .set_physymclk = dccg35_set_physymclk, - .set_physymclk_root_clock_gating = dccg35_set_physymclk_root_clock_gating, - .set_dtbclk_dto = dccg35_set_dtbclk_dto, - .set_audio_dtbclk_dto = dccg31_set_audio_dtbclk_dto, - .set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en, - .otg_add_pixel = dccg31_otg_add_pixel, - .otg_drop_pixel = dccg31_otg_drop_pixel, - .set_dispclk_change_mode = dccg31_set_dispclk_change_mode, - .disable_dsc = dccg35_disable_dscclk, - .enable_dsc = dccg35_enable_dscclk, - .set_pixel_rate_div = dccg35_set_pixel_rate_div, - .set_valid_pixel_rate = dccg35_set_valid_pixel_rate, - .enable_symclk_se = dccg35_enable_symclk_se, - .disable_symclk_se = dccg35_disable_symclk_se, - .set_dtbclk_p_src = dccg35_set_dtbclk_p_src, -}; - -struct dccg *dccg35_create( - struct dc_context *ctx, - const struct dccg_registers *regs, - const struct dccg_shift *dccg_shift, - const struct dccg_mask *dccg_mask) -{ - struct dcn_dccg *dccg_dcn = kzalloc(sizeof(*dccg_dcn), GFP_KERNEL); - struct dccg *base; - - if (dccg_dcn == NULL) { - BREAK_TO_DEBUGGER(); - return NULL; - } - - base = &dccg_dcn->base; - base->ctx = ctx; - base->funcs = &dccg35_funcs; - - dccg_dcn->regs = regs; - dccg_dcn->dccg_shift = dccg_shift; - dccg_dcn->dccg_mask = dccg_mask; - - return &dccg_dcn->base; -} diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dccg.h b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dccg.h deleted file mode 100644 index 1586a45ca3bd..000000000000 --- a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dccg.h +++ /dev/null @@ -1,246 +0,0 @@ -/* SPDX-License-Identifier: MIT */ -/* - * Copyright 2023 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#ifndef __DCN35_DCCG_H__ -#define __DCN35_DCCG_H__ - -#include "dcn314/dcn314_dccg.h" - -#define DCCG_SFII(block, reg_name, field_prefix, field_name, inst, post_fix)\ - .field_prefix ## _ ## field_name[inst] = block ## inst ## _ ## reg_name ## __ ## field_prefix ## inst ## _ ## field_name ## post_fix - - -#define DCCG_REG_LIST_DCN35() \ - DCCG_REG_LIST_DCN314(),\ - SR(DPPCLK_CTRL),\ - SR(DCCG_GATE_DISABLE_CNTL4),\ - SR(DCCG_GATE_DISABLE_CNTL5),\ - SR(DCCG_GATE_DISABLE_CNTL6),\ - SR(DCCG_GLOBAL_FGCG_REP_CNTL),\ - SR(SYMCLKA_CLOCK_ENABLE),\ - SR(SYMCLKB_CLOCK_ENABLE),\ - SR(SYMCLKC_CLOCK_ENABLE),\ - SR(SYMCLKD_CLOCK_ENABLE),\ - SR(SYMCLKE_CLOCK_ENABLE) - -#define DCCG_MASK_SH_LIST_DCN35(mask_sh) \ - DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 0, mask_sh),\ - DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 1, mask_sh),\ - DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 2, mask_sh),\ - DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 3, mask_sh),\ - DCCG_SF(DPPCLK_CTRL, DPPCLK0_EN, mask_sh),\ - DCCG_SF(DPPCLK_CTRL, DPPCLK1_EN, mask_sh),\ - DCCG_SF(DPPCLK_CTRL, DPPCLK2_EN, mask_sh),\ - DCCG_SF(DPPCLK_CTRL, DPPCLK3_EN, mask_sh),\ - DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_PHASE, mask_sh),\ - DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_MODULO, mask_sh),\ - DCCG_SF(HDMICHARCLK0_CLOCK_CNTL, HDMICHARCLK0_EN, mask_sh),\ - DCCG_SF(HDMICHARCLK0_CLOCK_CNTL, HDMICHARCLK0_SRC_SEL, mask_sh),\ - DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_EN, mask_sh),\ - DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_SRC_SEL, mask_sh),\ - DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_EN, mask_sh),\ - DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_SRC_SEL, mask_sh),\ - DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_EN, mask_sh),\ - DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_SRC_SEL, mask_sh),\ - DCCG_SF(PHYDSYMCLK_CLOCK_CNTL, PHYDSYMCLK_EN, mask_sh),\ - DCCG_SF(PHYDSYMCLK_CLOCK_CNTL, PHYDSYMCLK_SRC_SEL, mask_sh),\ - DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK0_EN, mask_sh),\ - DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK1_EN, mask_sh),\ - DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK2_EN, mask_sh),\ - DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK3_EN, mask_sh),\ - DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK0_SRC_SEL, mask_sh),\ - DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK1_SRC_SEL, mask_sh),\ - DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK2_SRC_SEL, mask_sh),\ - DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK3_SRC_SEL, mask_sh),\ - DCCG_SF(HDMISTREAMCLK_CNTL, HDMISTREAMCLK0_EN, mask_sh),\ - DCCG_SF(HDMISTREAMCLK_CNTL, HDMISTREAMCLK0_SRC_SEL, mask_sh),\ - DCCG_SF(DSCCLK_DTO_CTRL, DSCCLK0_EN, mask_sh),\ - DCCG_SF(DSCCLK_DTO_CTRL, DSCCLK1_EN, mask_sh),\ - DCCG_SF(DSCCLK_DTO_CTRL, DSCCLK2_EN, mask_sh),\ - DCCG_SF(DSCCLK_DTO_CTRL, DSCCLK3_EN, mask_sh),\ - DCCG_SF(DSCCLK0_DTO_PARAM, DSCCLK0_DTO_PHASE, mask_sh),\ - DCCG_SF(DSCCLK0_DTO_PARAM, DSCCLK0_DTO_MODULO, mask_sh),\ - DCCG_SF(DSCCLK1_DTO_PARAM, DSCCLK1_DTO_PHASE, mask_sh),\ - DCCG_SF(DSCCLK1_DTO_PARAM, DSCCLK1_DTO_MODULO, mask_sh),\ - DCCG_SF(DSCCLK2_DTO_PARAM, DSCCLK2_DTO_PHASE, mask_sh),\ - DCCG_SF(DSCCLK2_DTO_PARAM, DSCCLK2_DTO_MODULO, mask_sh),\ - DCCG_SF(DSCCLK3_DTO_PARAM, DSCCLK3_DTO_PHASE, mask_sh),\ - DCCG_SF(DSCCLK3_DTO_PARAM, DSCCLK3_DTO_MODULO, mask_sh),\ - DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE0_SRC_SEL, mask_sh),\ - DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE1_SRC_SEL, mask_sh),\ - DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE2_SRC_SEL, mask_sh),\ - DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE3_SRC_SEL, mask_sh),\ - DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE0_EN, mask_sh),\ - DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE1_EN, mask_sh),\ - DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE2_EN, mask_sh),\ - DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE3_EN, mask_sh),\ - DCCG_SF(SYMCLK32_LE_CNTL, SYMCLK32_LE0_SRC_SEL, mask_sh),\ - DCCG_SF(SYMCLK32_LE_CNTL, SYMCLK32_LE1_SRC_SEL, mask_sh),\ - DCCG_SF(SYMCLK32_LE_CNTL, SYMCLK32_LE0_EN, mask_sh),\ - DCCG_SF(SYMCLK32_LE_CNTL, SYMCLK32_LE1_EN, mask_sh),\ - DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 0, mask_sh),\ - DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 1, mask_sh),\ - DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 2, mask_sh),\ - DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 3, mask_sh),\ - DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLKDTO, ENABLE_STATUS, 0, mask_sh),\ - DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLKDTO, ENABLE_STATUS, 1, mask_sh),\ - DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLKDTO, ENABLE_STATUS, 2, mask_sh),\ - DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLKDTO, ENABLE_STATUS, 3, mask_sh),\ - DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 0, mask_sh),\ - DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 1, mask_sh),\ - DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 2, mask_sh),\ - DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 3, mask_sh),\ - DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 0, mask_sh),\ - DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 1, mask_sh),\ - DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 2, mask_sh),\ - DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 3, mask_sh),\ - DCCG_SF(OTG_PIXEL_RATE_DIV, OTG0_PIXEL_RATE_DIVK1, mask_sh),\ - DCCG_SF(OTG_PIXEL_RATE_DIV, OTG0_PIXEL_RATE_DIVK2, mask_sh),\ - DCCG_SF(OTG_PIXEL_RATE_DIV, OTG1_PIXEL_RATE_DIVK1, mask_sh),\ - DCCG_SF(OTG_PIXEL_RATE_DIV, OTG1_PIXEL_RATE_DIVK2, mask_sh),\ - DCCG_SF(OTG_PIXEL_RATE_DIV, OTG2_PIXEL_RATE_DIVK1, mask_sh),\ - DCCG_SF(OTG_PIXEL_RATE_DIV, OTG2_PIXEL_RATE_DIVK2, mask_sh),\ - DCCG_SF(OTG_PIXEL_RATE_DIV, OTG3_PIXEL_RATE_DIVK1, mask_sh),\ - DCCG_SF(OTG_PIXEL_RATE_DIV, OTG3_PIXEL_RATE_DIVK2, mask_sh),\ - DCCG_SF(OTG_PIXEL_RATE_DIV, OTG3_PIXEL_RATE_DIVK2, mask_sh),\ - DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 0, mask_sh),\ - DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 1, mask_sh),\ - DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 2, mask_sh),\ - DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 3, mask_sh),\ - DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P0_SRC_SEL, mask_sh),\ - DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P0_EN, mask_sh),\ - DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P1_SRC_SEL, mask_sh),\ - DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P1_EN, mask_sh),\ - DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P2_SRC_SEL, mask_sh),\ - DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P2_EN, mask_sh),\ - DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P3_SRC_SEL, mask_sh),\ - DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P3_EN, mask_sh),\ - DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_EN, mask_sh),\ - DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_SRC_SEL, mask_sh),\ - DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_EN, mask_sh),\ - DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_SRC_SEL, mask_sh),\ - DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_EN, mask_sh),\ - DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_SRC_SEL, mask_sh),\ - DCCG_SF(PHYDSYMCLK_CLOCK_CNTL, PHYDSYMCLK_EN, mask_sh),\ - DCCG_SF(PHYDSYMCLK_CLOCK_CNTL, PHYDSYMCLK_SRC_SEL, mask_sh),\ - DCCG_SF(PHYESYMCLK_CLOCK_CNTL, PHYESYMCLK_EN, mask_sh),\ - DCCG_SF(PHYESYMCLK_CLOCK_CNTL, PHYESYMCLK_SRC_SEL, mask_sh),\ - DCCG_SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO_SEL, mask_sh),\ - DCCG_SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, mask_sh),\ - DCCG_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, mask_sh),\ - DCCG_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_RDIVIDER, mask_sh),\ - DCCG_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, mask_sh),\ - DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYASYMCLK_ROOT_GATE_DISABLE, mask_sh),\ - DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYBSYMCLK_ROOT_GATE_DISABLE, mask_sh),\ - DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYCSYMCLK_ROOT_GATE_DISABLE, mask_sh),\ - DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYDSYMCLK_ROOT_GATE_DISABLE, mask_sh),\ - DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYESYMCLK_ROOT_GATE_DISABLE, mask_sh),\ - DCCG_SF(DCCG_GLOBAL_FGCG_REP_CNTL, DCCG_GLOBAL_FGCG_REP_DIS, mask_sh),\ - DCCG_SF(SYMCLKA_CLOCK_ENABLE, SYMCLKA_CLOCK_ENABLE, mask_sh),\ - DCCG_SF(SYMCLKB_CLOCK_ENABLE, SYMCLKB_CLOCK_ENABLE, mask_sh),\ - DCCG_SF(SYMCLKC_CLOCK_ENABLE, SYMCLKC_CLOCK_ENABLE, mask_sh),\ - DCCG_SF(SYMCLKD_CLOCK_ENABLE, SYMCLKD_CLOCK_ENABLE, mask_sh),\ - DCCG_SF(SYMCLKE_CLOCK_ENABLE, SYMCLKE_CLOCK_ENABLE, mask_sh),\ - DCCG_SF(SYMCLKA_CLOCK_ENABLE, SYMCLKA_FE_EN, mask_sh),\ - DCCG_SF(SYMCLKB_CLOCK_ENABLE, SYMCLKB_FE_EN, mask_sh),\ - DCCG_SF(SYMCLKC_CLOCK_ENABLE, SYMCLKC_FE_EN, mask_sh),\ - DCCG_SF(SYMCLKD_CLOCK_ENABLE, SYMCLKD_FE_EN, mask_sh),\ - DCCG_SF(SYMCLKE_CLOCK_ENABLE, SYMCLKE_FE_EN, mask_sh),\ - DCCG_SF(SYMCLKA_CLOCK_ENABLE, SYMCLKA_SRC_SEL, mask_sh),\ - DCCG_SF(SYMCLKB_CLOCK_ENABLE, SYMCLKB_SRC_SEL, mask_sh),\ - DCCG_SF(SYMCLKC_CLOCK_ENABLE, SYMCLKC_SRC_SEL, mask_sh),\ - DCCG_SF(SYMCLKD_CLOCK_ENABLE, SYMCLKD_SRC_SEL, mask_sh),\ - DCCG_SF(SYMCLKE_CLOCK_ENABLE, SYMCLKE_SRC_SEL, mask_sh),\ - DCCG_SF(SYMCLKA_CLOCK_ENABLE, SYMCLKA_FE_SRC_SEL, mask_sh),\ - DCCG_SF(SYMCLKB_CLOCK_ENABLE, SYMCLKB_FE_SRC_SEL, mask_sh),\ - DCCG_SF(SYMCLKC_CLOCK_ENABLE, SYMCLKC_FE_SRC_SEL, mask_sh),\ - DCCG_SF(SYMCLKD_CLOCK_ENABLE, SYMCLKD_FE_SRC_SEL, mask_sh),\ - DCCG_SF(SYMCLKE_CLOCK_ENABLE, SYMCLKE_FE_SRC_SEL, mask_sh),\ - DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P0_GATE_DISABLE, mask_sh),\ - DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P1_GATE_DISABLE, mask_sh),\ - DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P2_GATE_DISABLE, mask_sh),\ - DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P3_GATE_DISABLE, mask_sh),\ - DCCG_SF(DCCG_GATE_DISABLE_CNTL6, DSCCLK0_ROOT_GATE_DISABLE, mask_sh),\ - DCCG_SF(DCCG_GATE_DISABLE_CNTL6, DSCCLK1_ROOT_GATE_DISABLE, mask_sh),\ - DCCG_SF(DCCG_GATE_DISABLE_CNTL6, DSCCLK2_ROOT_GATE_DISABLE, mask_sh),\ - DCCG_SF(DCCG_GATE_DISABLE_CNTL6, DSCCLK3_ROOT_GATE_DISABLE, mask_sh),\ - DCCG_SF(DCCG_GATE_DISABLE_CNTL5, SYMCLKA_FE_ROOT_GATE_DISABLE, mask_sh),\ - DCCG_SF(DCCG_GATE_DISABLE_CNTL5, SYMCLKB_FE_ROOT_GATE_DISABLE, mask_sh),\ - DCCG_SF(DCCG_GATE_DISABLE_CNTL5, SYMCLKC_FE_ROOT_GATE_DISABLE, mask_sh),\ - DCCG_SF(DCCG_GATE_DISABLE_CNTL5, SYMCLKD_FE_ROOT_GATE_DISABLE, mask_sh),\ - DCCG_SF(DCCG_GATE_DISABLE_CNTL5, SYMCLKE_FE_ROOT_GATE_DISABLE, mask_sh),\ - DCCG_SF(DCCG_GATE_DISABLE_CNTL6, DPPCLK0_ROOT_GATE_DISABLE, mask_sh),\ - DCCG_SF(DCCG_GATE_DISABLE_CNTL6, DPPCLK1_ROOT_GATE_DISABLE, mask_sh),\ - DCCG_SF(DCCG_GATE_DISABLE_CNTL6, DPPCLK2_ROOT_GATE_DISABLE, mask_sh),\ - DCCG_SF(DCCG_GATE_DISABLE_CNTL6, DPPCLK3_ROOT_GATE_DISABLE, mask_sh),\ - DCCG_SF(DCCG_GATE_DISABLE_CNTL2, HDMICHARCLK0_GATE_DISABLE, mask_sh),\ - DCCG_SF(DCCG_GATE_DISABLE_CNTL4, HDMICHARCLK0_ROOT_GATE_DISABLE, mask_sh),\ - DCCG_SF(DCCG_GATE_DISABLE_CNTL6, HDMISTREAMCLK0_ROOT_GATE_DISABLE, mask_sh),\ - DCCG_SF(DCCG_GATE_DISABLE_CNTL5, SYMCLKA_ROOT_GATE_DISABLE, mask_sh),\ - DCCG_SF(DCCG_GATE_DISABLE_CNTL5, SYMCLKB_ROOT_GATE_DISABLE, mask_sh),\ - DCCG_SF(DCCG_GATE_DISABLE_CNTL5, SYMCLKC_ROOT_GATE_DISABLE, mask_sh),\ - DCCG_SF(DCCG_GATE_DISABLE_CNTL5, SYMCLKD_ROOT_GATE_DISABLE, mask_sh),\ - DCCG_SF(DCCG_GATE_DISABLE_CNTL5, SYMCLKE_ROOT_GATE_DISABLE, mask_sh),\ - DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE0_GATE_DISABLE, mask_sh),\ - DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE1_GATE_DISABLE, mask_sh),\ - DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE2_GATE_DISABLE, mask_sh),\ - DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE3_GATE_DISABLE, mask_sh),\ - DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_LE0_GATE_DISABLE, mask_sh),\ - DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_LE1_GATE_DISABLE, mask_sh),\ - DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_SE0_GATE_DISABLE, mask_sh),\ - DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_SE1_GATE_DISABLE, mask_sh),\ - DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_SE2_GATE_DISABLE, mask_sh),\ - DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_SE3_GATE_DISABLE, mask_sh),\ - DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_LE0_GATE_DISABLE, mask_sh),\ - DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_LE1_GATE_DISABLE, mask_sh),\ - DCCG_SF(DCCG_GATE_DISABLE_CNTL4, PHYA_REFCLK_ROOT_GATE_DISABLE, mask_sh),\ - DCCG_SF(DCCG_GATE_DISABLE_CNTL4, PHYB_REFCLK_ROOT_GATE_DISABLE, mask_sh),\ - DCCG_SF(DCCG_GATE_DISABLE_CNTL4, PHYC_REFCLK_ROOT_GATE_DISABLE, mask_sh),\ - DCCG_SF(DCCG_GATE_DISABLE_CNTL4, PHYD_REFCLK_ROOT_GATE_DISABLE, mask_sh),\ - DCCG_SF(DCCG_GATE_DISABLE_CNTL4, PHYE_REFCLK_ROOT_GATE_DISABLE, mask_sh),\ - DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK0_ROOT_GATE_DISABLE, mask_sh),\ - DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK1_ROOT_GATE_DISABLE, mask_sh),\ - DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK2_ROOT_GATE_DISABLE, mask_sh),\ - DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK3_ROOT_GATE_DISABLE, mask_sh),\ - DCCG_SF(HDMISTREAMCLK0_DTO_PARAM, HDMISTREAMCLK0_DTO_PHASE, mask_sh),\ - DCCG_SF(HDMISTREAMCLK0_DTO_PARAM, HDMISTREAMCLK0_DTO_MODULO, mask_sh),\ - DCCG_SF(DCCG_GATE_DISABLE_CNTL, DISPCLK_DCCG_GATE_DISABLE, mask_sh),\ - DCCG_SF(DCCG_GATE_DISABLE_CNTL3, HDMISTREAMCLK0_GATE_DISABLE, mask_sh),\ - DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK0_GATE_DISABLE, mask_sh),\ - DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK1_GATE_DISABLE, mask_sh),\ - DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK2_GATE_DISABLE, mask_sh),\ - DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK3_GATE_DISABLE, mask_sh),\ - -struct dccg *dccg35_create( - struct dc_context *ctx, - const struct dccg_registers *regs, - const struct dccg_shift *dccg_shift, - const struct dccg_mask *dccg_mask); - -void dccg35_init(struct dccg *dccg); - -void dccg35_enable_global_fgcg_rep(struct dccg *dccg, bool value); - - -#endif //__DCN35_DCCG_H__ diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dio_link_encoder.c deleted file mode 100644 index 81e349d5835b..000000000000 --- a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dio_link_encoder.c +++ /dev/null @@ -1,272 +0,0 @@ -/* SPDX-License-Identifier: MIT */ -/* - * Copyright 2023 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#include "reg_helper.h" - -#include "core_types.h" -#include "link_encoder.h" -#include "dcn31/dcn31_dio_link_encoder.h" -#include "dcn35_dio_link_encoder.h" -#define CTX \ - enc10->base.ctx -#define DC_LOGGER \ - enc10->base.ctx->logger - -#define REG(reg)\ - (enc10->link_regs->reg) - -#undef FN -#define FN(reg_name, field_name) \ - enc10->link_shift->field_name, enc10->link_mask->field_name -/* - * @brief - * Trigger Source Select - * ASIC-dependent, actual values for register programming - */ -#define DCN35_DIG_FE_SOURCE_SELECT_INVALID 0x0 -#define DCN35_DIG_FE_SOURCE_SELECT_DIGA 0x1 -#define DCN35_DIG_FE_SOURCE_SELECT_DIGB 0x2 -#define DCN35_DIG_FE_SOURCE_SELECT_DIGC 0x4 -#define DCN35_DIG_FE_SOURCE_SELECT_DIGD 0x08 -#define DCN35_DIG_FE_SOURCE_SELECT_DIGE 0x10 - - -bool dcn35_is_dig_enabled(struct link_encoder *enc) -{ - uint32_t enabled; - struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); - - REG_GET(DIG_BE_CLK_CNTL, DIG_BE_CLK_EN, &enabled); - return (enabled == 1); -} - -enum signal_type dcn35_get_dig_mode( - struct link_encoder *enc) -{ - uint32_t value; - struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); - - REG_GET(DIG_BE_CLK_CNTL, DIG_BE_MODE, &value); - switch (value) { - case 0: - return SIGNAL_TYPE_DISPLAY_PORT; - case 2: - return SIGNAL_TYPE_DVI_SINGLE_LINK; - case 3: - return SIGNAL_TYPE_HDMI_TYPE_A; - case 5: - return SIGNAL_TYPE_DISPLAY_PORT_MST; - default: - return SIGNAL_TYPE_NONE; - } - return SIGNAL_TYPE_NONE; -} - -void dcn35_link_encoder_setup( - struct link_encoder *enc, - enum signal_type signal) -{ - struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); - - switch (signal) { - case SIGNAL_TYPE_EDP: - case SIGNAL_TYPE_DISPLAY_PORT: - /* DP SST */ - REG_UPDATE(DIG_BE_CLK_CNTL, DIG_BE_MODE, 0); - break; - case SIGNAL_TYPE_DVI_SINGLE_LINK: - case SIGNAL_TYPE_DVI_DUAL_LINK: - /* TMDS-DVI */ - REG_UPDATE(DIG_BE_CLK_CNTL, DIG_BE_MODE, 2); - break; - case SIGNAL_TYPE_HDMI_TYPE_A: - /* TMDS-HDMI */ - REG_UPDATE(DIG_BE_CLK_CNTL, DIG_BE_MODE, 3); - break; - case SIGNAL_TYPE_DISPLAY_PORT_MST: - /* DP MST */ - REG_UPDATE(DIG_BE_CLK_CNTL, DIG_BE_MODE, 5); - break; - default: - ASSERT_CRITICAL(false); - /* invalid mode ! */ - break; - } - REG_UPDATE(DIG_BE_CLK_CNTL, DIG_BE_CLK_EN, 1); - -} - -void dcn35_link_encoder_init(struct link_encoder *enc) -{ - enc32_hw_init(enc); - dcn35_link_encoder_set_fgcg(enc, enc->ctx->dc->debug.enable_fine_grain_clock_gating.bits.dio); -} - -void dcn35_link_encoder_set_fgcg(struct link_encoder *enc, bool enable) -{ - struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); - - REG_UPDATE(DIO_CLK_CNTL, DIO_FGCG_REP_DIS, !enable); -} - -static const struct link_encoder_funcs dcn35_link_enc_funcs = { - .read_state = link_enc2_read_state, - .validate_output_with_stream = - dcn30_link_encoder_validate_output_with_stream, - .hw_init = dcn35_link_encoder_init, - .setup = dcn35_link_encoder_setup, - .enable_tmds_output = dcn10_link_encoder_enable_tmds_output, - .enable_dp_output = dcn31_link_encoder_enable_dp_output, - .enable_dp_mst_output = dcn31_link_encoder_enable_dp_mst_output, - .disable_output = dcn31_link_encoder_disable_output, - .dp_set_lane_settings = dcn10_link_encoder_dp_set_lane_settings, - .dp_set_phy_pattern = dcn10_link_encoder_dp_set_phy_pattern, - .update_mst_stream_allocation_table = - dcn10_link_encoder_update_mst_stream_allocation_table, - .psr_program_dp_dphy_fast_training = - dcn10_psr_program_dp_dphy_fast_training, - .psr_program_secondary_packet = dcn10_psr_program_secondary_packet, - .connect_dig_be_to_fe = dcn10_link_encoder_connect_dig_be_to_fe, - .enable_hpd = dcn10_link_encoder_enable_hpd, - .disable_hpd = dcn10_link_encoder_disable_hpd, - .is_dig_enabled = dcn35_is_dig_enabled, - .destroy = dcn10_link_encoder_destroy, - .fec_set_enable = enc2_fec_set_enable, - .fec_set_ready = enc2_fec_set_ready, - .fec_is_active = enc2_fec_is_active, - .get_dig_frontend = dcn10_get_dig_frontend, - .get_dig_mode = dcn35_get_dig_mode, - .is_in_alt_mode = dcn31_link_encoder_is_in_alt_mode, - .get_max_link_cap = dcn31_link_encoder_get_max_link_cap, - .set_dio_phy_mux = dcn31_link_encoder_set_dio_phy_mux, -}; - -void dcn35_link_encoder_construct( - struct dcn20_link_encoder *enc20, - const struct encoder_init_data *init_data, - const struct encoder_feature_support *enc_features, - const struct dcn10_link_enc_registers *link_regs, - const struct dcn10_link_enc_aux_registers *aux_regs, - const struct dcn10_link_enc_hpd_registers *hpd_regs, - const struct dcn10_link_enc_shift *link_shift, - const struct dcn10_link_enc_mask *link_mask) -{ - struct bp_connector_speed_cap_info bp_cap_info = {0}; - const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs; - enum bp_result result = BP_RESULT_OK; - struct dcn10_link_encoder *enc10 = &enc20->enc10; - - enc10->base.funcs = &dcn35_link_enc_funcs; - enc10->base.ctx = init_data->ctx; - enc10->base.id = init_data->encoder; - - enc10->base.hpd_source = init_data->hpd_source; - enc10->base.connector = init_data->connector; - - - enc10->base.preferred_engine = ENGINE_ID_UNKNOWN; - - enc10->base.features = *enc_features; - - enc10->base.transmitter = init_data->transmitter; - - /* set the flag to indicate whether driver poll the I2C data pin - * while doing the DP sink detect - */ - -/* if (dal_adapter_service_is_feature_supported(as, - * FEATURE_DP_SINK_DETECT_POLL_DATA_PIN)) - * enc10->base.features.flags.bits. - * DP_SINK_DETECT_POLL_DATA_PIN = true; - */ - - enc10->base.output_signals = - SIGNAL_TYPE_DVI_SINGLE_LINK | - SIGNAL_TYPE_DVI_DUAL_LINK | - SIGNAL_TYPE_LVDS | - SIGNAL_TYPE_DISPLAY_PORT | - SIGNAL_TYPE_DISPLAY_PORT_MST | - SIGNAL_TYPE_EDP | - SIGNAL_TYPE_HDMI_TYPE_A; - - enc10->link_regs = link_regs; - enc10->aux_regs = aux_regs; - enc10->hpd_regs = hpd_regs; - enc10->link_shift = link_shift; - enc10->link_mask = link_mask; - - switch (enc10->base.transmitter) { - case TRANSMITTER_UNIPHY_A: - enc10->base.preferred_engine = ENGINE_ID_DIGA; - break; - case TRANSMITTER_UNIPHY_B: - enc10->base.preferred_engine = ENGINE_ID_DIGB; - break; - case TRANSMITTER_UNIPHY_C: - enc10->base.preferred_engine = ENGINE_ID_DIGC; - break; - case TRANSMITTER_UNIPHY_D: - enc10->base.preferred_engine = ENGINE_ID_DIGD; - break; - case TRANSMITTER_UNIPHY_E: - enc10->base.preferred_engine = ENGINE_ID_DIGE; - break; - default: - ASSERT_CRITICAL(false); - enc10->base.preferred_engine = ENGINE_ID_UNKNOWN; - } - - enc10->base.features.flags.bits.HDMI_6GB_EN = 1; - if (enc10->base.connector.id == CONNECTOR_ID_USBC) - enc10->base.features.flags.bits.DP_IS_USB_C = 1; - - if (bp_funcs->get_connector_speed_cap_info) - result = bp_funcs->get_connector_speed_cap_info(enc10->base.ctx->dc_bios, - enc10->base.connector, &bp_cap_info); - - /* Override features with DCE-specific values */ - if (result == BP_RESULT_OK) { - enc10->base.features.flags.bits.IS_HBR2_CAPABLE = - bp_cap_info.DP_HBR2_EN; - enc10->base.features.flags.bits.IS_HBR3_CAPABLE = - bp_cap_info.DP_HBR3_EN; - enc10->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN; - enc10->base.features.flags.bits.IS_DP2_CAPABLE = 1; - enc10->base.features.flags.bits.IS_UHBR10_CAPABLE = bp_cap_info.DP_UHBR10_EN; - enc10->base.features.flags.bits.IS_UHBR13_5_CAPABLE = bp_cap_info.DP_UHBR13_5_EN; - enc10->base.features.flags.bits.IS_UHBR20_CAPABLE = bp_cap_info.DP_UHBR20_EN; - if (bp_cap_info.DP_IS_USB_C) { - /*BIOS not switch to use CONNECTOR_ID_USBC = 24 yet*/ - enc10->base.features.flags.bits.DP_IS_USB_C = 1; - } - - } else { - DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n", - __func__, - result); - } - if (enc10->base.ctx->dc->debug.hdmi20_disable) - enc10->base.features.flags.bits.HDMI_6GB_EN = 0; - -} diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dio_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dio_link_encoder.h deleted file mode 100644 index e1e560732a9d..000000000000 --- a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dio_link_encoder.h +++ /dev/null @@ -1,137 +0,0 @@ -/* SPDX-License-Identifier: MIT */ -/* - * Copyright 2023 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#ifndef __DC_LINK_ENCODER__DCN35_H__ -#define __DC_LINK_ENCODER__DCN35_H__ - -#include "dcn32/dcn32_dio_link_encoder.h" -#include "dcn30/dcn30_dio_link_encoder.h" -#include "dcn31/dcn31_dio_link_encoder.h" - -#define LINK_ENCODER_MASK_SH_LIST_DCN35(mask_sh) \ - LE_SF(DIG0_DIG_BE_EN_CNTL, DIG_BE_ENABLE, mask_sh),\ - LE_SF(DIG0_DIG_BE_CNTL, DIG_RB_SWITCH_EN, mask_sh),\ - LE_SF(DIG0_DIG_BE_CNTL, DIG_HPD_SELECT, mask_sh),\ - LE_SF(DIG0_DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, mask_sh),\ - LE_SF(DIG0_DIG_BE_CLK_CNTL, DIG_BE_MODE, mask_sh),\ - LE_SF(DIG0_DIG_BE_CLK_CNTL, DIG_BE_CLK_EN, mask_sh),\ - LE_SF(DIG0_DIG_BE_CLK_CNTL, DIG_BE_SOFT_RESET, mask_sh),\ - LE_SF(DIG0_DIG_BE_CLK_CNTL, DIG_BE_SYMCLK_G_CLOCK_ON, mask_sh),\ - LE_SF(DIG0_DIG_BE_CLK_CNTL, DIG_BE_SYMCLK_G_TMDS_CLOCK_ON, mask_sh),\ - LE_SF(DIG0_DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, mask_sh),\ - LE_SF(DIG0_TMDS_CTL_BITS, TMDS_CTL0, mask_sh), \ - LE_SF(DP0_DP_DPHY_CNTL, DPHY_BYPASS, mask_sh),\ - LE_SF(DP0_DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE0, mask_sh),\ - LE_SF(DP0_DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE1, mask_sh),\ - LE_SF(DP0_DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE2, mask_sh),\ - LE_SF(DP0_DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE3, mask_sh),\ - LE_SF(DP0_DP_DPHY_PRBS_CNTL, DPHY_PRBS_EN, mask_sh),\ - LE_SF(DP0_DP_DPHY_PRBS_CNTL, DPHY_PRBS_SEL, mask_sh),\ - LE_SF(DP0_DP_DPHY_SYM0, DPHY_SYM1, mask_sh),\ - LE_SF(DP0_DP_DPHY_SYM0, DPHY_SYM2, mask_sh),\ - LE_SF(DP0_DP_DPHY_SYM0, DPHY_SYM3, mask_sh),\ - LE_SF(DP0_DP_DPHY_SYM1, DPHY_SYM4, mask_sh),\ - LE_SF(DP0_DP_DPHY_SYM1, DPHY_SYM5, mask_sh),\ - LE_SF(DP0_DP_DPHY_SYM1, DPHY_SYM6, mask_sh),\ - LE_SF(DP0_DP_DPHY_SYM2, DPHY_SYM7, mask_sh),\ - LE_SF(DP0_DP_DPHY_SYM2, DPHY_SYM8, mask_sh),\ - LE_SF(DP0_DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_BS_COUNT, mask_sh),\ - LE_SF(DP0_DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_ADVANCE, mask_sh),\ - LE_SF(DP0_DP_DPHY_FAST_TRAINING, DPHY_RX_FAST_TRAINING_CAPABLE, mask_sh),\ - LE_SF(DP0_DP_DPHY_BS_SR_SWAP_CNTL, DPHY_LOAD_BS_COUNT, mask_sh),\ - LE_SF(DP0_DP_DPHY_TRAINING_PATTERN_SEL, DPHY_TRAINING_PATTERN_SEL, mask_sh),\ - LE_SF(DP0_DP_DPHY_HBR2_PATTERN_CONTROL, DP_DPHY_HBR2_PATTERN_CONTROL, mask_sh),\ - LE_SF(DP0_DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, mask_sh),\ - LE_SF(DP0_DP_LINK_FRAMING_CNTL, DP_IDLE_BS_INTERVAL, mask_sh),\ - LE_SF(DP0_DP_LINK_FRAMING_CNTL, DP_VBID_DISABLE, mask_sh),\ - LE_SF(DP0_DP_LINK_FRAMING_CNTL, DP_VID_ENHANCED_FRAME_MODE, mask_sh),\ - LE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, mask_sh),\ - LE_SF(DP0_DP_CONFIG, DP_UDI_LANES, mask_sh),\ - LE_SF(DP0_DP_SEC_CNTL1, DP_SEC_GSP0_LINE_NUM, mask_sh),\ - LE_SF(DP0_DP_SEC_CNTL1, DP_SEC_GSP0_PRIORITY, mask_sh),\ - LE_SF(DP0_DP_MSE_SAT0, DP_MSE_SAT_SRC0, mask_sh),\ - LE_SF(DP0_DP_MSE_SAT0, DP_MSE_SAT_SRC1, mask_sh),\ - LE_SF(DP0_DP_MSE_SAT0, DP_MSE_SAT_SLOT_COUNT0, mask_sh),\ - LE_SF(DP0_DP_MSE_SAT0, DP_MSE_SAT_SLOT_COUNT1, mask_sh),\ - LE_SF(DP0_DP_MSE_SAT1, DP_MSE_SAT_SRC2, mask_sh),\ - LE_SF(DP0_DP_MSE_SAT1, DP_MSE_SAT_SRC3, mask_sh),\ - LE_SF(DP0_DP_MSE_SAT1, DP_MSE_SAT_SLOT_COUNT2, mask_sh),\ - LE_SF(DP0_DP_MSE_SAT1, DP_MSE_SAT_SLOT_COUNT3, mask_sh),\ - LE_SF(DP0_DP_MSE_SAT_UPDATE, DP_MSE_SAT_UPDATE, mask_sh),\ - LE_SF(DP0_DP_MSE_SAT_UPDATE, DP_MSE_16_MTP_KEEPOUT, mask_sh),\ - LE_SF(DP_AUX0_AUX_CONTROL, AUX_HPD_SEL, mask_sh),\ - LE_SF(DP_AUX0_AUX_CONTROL, AUX_LS_READ_EN, mask_sh),\ - LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_RECEIVE_WINDOW, mask_sh),\ - LE_SF(HPD0_DC_HPD_CONTROL, DC_HPD_EN, mask_sh),\ - LE_SF(DP0_DP_DPHY_CNTL, DPHY_FEC_EN, mask_sh),\ - LE_SF(DP0_DP_DPHY_CNTL, DPHY_FEC_READY_SHADOW, mask_sh),\ - LE_SF(DP0_DP_DPHY_CNTL, DPHY_FEC_ACTIVE_STATUS, mask_sh),\ - LE_SF(DIG0_TMDS_CTL_BITS, TMDS_CTL0, mask_sh), \ - LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_START_WINDOW, mask_sh),\ - LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_HALF_SYM_DETECT_LEN, mask_sh),\ - LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_TRANSITION_FILTER_EN, mask_sh),\ - LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT, mask_sh),\ - LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_ALLOW_BELOW_THRESHOLD_START, mask_sh),\ - LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_ALLOW_BELOW_THRESHOLD_STOP, mask_sh),\ - LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_PHASE_DETECT_LEN, mask_sh),\ - LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_DETECTION_THRESHOLD, mask_sh), \ - LE_SF(DP_AUX0_AUX_DPHY_TX_CONTROL, AUX_TX_PRECHARGE_LEN, mask_sh),\ - LE_SF(DP_AUX0_AUX_DPHY_TX_CONTROL, AUX_TX_PRECHARGE_SYMBOLS, mask_sh),\ - LE_SF(DP_AUX0_AUX_DPHY_TX_CONTROL, AUX_MODE_DET_CHECK_DELAY, mask_sh),\ - LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL1, AUX_RX_PRECHARGE_SKIP, mask_sh),\ - LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL1, AUX_RX_TIMEOUT_LEN, mask_sh),\ - LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL1, AUX_RX_TIMEOUT_LEN_MUL, mask_sh),\ - LE_SF(DIO_LINKA_CNTL, ENC_TYPE_SEL, mask_sh),\ - LE_SF(DIO_LINKA_CNTL, HPO_DP_ENC_SEL, mask_sh),\ - LE_SF(DIO_LINKA_CNTL, HPO_HDMI_ENC_SEL, mask_sh),\ - LE_SF(DIO_CLK_CNTL, DISPCLK_R_GATE_DIS, mask_sh),\ - LE_SF(DIO_CLK_CNTL, DISPCLK_G_GATE_DIS, mask_sh),\ - LE_SF(DIO_CLK_CNTL, REFCLK_R_GATE_DIS, mask_sh),\ - LE_SF(DIO_CLK_CNTL, REFCLK_G_GATE_DIS, mask_sh),\ - LE_SF(DIO_CLK_CNTL, SOCCLK_G_GATE_DIS, mask_sh),\ - LE_SF(DIO_CLK_CNTL, SYMCLK_FE_R_GATE_DIS, mask_sh),\ - LE_SF(DIO_CLK_CNTL, SYMCLK_FE_G_GATE_DIS, mask_sh),\ - LE_SF(DIO_CLK_CNTL, SYMCLK_R_GATE_DIS, mask_sh),\ - LE_SF(DIO_CLK_CNTL, SYMCLK_G_GATE_DIS, mask_sh),\ - LE_SF(DIO_CLK_CNTL, DIO_FGCG_REP_DIS, mask_sh) - - -void dcn35_link_encoder_construct( - struct dcn20_link_encoder *enc20, - const struct encoder_init_data *init_data, - const struct encoder_feature_support *enc_features, - const struct dcn10_link_enc_registers *link_regs, - const struct dcn10_link_enc_aux_registers *aux_regs, - const struct dcn10_link_enc_hpd_registers *hpd_regs, - const struct dcn10_link_enc_shift *link_shift, - const struct dcn10_link_enc_mask *link_mask); - -void dcn35_link_encoder_init(struct link_encoder *enc); -void dcn35_link_encoder_set_fgcg(struct link_encoder *enc, bool enabled); -bool dcn35_is_dig_enabled(struct link_encoder *enc); - -enum signal_type dcn35_get_dig_mode(struct link_encoder *enc); -void dcn35_link_encoder_setup(struct link_encoder *enc, enum signal_type signal); - -#endif /* __DC_LINK_ENCODER__DCN35_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dio_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dio_stream_encoder.c deleted file mode 100644 index 62a8f0b56006..000000000000 --- a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dio_stream_encoder.c +++ /dev/null @@ -1,526 +0,0 @@ -/* SPDX-License-Identifier: MIT */ -/* - * Copyright 2023 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ - - -#include "dc_bios_types.h" -#include "dcn30/dcn30_dio_stream_encoder.h" -#include "dcn314/dcn314_dio_stream_encoder.h" -#include "dcn32/dcn32_dio_stream_encoder.h" -#include "dcn35_dio_stream_encoder.h" -#include "reg_helper.h" -#include "hw_shared.h" -#include "link.h" -#include "dpcd_defs.h" - -#define DC_LOGGER \ - enc1->base.ctx->logger - -#define REG(reg)\ - (enc1->regs->reg) - -#undef FN -#define FN(reg_name, field_name) \ - enc1->se_shift->field_name, enc1->se_mask->field_name - -#define VBI_LINE_0 0 -#define HDMI_CLOCK_CHANNEL_RATE_MORE_340M 340000 - -#define CTX \ - enc1->base.ctx -/* setup stream encoder in dvi mode */ -static void enc35_stream_encoder_dvi_set_stream_attribute( - struct stream_encoder *enc, - struct dc_crtc_timing *crtc_timing, - bool is_dual_link) -{ - struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); - - if (!enc->ctx->dc->debug.avoid_vbios_exec_table) { - struct bp_encoder_control cntl = {0}; - - cntl.action = ENCODER_CONTROL_SETUP; - cntl.engine_id = enc1->base.id; - cntl.signal = is_dual_link ? - SIGNAL_TYPE_DVI_DUAL_LINK : SIGNAL_TYPE_DVI_SINGLE_LINK; - cntl.enable_dp_audio = false; - cntl.pixel_clock = crtc_timing->pix_clk_100hz / 10; - cntl.lanes_number = (is_dual_link) ? LANE_COUNT_EIGHT : LANE_COUNT_FOUR; - - if (enc1->base.bp->funcs->encoder_control( - enc1->base.bp, &cntl) != BP_RESULT_OK) - return; - - } else { - - //Set pattern for clock channel, default vlue 0x63 does not work - REG_UPDATE(DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, 0x1F); - - //DIG_BE_TMDS_DVI_MODE : TMDS-DVI mode is already set in link_encoder_setup - - //DIG_SOURCE_SELECT is already set in dig_connect_to_otg - - /* DIG_START is removed from the register spec */ - } - - ASSERT(crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB); - ASSERT(crtc_timing->display_color_depth == COLOR_DEPTH_888); - enc1_stream_encoder_set_stream_attribute_helper(enc1, crtc_timing); -} -/* setup stream encoder in hdmi mode */ -static void enc35_stream_encoder_hdmi_set_stream_attribute( - struct stream_encoder *enc, - struct dc_crtc_timing *crtc_timing, - int actual_pix_clk_khz, - bool enable_audio) -{ - struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); - - if (!enc->ctx->dc->debug.avoid_vbios_exec_table) { - struct bp_encoder_control cntl = {0}; - - cntl.action = ENCODER_CONTROL_SETUP; - cntl.engine_id = enc1->base.id; - cntl.signal = SIGNAL_TYPE_HDMI_TYPE_A; - cntl.enable_dp_audio = enable_audio; - cntl.pixel_clock = actual_pix_clk_khz; - cntl.lanes_number = LANE_COUNT_FOUR; - - if (enc1->base.bp->funcs->encoder_control( - enc1->base.bp, &cntl) != BP_RESULT_OK) - return; - - } else { - - //Set pattern for clock channel, default vlue 0x63 does not work - REG_UPDATE(DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, 0x1F); - - //DIG_BE_TMDS_HDMI_MODE : TMDS-HDMI mode is already set in link_encoder_setup - - //DIG_SOURCE_SELECT is already set in dig_connect_to_otg - - /* DIG_START is removed from the register spec */ - enc314_enable_fifo(enc); - } - - /* Configure pixel encoding */ - enc1_stream_encoder_set_stream_attribute_helper(enc1, crtc_timing); - - /* setup HDMI engine */ - REG_UPDATE_6(HDMI_CONTROL, - HDMI_PACKET_GEN_VERSION, 1, - HDMI_KEEPOUT_MODE, 1, - HDMI_DEEP_COLOR_ENABLE, 0, - HDMI_DATA_SCRAMBLE_EN, 0, - HDMI_NO_EXTRA_NULL_PACKET_FILLED, 1, - HDMI_CLOCK_CHANNEL_RATE, 0); - - /* Configure color depth */ - switch (crtc_timing->display_color_depth) { - case COLOR_DEPTH_888: - REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0); - break; - case COLOR_DEPTH_101010: - if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) { - REG_UPDATE_2(HDMI_CONTROL, - HDMI_DEEP_COLOR_DEPTH, 1, - HDMI_DEEP_COLOR_ENABLE, 0); - } else { - REG_UPDATE_2(HDMI_CONTROL, - HDMI_DEEP_COLOR_DEPTH, 1, - HDMI_DEEP_COLOR_ENABLE, 1); - } - break; - case COLOR_DEPTH_121212: - if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) { - REG_UPDATE_2(HDMI_CONTROL, - HDMI_DEEP_COLOR_DEPTH, 2, - HDMI_DEEP_COLOR_ENABLE, 0); - } else { - REG_UPDATE_2(HDMI_CONTROL, - HDMI_DEEP_COLOR_DEPTH, 2, - HDMI_DEEP_COLOR_ENABLE, 1); - } - break; - case COLOR_DEPTH_161616: - REG_UPDATE_2(HDMI_CONTROL, - HDMI_DEEP_COLOR_DEPTH, 3, - HDMI_DEEP_COLOR_ENABLE, 1); - break; - default: - break; - } - - if (actual_pix_clk_khz >= HDMI_CLOCK_CHANNEL_RATE_MORE_340M) { - /* enable HDMI data scrambler - * HDMI_CLOCK_CHANNEL_RATE_MORE_340M - * Clock channel frequency is 1/4 of character rate. - */ - REG_UPDATE_2(HDMI_CONTROL, - HDMI_DATA_SCRAMBLE_EN, 1, - HDMI_CLOCK_CHANNEL_RATE, 1); - } else if (crtc_timing->flags.LTE_340MCSC_SCRAMBLE) { - - /* TODO: New feature for DCE11, still need to implement */ - - /* enable HDMI data scrambler - * HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE - * Clock channel frequency is the same - * as character rate - */ - REG_UPDATE_2(HDMI_CONTROL, - HDMI_DATA_SCRAMBLE_EN, 1, - HDMI_CLOCK_CHANNEL_RATE, 0); - } - - - /* Enable transmission of General Control packet on every frame */ - REG_UPDATE_3(HDMI_VBI_PACKET_CONTROL, - HDMI_GC_CONT, 1, - HDMI_GC_SEND, 1, - HDMI_NULL_SEND, 1); - - /* Disable Audio Content Protection packet transmission */ - REG_UPDATE(HDMI_VBI_PACKET_CONTROL, HDMI_ACP_SEND, 0); - - /* following belongs to audio */ - /* Enable Audio InfoFrame packet transmission. */ - REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1); - - /* update double-buffered AUDIO_INFO registers immediately */ - ASSERT(enc->afmt); - enc->afmt->funcs->audio_info_immediate_update(enc->afmt); - - /* Select line number on which to send Audio InfoFrame packets */ - REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, - VBI_LINE_0 + 2); - - /* set HDMI GC AVMUTE */ - REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, 0); - switch (crtc_timing->pixel_encoding) { - case PIXEL_ENCODING_YCBCR422: - REG_UPDATE(HDMI_CONTROL, TMDS_PIXEL_ENCODING, 1); - break; - default: - REG_UPDATE(HDMI_CONTROL, TMDS_PIXEL_ENCODING, 0); - break; - } - REG_UPDATE(HDMI_CONTROL, TMDS_COLOR_FORMAT, 0); -} - - - -static void enc35_stream_encoder_enable( - struct stream_encoder *enc, - enum signal_type signal, - bool enable) -{ - struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); - - if (enable) { - switch (signal) { - case SIGNAL_TYPE_DVI_SINGLE_LINK: - case SIGNAL_TYPE_DVI_DUAL_LINK: - /* TMDS-DVI */ - REG_UPDATE(DIG_FE_CLK_CNTL, DIG_FE_MODE, 2); - break; - case SIGNAL_TYPE_HDMI_TYPE_A: - /* TMDS-HDMI */ - REG_UPDATE(DIG_FE_CLK_CNTL, DIG_FE_MODE, 3); - break; - case SIGNAL_TYPE_DISPLAY_PORT_MST: - /* DP MST */ - REG_UPDATE(DIG_FE_CLK_CNTL, DIG_FE_MODE, 5); - break; - case SIGNAL_TYPE_EDP: - case SIGNAL_TYPE_DISPLAY_PORT: - /* DP SST */ - REG_UPDATE(DIG_FE_CLK_CNTL, DIG_FE_MODE, 0); - break; - default: - /* invalid mode ! */ - ASSERT_CRITICAL(false); - } - } -} - -static bool is_two_pixels_per_containter(const struct dc_crtc_timing *timing) -{ - bool two_pix = timing->pixel_encoding == PIXEL_ENCODING_YCBCR420; - - two_pix = two_pix || (timing->flags.DSC && timing->pixel_encoding == PIXEL_ENCODING_YCBCR422 - && !timing->dsc_cfg.ycbcr422_simple); - return two_pix; -} - -static bool is_h_timing_divisible_by_2(const struct dc_crtc_timing *timing) -{ - /* math borrowed from function of same name in inc/resource - * checks if h_timing is divisible by 2 - */ - - bool divisible = false; - uint16_t h_blank_start = 0; - uint16_t h_blank_end = 0; - - if (timing) { - h_blank_start = timing->h_total - timing->h_front_porch; - h_blank_end = h_blank_start - timing->h_addressable; - - /* HTOTAL, Hblank start/end, and Hsync start/end all must be - * divisible by 2 in order for the horizontal timing params - * to be considered divisible by 2. Hsync start is always 0. - */ - divisible = (timing->h_total % 2 == 0) && - (h_blank_start % 2 == 0) && - (h_blank_end % 2 == 0) && - (timing->h_sync_width % 2 == 0); - } - return divisible; -} - -static bool is_dp_dig_pixel_rate_div_policy(struct dc *dc, const struct dc_crtc_timing *timing) -{ - /* should be functionally the same as dcn32_is_dp_dig_pixel_rate_div_policy for DP encoders*/ - return is_h_timing_divisible_by_2(timing) && - dc->debug.enable_dp_dig_pixel_rate_div_policy; -} - -static void enc35_stream_encoder_dp_unblank( - struct dc_link *link, - struct stream_encoder *enc, - const struct encoder_unblank_param *param) -{ - struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); - struct dc *dc = enc->ctx->dc; - - if (param->link_settings.link_rate != LINK_RATE_UNKNOWN) { - uint32_t n_vid = 0x8000; - uint32_t m_vid; - uint32_t n_multiply = 0; - uint32_t pix_per_cycle = 0; - uint64_t m_vid_l = n_vid; - - /* YCbCr 4:2:0 : Computed VID_M will be 2X the input rate */ - if (is_two_pixels_per_containter(¶m->timing) || param->opp_cnt > 1 - || is_dp_dig_pixel_rate_div_policy(dc, ¶m->timing)) { - /*this logic should be the same in get_pixel_clock_parameters() */ - n_multiply = 1; - pix_per_cycle = 1; - } - /* M / N = Fstream / Flink - * m_vid / n_vid = pixel rate / link rate - */ - - m_vid_l *= param->timing.pix_clk_100hz / 10; - m_vid_l = div_u64(m_vid_l, - param->link_settings.link_rate - * LINK_RATE_REF_FREQ_IN_KHZ); - - m_vid = (uint32_t) m_vid_l; - - /* enable auto measurement */ - - REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 0); - - /* auto measurement need 1 full 0x8000 symbol cycle to kick in, - * therefore program initial value for Mvid and Nvid - */ - - REG_UPDATE(DP_VID_N, DP_VID_N, n_vid); - - REG_UPDATE(DP_VID_M, DP_VID_M, m_vid); - - REG_UPDATE_2(DP_VID_TIMING, - DP_VID_M_N_GEN_EN, 1, - DP_VID_N_MUL, n_multiply); - - REG_UPDATE(DP_PIXEL_FORMAT, - DP_PIXEL_PER_CYCLE_PROCESSING_MODE, - pix_per_cycle); - } - - /* make sure stream is disabled before resetting steer fifo */ - REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, false); - REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, 0, 10, 5000); - - /* DIG_START is removed from the register spec */ - - /* switch DP encoder to CRTC data, but reset it the fifo first. It may happen - * that it overflows during mode transition, and sometimes doesn't recover. - */ - REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 1); - udelay(10); - - REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 0); - - /* wait 100us for DIG/DP logic to prime - * (i.e. a few video lines) - */ - udelay(100); - - /* the hardware would start sending video at the start of the next DP - * frame (i.e. rising edge of the vblank). - * NOTE: We used to program DP_VID_STREAM_DIS_DEFER = 2 here, but this - * register has no effect on enable transition! HW always makes sure - * VID_STREAM enable at start of next frame, and this is not - * programmable - */ - - REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true); - - /* - * DIG Resync FIFO now needs to be explicitly enabled. - * This should come after DP_VID_STREAM_ENABLE per HW docs. - */ - enc314_enable_fifo(enc); - - link->dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_ENABLE_DP_VID_STREAM); -} - -static void enc35_stream_encoder_map_to_link( - struct stream_encoder *enc, - uint32_t stream_enc_inst, - uint32_t link_enc_inst) -{ - struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); - - ASSERT(stream_enc_inst < 5 && link_enc_inst < 5); - REG_UPDATE(STREAM_MAPPER_CONTROL, - DIG_STREAM_LINK_TARGET, link_enc_inst); -} - -static void enc35_reset_fifo(struct stream_encoder *enc, bool reset) -{ - struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); - uint32_t reset_val = reset ? 1 : 0; - uint32_t is_symclk_on; - - REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_RESET, reset_val); - REG_GET(DIG_FE_CLK_CNTL, DIG_FE_SYMCLK_FE_G_CLOCK_ON, &is_symclk_on); - - if (is_symclk_on) - REG_WAIT(DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, reset_val, 10, 5000); - else - udelay(10); -} - -static void enc35_disable_fifo(struct stream_encoder *enc) -{ - struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); - - REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_ENABLE, 0); - REG_UPDATE(DIG_FE_EN_CNTL, DIG_FE_ENABLE, 0); - REG_UPDATE(DIG_FE_CLK_CNTL, DIG_FE_CLK_EN, 0); -} - -static void enc35_enable_fifo(struct stream_encoder *enc) -{ - struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); - - REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_READ_START_LEVEL, 0x7); - REG_UPDATE(DIG_FE_CLK_CNTL, DIG_FE_CLK_EN, 1); - REG_UPDATE(DIG_FE_EN_CNTL, DIG_FE_ENABLE, 1); - - enc35_reset_fifo(enc, true); - enc35_reset_fifo(enc, false); - - REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_ENABLE, 1); -} - -static const struct stream_encoder_funcs dcn35_str_enc_funcs = { - .dp_set_odm_combine = - enc314_dp_set_odm_combine, - .dp_set_stream_attribute = - enc2_stream_encoder_dp_set_stream_attribute, - .hdmi_set_stream_attribute = - enc35_stream_encoder_hdmi_set_stream_attribute, - .dvi_set_stream_attribute = - enc35_stream_encoder_dvi_set_stream_attribute, - .set_throttled_vcp_size = - enc1_stream_encoder_set_throttled_vcp_size, - .update_hdmi_info_packets = - enc3_stream_encoder_update_hdmi_info_packets, - .stop_hdmi_info_packets = - enc3_stream_encoder_stop_hdmi_info_packets, - .update_dp_info_packets_sdp_line_num = - enc3_stream_encoder_update_dp_info_packets_sdp_line_num, - .update_dp_info_packets = - enc3_stream_encoder_update_dp_info_packets, - .stop_dp_info_packets = - enc1_stream_encoder_stop_dp_info_packets, - .dp_blank = - enc314_stream_encoder_dp_blank, - .dp_unblank = - enc35_stream_encoder_dp_unblank, - .audio_mute_control = enc3_audio_mute_control, - - .dp_audio_setup = enc3_se_dp_audio_setup, - .dp_audio_enable = enc3_se_dp_audio_enable, - .dp_audio_disable = enc1_se_dp_audio_disable, - - .hdmi_audio_setup = enc3_se_hdmi_audio_setup, - .hdmi_audio_disable = enc1_se_hdmi_audio_disable, - .setup_stereo_sync = enc1_setup_stereo_sync, - .set_avmute = enc1_stream_encoder_set_avmute, - .dig_connect_to_otg = enc1_dig_connect_to_otg, - .dig_source_otg = enc1_dig_source_otg, - - .dp_get_pixel_format = enc1_stream_encoder_dp_get_pixel_format, - - .enc_read_state = enc314_read_state, - .dp_set_dsc_config = enc314_dp_set_dsc_config, - .dp_set_dsc_pps_info_packet = enc3_dp_set_dsc_pps_info_packet, - .set_dynamic_metadata = enc2_set_dynamic_metadata, - .hdmi_reset_stream_attribute = enc1_reset_hdmi_stream_attribute, - .dig_stream_enable = enc35_stream_encoder_enable, - - .set_input_mode = enc314_set_dig_input_mode, - .enable_fifo = enc35_enable_fifo, - .disable_fifo = enc35_disable_fifo, - .map_stream_to_link = enc35_stream_encoder_map_to_link, -}; - -void dcn35_dio_stream_encoder_construct( - struct dcn10_stream_encoder *enc1, - struct dc_context *ctx, - struct dc_bios *bp, - enum engine_id eng_id, - struct vpg *vpg, - struct afmt *afmt, - const struct dcn10_stream_enc_registers *regs, - const struct dcn10_stream_encoder_shift *se_shift, - const struct dcn10_stream_encoder_mask *se_mask) -{ - enc1->base.funcs = &dcn35_str_enc_funcs; - enc1->base.ctx = ctx; - enc1->base.id = eng_id; - enc1->base.bp = bp; - enc1->base.vpg = vpg; - enc1->base.afmt = afmt; - enc1->regs = regs; - enc1->se_shift = se_shift; - enc1->se_mask = se_mask; - enc1->base.stream_enc_inst = vpg->inst; -} - diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dio_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dio_stream_encoder.h deleted file mode 100644 index 499052329ebb..000000000000 --- a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dio_stream_encoder.h +++ /dev/null @@ -1,327 +0,0 @@ -/* SPDX-License-Identifier: MIT */ -/* - * Copyright 2023 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#ifndef __DC_DIO_STREAM_ENCODER_DCN35_H__ -#define __DC_DIO_STREAM_ENCODER_DCN35_H__ - -#include "dcn30/dcn30_vpg.h" -#include "dcn30/dcn30_afmt.h" -#include "stream_encoder.h" -#include "dcn10/dcn10_link_encoder.h" -#include "dcn20/dcn20_stream_encoder.h" - -/* Register bit field name change */ -#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_GATE_DIS__SHIFT 0x8 -#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_EN__SHIFT 0x9 -#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_CLOCK_ON__SHIFT 0xa -#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_DATA_SWAP__SHIFT 0xe -#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_DATA_ORDER_INVERT__SHIFT 0xf - -#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_GATE_DIS_MASK 0x00000100L -#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_EN_MASK 0x00000200L -#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_CLOCK_ON_MASK 0x00000400L -#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_DATA_SWAP_MASK 0x00004000L -#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_DATA_ORDER_INVERT_MASK 0x00008000L - - -#define SE_DCN35_REG_LIST(id)\ - SRI(AFMT_CNTL, DIG, id), \ - SRI(DIG_FE_CNTL, DIG, id), \ - SRI(HDMI_CONTROL, DIG, id), \ - SRI(HDMI_DB_CONTROL, DIG, id), \ - SRI(HDMI_GC, DIG, id), \ - SRI(HDMI_GENERIC_PACKET_CONTROL0, DIG, id), \ - SRI(HDMI_GENERIC_PACKET_CONTROL1, DIG, id), \ - SRI(HDMI_GENERIC_PACKET_CONTROL2, DIG, id), \ - SRI(HDMI_GENERIC_PACKET_CONTROL3, DIG, id), \ - SRI(HDMI_GENERIC_PACKET_CONTROL4, DIG, id), \ - SRI(HDMI_GENERIC_PACKET_CONTROL5, DIG, id), \ - SRI(HDMI_GENERIC_PACKET_CONTROL6, DIG, id), \ - SRI(HDMI_GENERIC_PACKET_CONTROL7, DIG, id), \ - SRI(HDMI_GENERIC_PACKET_CONTROL8, DIG, id), \ - SRI(HDMI_GENERIC_PACKET_CONTROL9, DIG, id), \ - SRI(HDMI_GENERIC_PACKET_CONTROL10, DIG, id), \ - SRI(HDMI_INFOFRAME_CONTROL0, DIG, id), \ - SRI(HDMI_INFOFRAME_CONTROL1, DIG, id), \ - SRI(HDMI_VBI_PACKET_CONTROL, DIG, id), \ - SRI(HDMI_AUDIO_PACKET_CONTROL, DIG, id),\ - SRI(HDMI_ACR_PACKET_CONTROL, DIG, id),\ - SRI(HDMI_ACR_32_0, DIG, id),\ - SRI(HDMI_ACR_32_1, DIG, id),\ - SRI(HDMI_ACR_44_0, DIG, id),\ - SRI(HDMI_ACR_44_1, DIG, id),\ - SRI(HDMI_ACR_48_0, DIG, id),\ - SRI(HDMI_ACR_48_1, DIG, id),\ - SRI(DP_DB_CNTL, DP, id), \ - SRI(DP_MSA_MISC, DP, id), \ - SRI(DP_MSA_VBID_MISC, DP, id), \ - SRI(DP_MSA_COLORIMETRY, DP, id), \ - SRI(DP_MSA_TIMING_PARAM1, DP, id), \ - SRI(DP_MSA_TIMING_PARAM2, DP, id), \ - SRI(DP_MSA_TIMING_PARAM3, DP, id), \ - SRI(DP_MSA_TIMING_PARAM4, DP, id), \ - SRI(DP_MSE_RATE_CNTL, DP, id), \ - SRI(DP_MSE_RATE_UPDATE, DP, id), \ - SRI(DP_PIXEL_FORMAT, DP, id), \ - SRI(DP_SEC_CNTL, DP, id), \ - SRI(DP_SEC_CNTL1, DP, id), \ - SRI(DP_SEC_CNTL2, DP, id), \ - SRI(DP_SEC_CNTL5, DP, id), \ - SRI(DP_SEC_CNTL6, DP, id), \ - SRI(DP_STEER_FIFO, DP, id), \ - SRI(DP_VID_M, DP, id), \ - SRI(DP_VID_N, DP, id), \ - SRI(DP_VID_STREAM_CNTL, DP, id), \ - SRI(DP_VID_TIMING, DP, id), \ - SRI(DP_SEC_AUD_N, DP, id), \ - SRI(DP_SEC_TIMESTAMP, DP, id), \ - SRI(DP_DSC_CNTL, DP, id), \ - SRI(DP_SEC_METADATA_TRANSMISSION, DP, id), \ - SRI(HDMI_METADATA_PACKET_CONTROL, DIG, id), \ - SRI(DP_SEC_FRAMING4, DP, id), \ - SRI(DP_GSP11_CNTL, DP, id), \ - SRI(DME_CONTROL, DME, id),\ - SRI(DP_SEC_METADATA_TRANSMISSION, DP, id), \ - SRI(HDMI_METADATA_PACKET_CONTROL, DIG, id), \ - SRI(DIG_FE_CNTL, DIG, id), \ - SRI(DIG_FE_EN_CNTL, DIG, id), \ - SRI(DIG_FE_CLK_CNTL, DIG, id), \ - SRI(DIG_CLOCK_PATTERN, DIG, id), \ - SRI(DIG_FIFO_CTRL0, DIG, id),\ - SRI(STREAM_MAPPER_CONTROL, DIG, id) - - -#define SE_COMMON_MASK_SH_LIST_DCN35(mask_sh)\ - SE_SF(DP0_DP_PIXEL_FORMAT, DP_PIXEL_ENCODING, mask_sh),\ - SE_SF(DP0_DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH, mask_sh),\ - SE_SF(DP0_DP_PIXEL_FORMAT, DP_PIXEL_PER_CYCLE_PROCESSING_MODE, mask_sh),\ - SE_SF(DIG0_HDMI_CONTROL, HDMI_PACKET_GEN_VERSION, mask_sh),\ - SE_SF(DIG0_HDMI_CONTROL, HDMI_KEEPOUT_MODE, mask_sh),\ - SE_SF(DIG0_HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, mask_sh),\ - SE_SF(DIG0_HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, mask_sh),\ - SE_SF(DIG0_HDMI_CONTROL, HDMI_DATA_SCRAMBLE_EN, mask_sh),\ - SE_SF(DIG0_HDMI_CONTROL, HDMI_NO_EXTRA_NULL_PACKET_FILLED, mask_sh),\ - SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, mask_sh),\ - SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, mask_sh),\ - SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, mask_sh),\ - SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_ACP_SEND, mask_sh),\ - SE_SF(DIG0_HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, mask_sh),\ - SE_SF(DIG0_HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, mask_sh),\ - SE_SF(DIG0_HDMI_GC, HDMI_GC_AVMUTE, mask_sh),\ - SE_SF(DP0_DP_MSE_RATE_CNTL, DP_MSE_RATE_X, mask_sh),\ - SE_SF(DP0_DP_MSE_RATE_CNTL, DP_MSE_RATE_Y, mask_sh),\ - SE_SF(DP0_DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING, mask_sh),\ - SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, mask_sh),\ - SE_SF(DP0_DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, mask_sh),\ - SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP1_ENABLE, mask_sh),\ - SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, mask_sh),\ - SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, mask_sh),\ - SE_SF(DP0_DP_SEC_CNTL, DP_SEC_MPG_ENABLE, mask_sh),\ - SE_SF(DP0_DP_SEC_CNTL1, DP_SEC_GSP5_LINE_REFERENCE, mask_sh),\ - SE_SF(DP0_DP_SEC_CNTL2, DP_SEC_GSP4_SEND, mask_sh),\ - SE_SF(DP0_DP_SEC_CNTL2, DP_SEC_GSP4_SEND_PENDING, mask_sh),\ - SE_SF(DP0_DP_SEC_CNTL4, DP_SEC_GSP4_LINE_NUM, mask_sh),\ - SE_SF(DP0_DP_SEC_CNTL5, DP_SEC_GSP5_LINE_NUM, mask_sh),\ - SE_SF(DP0_DP_SEC_CNTL2, DP_SEC_GSP4_SEND_ANY_LINE, mask_sh),\ - SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, mask_sh),\ - SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, mask_sh),\ - SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, mask_sh),\ - SE_SF(DP0_DP_STEER_FIFO, DP_STEER_FIFO_RESET, mask_sh),\ - SE_SF(DP0_DP_VID_TIMING, DP_VID_M_N_GEN_EN, mask_sh),\ - SE_SF(DP0_DP_VID_N, DP_VID_N, mask_sh),\ - SE_SF(DP0_DP_VID_M, DP_VID_M, mask_sh),\ - SE_SF(DIG0_HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, mask_sh),\ - SE_SF(DIG0_HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, mask_sh),\ - SE_SF(DIG0_HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, mask_sh),\ - SE_SF(DIG0_HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUDIO_PRIORITY, mask_sh),\ - SE_SF(DIG0_HDMI_ACR_32_0, HDMI_ACR_CTS_32, mask_sh),\ - SE_SF(DIG0_HDMI_ACR_32_1, HDMI_ACR_N_32, mask_sh),\ - SE_SF(DIG0_HDMI_ACR_44_0, HDMI_ACR_CTS_44, mask_sh),\ - SE_SF(DIG0_HDMI_ACR_44_1, HDMI_ACR_N_44, mask_sh),\ - SE_SF(DIG0_HDMI_ACR_48_0, HDMI_ACR_CTS_48, mask_sh),\ - SE_SF(DIG0_HDMI_ACR_48_1, HDMI_ACR_N_48, mask_sh),\ - SE_SF(DP0_DP_SEC_AUD_N, DP_SEC_AUD_N, mask_sh),\ - SE_SF(DP0_DP_SEC_TIMESTAMP, DP_SEC_TIMESTAMP_MODE, mask_sh),\ - SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ASP_ENABLE, mask_sh),\ - SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ATP_ENABLE, mask_sh),\ - SE_SF(DP0_DP_SEC_CNTL, DP_SEC_AIP_ENABLE, mask_sh),\ - SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ACM_ENABLE, mask_sh),\ - SE_SF(DIG0_AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, mask_sh),\ - SE_SF(DIG0_HDMI_CONTROL, HDMI_CLOCK_CHANNEL_RATE, mask_sh),\ - SE_SF(DIG0_HDMI_CONTROL, TMDS_PIXEL_ENCODING, mask_sh),\ - SE_SF(DIG0_HDMI_CONTROL, TMDS_COLOR_FORMAT, mask_sh),\ - SE_SF(DIG0_DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, mask_sh),\ - SE_SF(DIG0_DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, mask_sh),\ - SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP4_ENABLE, mask_sh),\ - SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP5_ENABLE, mask_sh),\ - SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP6_ENABLE, mask_sh),\ - SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP7_ENABLE, mask_sh),\ - SE_SF(DP0_DP_SEC_CNTL2, DP_SEC_GSP7_SEND, mask_sh),\ - SE_SF(DP0_DP_SEC_CNTL6, DP_SEC_GSP7_LINE_NUM, mask_sh),\ - SE_SF(DP0_DP_SEC_CNTL2, DP_SEC_GSP11_PPS, mask_sh),\ - SE_SF(DP0_DP_GSP11_CNTL, DP_SEC_GSP11_ENABLE, mask_sh),\ - SE_SF(DP0_DP_GSP11_CNTL, DP_SEC_GSP11_LINE_NUM, mask_sh),\ - SE_SF(DP0_DP_DB_CNTL, DP_DB_DISABLE, mask_sh),\ - SE_SF(DP0_DP_MSA_COLORIMETRY, DP_MSA_MISC0, mask_sh),\ - SE_SF(DP0_DP_MSA_TIMING_PARAM1, DP_MSA_HTOTAL, mask_sh),\ - SE_SF(DP0_DP_MSA_TIMING_PARAM1, DP_MSA_VTOTAL, mask_sh),\ - SE_SF(DP0_DP_MSA_TIMING_PARAM2, DP_MSA_HSTART, mask_sh),\ - SE_SF(DP0_DP_MSA_TIMING_PARAM2, DP_MSA_VSTART, mask_sh),\ - SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_HSYNCWIDTH, mask_sh),\ - SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_HSYNCPOLARITY, mask_sh),\ - SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_VSYNCWIDTH, mask_sh),\ - SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_VSYNCPOLARITY, mask_sh),\ - SE_SF(DP0_DP_MSA_TIMING_PARAM4, DP_MSA_HWIDTH, mask_sh),\ - SE_SF(DP0_DP_MSA_TIMING_PARAM4, DP_MSA_VHEIGHT, mask_sh),\ - SE_SF(DIG0_HDMI_DB_CONTROL, HDMI_DB_DISABLE, mask_sh),\ - SE_SF(DP0_DP_VID_TIMING, DP_VID_N_MUL, mask_sh),\ - SE_SF(DIG0_DIG_FE_CNTL, DIG_SOURCE_SELECT, mask_sh), \ - SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_CONT, mask_sh),\ - SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_SEND, mask_sh),\ - SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_CONT, mask_sh),\ - SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_SEND, mask_sh),\ - SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC2_CONT, mask_sh),\ - SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC2_SEND, mask_sh),\ - SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC3_CONT, mask_sh),\ - SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC3_SEND, mask_sh),\ - SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC4_CONT, mask_sh),\ - SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC4_SEND, mask_sh),\ - SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC5_CONT, mask_sh),\ - SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC5_SEND, mask_sh),\ - SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC6_CONT, mask_sh),\ - SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC6_SEND, mask_sh),\ - SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC7_CONT, mask_sh),\ - SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC7_SEND, mask_sh),\ - SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC8_CONT, mask_sh),\ - SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC8_SEND, mask_sh),\ - SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC9_CONT, mask_sh),\ - SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC9_SEND, mask_sh),\ - SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC10_CONT, mask_sh),\ - SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC10_SEND, mask_sh),\ - SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC11_CONT, mask_sh),\ - SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC11_SEND, mask_sh),\ - SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC12_CONT, mask_sh),\ - SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC12_SEND, mask_sh),\ - SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC13_CONT, mask_sh),\ - SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC13_SEND, mask_sh),\ - SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC14_CONT, mask_sh),\ - SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC14_SEND, mask_sh),\ - SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL1, HDMI_GENERIC0_LINE, mask_sh),\ - SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL1, HDMI_GENERIC1_LINE, mask_sh),\ - SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL2, HDMI_GENERIC2_LINE, mask_sh),\ - SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL2, HDMI_GENERIC3_LINE, mask_sh),\ - SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL3, HDMI_GENERIC4_LINE, mask_sh),\ - SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL3, HDMI_GENERIC5_LINE, mask_sh),\ - SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL4, HDMI_GENERIC6_LINE, mask_sh),\ - SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL4, HDMI_GENERIC7_LINE, mask_sh),\ - SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL7, HDMI_GENERIC8_LINE, mask_sh),\ - SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL7, HDMI_GENERIC9_LINE, mask_sh),\ - SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL8, HDMI_GENERIC10_LINE, mask_sh),\ - SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL8, HDMI_GENERIC11_LINE, mask_sh),\ - SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL9, HDMI_GENERIC12_LINE, mask_sh),\ - SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL9, HDMI_GENERIC13_LINE, mask_sh),\ - SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL10, HDMI_GENERIC14_LINE, mask_sh),\ - SE_SF(DP0_DP_DSC_CNTL, DP_DSC_MODE, mask_sh),\ - SE_SF(DP0_DP_MSA_VBID_MISC, DP_VBID6_LINE_REFERENCE, mask_sh),\ - SE_SF(DP0_DP_MSA_VBID_MISC, DP_VBID6_LINE_NUM, mask_sh),\ - SE_SF(DME0_DME_CONTROL, METADATA_ENGINE_EN, mask_sh),\ - SE_SF(DME0_DME_CONTROL, METADATA_HUBP_REQUESTOR_ID, mask_sh),\ - SE_SF(DME0_DME_CONTROL, METADATA_STREAM_TYPE, mask_sh),\ - SE_SF(DP0_DP_SEC_METADATA_TRANSMISSION, DP_SEC_METADATA_PACKET_ENABLE, mask_sh),\ - SE_SF(DP0_DP_SEC_METADATA_TRANSMISSION, DP_SEC_METADATA_PACKET_LINE_REFERENCE, mask_sh),\ - SE_SF(DP0_DP_SEC_METADATA_TRANSMISSION, DP_SEC_METADATA_PACKET_LINE, mask_sh),\ - SE_SF(DIG0_HDMI_METADATA_PACKET_CONTROL, HDMI_METADATA_PACKET_ENABLE, mask_sh),\ - SE_SF(DIG0_HDMI_METADATA_PACKET_CONTROL, HDMI_METADATA_PACKET_LINE_REFERENCE, mask_sh),\ - SE_SF(DIG0_HDMI_METADATA_PACKET_CONTROL, HDMI_METADATA_PACKET_LINE, mask_sh),\ - SE_SF(DIG0_HDMI_CONTROL, DOLBY_VISION_EN, mask_sh),\ - SE_SF(DIG0_DIG_FE_EN_CNTL, DIG_FE_ENABLE, mask_sh),\ - SE_SF(DIG0_DIG_FE_CLK_CNTL, DIG_FE_MODE, mask_sh),\ - SE_SF(DIG0_DIG_FE_CLK_CNTL, DIG_FE_CLK_EN, mask_sh),\ - SE_SF(DIG0_DIG_FE_CLK_CNTL, DIG_FE_SOFT_RESET, mask_sh),\ - SE_SF(DIG0_DIG_FE_CLK_CNTL, DIG_FE_DISPCLK_G_CLOCK_ON, mask_sh),\ - SE_SF(DIG0_DIG_FE_CLK_CNTL, DIG_FE_SYMCLK_FE_G_CLOCK_ON, mask_sh),\ - SE_SF(DIG0_DIG_FE_CLK_CNTL, DIG_FE_SYMCLK_FE_G_AFMT_CLOCK_ON, mask_sh),\ - SE_SF(DIG0_DIG_FE_CLK_CNTL, DIG_FE_SYMCLK_FE_G_TMDS_CLOCK_ON, mask_sh),\ - SE_SF(DIG0_DIG_FE_CLK_CNTL, DIG_FE_SOCCLK_G_AFMT_CLOCK_ON, mask_sh),\ - SE_SF(DP0_DP_SEC_FRAMING4, DP_SST_SDP_SPLITTING, mask_sh),\ - SE_SF(DIG0_DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, mask_sh),\ - SE_SF(DIG0_DIG_FIFO_CTRL0, DIG_FIFO_OUTPUT_PIXEL_MODE, mask_sh),\ - SE_SF(DIG0_DIG_FIFO_CTRL0, DIG_FIFO_READ_START_LEVEL, mask_sh),\ - SE_SF(DIG0_DIG_FIFO_CTRL0, DIG_FIFO_ENABLE, mask_sh),\ - SE_SF(DIG0_DIG_FIFO_CTRL0, DIG_FIFO_RESET, mask_sh),\ - SE_SF(DIG0_DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, mask_sh),\ - SE_SF(DIG0_STREAM_MAPPER_CONTROL, DIG_STREAM_LINK_TARGET, mask_sh), - -void dcn35_dio_stream_encoder_construct( - struct dcn10_stream_encoder *enc1, - struct dc_context *ctx, - struct dc_bios *bp, - enum engine_id eng_id, - struct vpg *vpg, - struct afmt *afmt, - const struct dcn10_stream_enc_registers *regs, - const struct dcn10_stream_encoder_shift *se_shift, - const struct dcn10_stream_encoder_mask *se_mask); - -void enc3_stream_encoder_update_hdmi_info_packets( - struct stream_encoder *enc, - const struct encoder_info_frame *info_frame); - -void enc3_stream_encoder_stop_hdmi_info_packets( - struct stream_encoder *enc); - -void enc3_stream_encoder_update_dp_info_packets_sdp_line_num( - struct stream_encoder *enc, - struct encoder_info_frame *info_frame); - -void enc3_stream_encoder_update_dp_info_packets( - struct stream_encoder *enc, - const struct encoder_info_frame *info_frame); - -void enc3_audio_mute_control( - struct stream_encoder *enc, - bool mute); - -void enc3_se_dp_audio_setup( - struct stream_encoder *enc, - unsigned int az_inst, - struct audio_info *info); - -void enc3_se_dp_audio_enable( - struct stream_encoder *enc); - -void enc3_se_hdmi_audio_setup( - struct stream_encoder *enc, - unsigned int az_inst, - struct audio_info *info, - struct audio_crtc_info *audio_crtc_info); - -void enc3_dp_set_dsc_pps_info_packet( - struct stream_encoder *enc, - bool enable, - uint8_t *dsc_packed_pps, - bool immediate_update); - - -#endif /* __DC_DIO_STREAM_ENCODER_DCN35_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dpp.c deleted file mode 100644 index 3341ef71009b..000000000000 --- a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dpp.c +++ /dev/null @@ -1,53 +0,0 @@ -/* SPDX-License-Identifier: MIT */ -/* - * Copyright 2023 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -#include "core_types.h" -#include "dcn35_dpp.h" -#include "reg_helper.h" - -#define REG(reg) dpp->tf_regs->reg - -#define CTX dpp->base.ctx - -#undef FN -#define FN(reg_name, field_name) \ - ((const struct dcn35_dpp_shift *)(dpp->tf_shift))->field_name, \ - ((const struct dcn35_dpp_mask *)(dpp->tf_mask))->field_name - -bool dpp35_construct(struct dcn3_dpp *dpp, struct dc_context *ctx, - uint32_t inst, const struct dcn3_dpp_registers *tf_regs, - const struct dcn35_dpp_shift *tf_shift, - const struct dcn35_dpp_mask *tf_mask) -{ - return dpp32_construct(dpp, ctx, inst, tf_regs, - (const struct dcn3_dpp_shift *)(tf_shift), - (const struct dcn3_dpp_mask *)(tf_mask)); -} - -void dpp35_set_fgcg(struct dcn3_dpp *dpp, bool enable) -{ - REG_UPDATE(DPP_CONTROL, DPP_FGCG_REP_DIS, !enable); -} diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dpp.h b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dpp.h deleted file mode 100644 index 09b84307cd9e..000000000000 --- a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dpp.h +++ /dev/null @@ -1,57 +0,0 @@ -/* SPDX-License-Identifier: MIT */ -/* - * Copyright 2023 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -#ifndef __DCN35_DPP_H__ -#define __DCN35_DPP_H__ - -#include "dcn32/dcn32_dpp.h" - -#define DPP_REG_LIST_SH_MASK_DCN35(mask_sh) \ - DPP_REG_LIST_SH_MASK_DCN30_COMMON(mask_sh), \ - TF_SF(DPP_TOP0_DPP_CONTROL, DPP_FGCG_REP_DIS, mask_sh) - -#define DPP_REG_FIELD_LIST_DCN35(type) \ - struct { \ - DPP_REG_FIELD_LIST_DCN3(type); \ - type DPP_FGCG_REP_DIS; \ - } - -struct dcn35_dpp_shift { - DPP_REG_FIELD_LIST_DCN35(uint8_t); -}; - -struct dcn35_dpp_mask { - DPP_REG_FIELD_LIST_DCN35(uint32_t); -}; - -bool dpp35_construct(struct dcn3_dpp *dpp3, struct dc_context *ctx, - uint32_t inst, const struct dcn3_dpp_registers *tf_regs, - const struct dcn35_dpp_shift *tf_shift, - const struct dcn35_dpp_mask *tf_mask); - -void dpp35_set_fgcg(struct dcn3_dpp *dpp, bool enable); - -#endif // __DCN35_DPP_H diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dwb.c b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dwb.c deleted file mode 100644 index b23a809999ed..000000000000 --- a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dwb.c +++ /dev/null @@ -1,58 +0,0 @@ -/* SPDX-License-Identifier: MIT */ -/* - * Copyright 2023 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#include "reg_helper.h" -#include "dcn35_dwb.h" - -#define REG(reg)\ - dwbc30->dwbc_regs->reg - -#define CTX \ - dwbc30->base.ctx - -#undef FN -#define FN(reg_name, field_name) \ - ((const struct dcn35_dwbc_shift *)(dwbc30->dwbc_shift))->field_name, \ - ((const struct dcn35_dwbc_mask *)(dwbc30->dwbc_mask)) \ - ->field_name - -#define DC_LOGGER \ - dwbc30->base.ctx->logger - -void dcn35_dwbc_construct(struct dcn30_dwbc *dwbc30, - struct dc_context *ctx, - const struct dcn30_dwbc_registers *dwbc_regs, - const struct dcn35_dwbc_shift *dwbc_shift, - const struct dcn35_dwbc_mask *dwbc_mask, - int inst) -{ - dcn30_dwbc_construct(dwbc30, ctx, dwbc_regs, - (const struct dcn30_dwbc_shift *)dwbc_shift, - (const struct dcn30_dwbc_mask *)dwbc_mask, inst); -} - -void dcn35_dwbc_set_fgcg(struct dcn30_dwbc *dwbc30, bool enable) -{ - REG_UPDATE(DWB_ENABLE_CLK_CTRL, DWB_FGCG_REP_DIS, !enable); -} diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dwb.h b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dwb.h deleted file mode 100644 index 886e727ed080..000000000000 --- a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dwb.h +++ /dev/null @@ -1,61 +0,0 @@ -/* SPDX-License-Identifier: MIT */ -/* - * Copyright 2023 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -#ifndef __DCN35_DWB_H -#define __DCN35_DWB_H - -#include "resource.h" -#include "dwb.h" -#include "dcn30/dcn30_dwb.h" - -#define DWBC_COMMON_MASK_SH_LIST_DCN35(mask_sh) \ - DWBC_COMMON_MASK_SH_LIST_DCN30(mask_sh), \ - SF_DWB2(DWB_ENABLE_CLK_CTRL, DWB_TOP, 0, DWB_FGCG_REP_DIS, mask_sh) - -#define DWBC_REG_FIELD_LIST_DCN3_5(type) \ - struct { \ - DWBC_REG_FIELD_LIST_DCN3_0(type); \ - type DWB_FGCG_REP_DIS; \ - } - -struct dcn35_dwbc_mask { - DWBC_REG_FIELD_LIST_DCN3_5(uint32_t); -}; - -struct dcn35_dwbc_shift { - DWBC_REG_FIELD_LIST_DCN3_5(uint8_t); -}; - -void dcn35_dwbc_construct(struct dcn30_dwbc *dwbc30, - struct dc_context *ctx, - const struct dcn30_dwbc_registers *dwbc_regs, - const struct dcn35_dwbc_shift *dwbc_shift, - const struct dcn35_dwbc_mask *dwbc_mask, - int inst); - -void dcn35_dwbc_set_fgcg(struct dcn30_dwbc *dwbc30, bool enable); - -#endif diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_hubbub.c deleted file mode 100644 index 339bf0c722dd..000000000000 --- a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_hubbub.c +++ /dev/null @@ -1,611 +0,0 @@ -/* SPDX-License-Identifier: MIT */ -/* - * Copyright 2023 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - - -#include "dcn30/dcn30_hubbub.h" -#include "dcn31/dcn31_hubbub.h" -#include "dcn32/dcn32_hubbub.h" -#include "dcn35_hubbub.h" -#include "dm_services.h" -#include "reg_helper.h" - - -#define CTX \ - hubbub2->base.ctx -#define DC_LOGGER \ - hubbub2->base.ctx->logger -#define REG(reg)\ - hubbub2->regs->reg - -#undef FN -#define FN(reg_name, field_name) \ - hubbub2->shifts->field_name, hubbub2->masks->field_name - -#define DCN35_CRB_SEGMENT_SIZE_KB 64 - -static void dcn35_init_crb(struct hubbub *hubbub) -{ - struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub); - - REG_GET(DCHUBBUB_DET0_CTRL, DET0_SIZE_CURRENT, - &hubbub2->det0_size); - - REG_GET(DCHUBBUB_DET1_CTRL, DET1_SIZE_CURRENT, - &hubbub2->det1_size); - - REG_GET(DCHUBBUB_DET2_CTRL, DET2_SIZE_CURRENT, - &hubbub2->det2_size); - - REG_GET(DCHUBBUB_DET3_CTRL, DET3_SIZE_CURRENT, - &hubbub2->det3_size); - - REG_GET(DCHUBBUB_COMPBUF_CTRL, COMPBUF_SIZE_CURRENT, - &hubbub2->compbuf_size_segments); - - REG_SET_2(COMPBUF_RESERVED_SPACE, 0, - COMPBUF_RESERVED_SPACE_64B, hubbub2->pixel_chunk_size / 32, - COMPBUF_RESERVED_SPACE_ZS, hubbub2->pixel_chunk_size / 128); - REG_UPDATE(DCHUBBUB_DEBUG_CTRL_0, DET_DEPTH, 0x5FF); -} - -static void dcn35_program_compbuf_size(struct hubbub *hubbub, unsigned int compbuf_size_kb, bool safe_to_increase) -{ - struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub); - unsigned int compbuf_size_segments = (compbuf_size_kb + DCN35_CRB_SEGMENT_SIZE_KB - 1) / DCN35_CRB_SEGMENT_SIZE_KB; - - if (safe_to_increase || compbuf_size_segments <= hubbub2->compbuf_size_segments) { - if (compbuf_size_segments > hubbub2->compbuf_size_segments) { - REG_WAIT(DCHUBBUB_DET0_CTRL, DET0_SIZE_CURRENT, hubbub2->det0_size, 1, 100); - REG_WAIT(DCHUBBUB_DET1_CTRL, DET1_SIZE_CURRENT, hubbub2->det1_size, 1, 100); - REG_WAIT(DCHUBBUB_DET2_CTRL, DET2_SIZE_CURRENT, hubbub2->det2_size, 1, 100); - REG_WAIT(DCHUBBUB_DET3_CTRL, DET3_SIZE_CURRENT, hubbub2->det3_size, 1, 100); - } - /* Should never be hit, if it is we have an erroneous hw config*/ - ASSERT(hubbub2->det0_size + hubbub2->det1_size + hubbub2->det2_size - + hubbub2->det3_size + compbuf_size_segments <= hubbub2->crb_size_segs); - REG_UPDATE(DCHUBBUB_COMPBUF_CTRL, COMPBUF_SIZE, compbuf_size_segments); - hubbub2->compbuf_size_segments = compbuf_size_segments; - ASSERT(REG_GET(DCHUBBUB_COMPBUF_CTRL, CONFIG_ERROR, &compbuf_size_segments) && !compbuf_size_segments); - } -} - -static uint32_t convert_and_clamp( - uint32_t wm_ns, - uint32_t refclk_mhz, - uint32_t clamp_value) -{ - uint32_t ret_val = 0; - - ret_val = wm_ns * refclk_mhz; - - ret_val /= 1000; - - if (ret_val > clamp_value) - ret_val = clamp_value; - - return ret_val; -} - -static bool hubbub35_program_stutter_z8_watermarks( - struct hubbub *hubbub, - struct dcn_watermark_set *watermarks, - unsigned int refclk_mhz, - bool safe_to_lower) -{ - struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub); - uint32_t prog_wm_value; - bool wm_pending = false; - - /* clock state A */ - if (watermarks->a.cstate_pstate.cstate_enter_plus_exit_z8_ns - > hubbub2->watermarks.a.cstate_pstate.cstate_enter_plus_exit_z8_ns) { - hubbub2->watermarks.a.cstate_pstate.cstate_enter_plus_exit_z8_ns = - watermarks->a.cstate_pstate.cstate_enter_plus_exit_z8_ns; - prog_wm_value = convert_and_clamp( - watermarks->a.cstate_pstate.cstate_enter_plus_exit_z8_ns, - refclk_mhz, 0xfffff); - REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A, 0, - DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A, prog_wm_value); - DC_LOG_BANDWIDTH_CALCS("SR_ENTER_WATERMARK_Z8_A calculated =%d\n" - "HW register value = 0x%x\n", - watermarks->a.cstate_pstate.cstate_enter_plus_exit_z8_ns, prog_wm_value); - } else if (watermarks->a.cstate_pstate.cstate_enter_plus_exit_z8_ns - < hubbub2->watermarks.a.cstate_pstate.cstate_enter_plus_exit_z8_ns) - wm_pending = true; - - if (safe_to_lower || watermarks->a.cstate_pstate.cstate_exit_z8_ns - > hubbub2->watermarks.a.cstate_pstate.cstate_exit_z8_ns) { - hubbub2->watermarks.a.cstate_pstate.cstate_exit_z8_ns = - watermarks->a.cstate_pstate.cstate_exit_z8_ns; - prog_wm_value = convert_and_clamp( - watermarks->a.cstate_pstate.cstate_exit_z8_ns, - refclk_mhz, 0xfffff); - REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A, 0, - DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A, prog_wm_value); - DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_Z8_A calculated =%d\n" - "HW register value = 0x%x\n", - watermarks->a.cstate_pstate.cstate_exit_z8_ns, prog_wm_value); - } else if (watermarks->a.cstate_pstate.cstate_exit_z8_ns - < hubbub2->watermarks.a.cstate_pstate.cstate_exit_z8_ns) - wm_pending = true; - - /* clock state B */ - - if (safe_to_lower || watermarks->b.cstate_pstate.cstate_enter_plus_exit_z8_ns - > hubbub2->watermarks.b.cstate_pstate.cstate_enter_plus_exit_z8_ns) { - hubbub2->watermarks.b.cstate_pstate.cstate_enter_plus_exit_z8_ns = - watermarks->b.cstate_pstate.cstate_enter_plus_exit_z8_ns; - prog_wm_value = convert_and_clamp( - watermarks->b.cstate_pstate.cstate_enter_plus_exit_z8_ns, - refclk_mhz, 0xfffff); - REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B, 0, - DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B, prog_wm_value); - DC_LOG_BANDWIDTH_CALCS("SR_ENTER_WATERMARK_Z8_B calculated =%d\n" - "HW register value = 0x%x\n", - watermarks->b.cstate_pstate.cstate_enter_plus_exit_z8_ns, prog_wm_value); - } else if (watermarks->b.cstate_pstate.cstate_enter_plus_exit_z8_ns - < hubbub2->watermarks.b.cstate_pstate.cstate_enter_plus_exit_z8_ns) - wm_pending = true; - - if (safe_to_lower || watermarks->b.cstate_pstate.cstate_exit_z8_ns - > hubbub2->watermarks.b.cstate_pstate.cstate_exit_z8_ns) { - hubbub2->watermarks.b.cstate_pstate.cstate_exit_z8_ns = - watermarks->b.cstate_pstate.cstate_exit_z8_ns; - prog_wm_value = convert_and_clamp( - watermarks->b.cstate_pstate.cstate_exit_z8_ns, - refclk_mhz, 0xfffff); - REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B, 0, - DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B, prog_wm_value); - DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_Z8_B calculated =%d\n" - "HW register value = 0x%x\n", - watermarks->b.cstate_pstate.cstate_exit_z8_ns, prog_wm_value); - } else if (watermarks->b.cstate_pstate.cstate_exit_z8_ns - < hubbub2->watermarks.b.cstate_pstate.cstate_exit_z8_ns) - wm_pending = true; - - /* clock state C */ - if (safe_to_lower || watermarks->c.cstate_pstate.cstate_enter_plus_exit_z8_ns - > hubbub2->watermarks.c.cstate_pstate.cstate_enter_plus_exit_z8_ns) { - hubbub2->watermarks.c.cstate_pstate.cstate_enter_plus_exit_z8_ns = - watermarks->c.cstate_pstate.cstate_enter_plus_exit_z8_ns; - prog_wm_value = convert_and_clamp( - watermarks->c.cstate_pstate.cstate_enter_plus_exit_z8_ns, - refclk_mhz, 0xfffff); - REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C, 0, - DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C, prog_wm_value); - DC_LOG_BANDWIDTH_CALCS("SR_ENTER_WATERMARK_Z8_C calculated =%d\n" - "HW register value = 0x%x\n", - watermarks->c.cstate_pstate.cstate_enter_plus_exit_z8_ns, prog_wm_value); - } else if (watermarks->c.cstate_pstate.cstate_enter_plus_exit_z8_ns - < hubbub2->watermarks.c.cstate_pstate.cstate_enter_plus_exit_z8_ns) - wm_pending = true; - - if (safe_to_lower || watermarks->c.cstate_pstate.cstate_exit_z8_ns - > hubbub2->watermarks.c.cstate_pstate.cstate_exit_z8_ns) { - hubbub2->watermarks.c.cstate_pstate.cstate_exit_z8_ns = - watermarks->c.cstate_pstate.cstate_exit_z8_ns; - prog_wm_value = convert_and_clamp( - watermarks->c.cstate_pstate.cstate_exit_z8_ns, - refclk_mhz, 0xfffff); - REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C, 0, - DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C, prog_wm_value); - DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_Z8_C calculated =%d\n" - "HW register value = 0x%x\n", - watermarks->c.cstate_pstate.cstate_exit_z8_ns, prog_wm_value); - } else if (watermarks->c.cstate_pstate.cstate_exit_z8_ns - < hubbub2->watermarks.c.cstate_pstate.cstate_exit_z8_ns) - wm_pending = true; - - /* clock state D */ - if (safe_to_lower || watermarks->d.cstate_pstate.cstate_enter_plus_exit_z8_ns - > hubbub2->watermarks.d.cstate_pstate.cstate_enter_plus_exit_z8_ns) { - hubbub2->watermarks.d.cstate_pstate.cstate_enter_plus_exit_z8_ns = - watermarks->d.cstate_pstate.cstate_enter_plus_exit_z8_ns; - prog_wm_value = convert_and_clamp( - watermarks->d.cstate_pstate.cstate_enter_plus_exit_z8_ns, - refclk_mhz, 0xfffff); - REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D, 0, - DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D, prog_wm_value); - DC_LOG_BANDWIDTH_CALCS("SR_ENTER_WATERMARK_Z8_D calculated =%d\n" - "HW register value = 0x%x\n", - watermarks->d.cstate_pstate.cstate_enter_plus_exit_z8_ns, prog_wm_value); - } else if (watermarks->d.cstate_pstate.cstate_enter_plus_exit_z8_ns - < hubbub2->watermarks.d.cstate_pstate.cstate_enter_plus_exit_z8_ns) - wm_pending = true; - - if (safe_to_lower || watermarks->d.cstate_pstate.cstate_exit_z8_ns - > hubbub2->watermarks.d.cstate_pstate.cstate_exit_z8_ns) { - hubbub2->watermarks.d.cstate_pstate.cstate_exit_z8_ns = - watermarks->d.cstate_pstate.cstate_exit_z8_ns; - prog_wm_value = convert_and_clamp( - watermarks->d.cstate_pstate.cstate_exit_z8_ns, - refclk_mhz, 0xfffff); - REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D, 0, - DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D, prog_wm_value); - DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_Z8_D calculated =%d\n" - "HW register value = 0x%x\n", - watermarks->d.cstate_pstate.cstate_exit_z8_ns, prog_wm_value); - } else if (watermarks->d.cstate_pstate.cstate_exit_z8_ns - < hubbub2->watermarks.d.cstate_pstate.cstate_exit_z8_ns) - wm_pending = true; - - return wm_pending; -} - -static void hubbub35_get_dchub_ref_freq(struct hubbub *hubbub, - unsigned int dccg_ref_freq_inKhz, - unsigned int *dchub_ref_freq_inKhz) -{ - struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub); - uint32_t ref_div = 0; - uint32_t ref_en = 0; - unsigned int dc_refclk_khz = 24000; - - REG_GET_2(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, &ref_div, - DCHUBBUB_GLOBAL_TIMER_ENABLE, &ref_en); - - if (ref_en) { - if (ref_div == 2) - *dchub_ref_freq_inKhz = dc_refclk_khz / 2; - else - *dchub_ref_freq_inKhz = dc_refclk_khz; - - /* - * The external Reference Clock may change based on the board or - * platform requirements and the programmable integer divide must - * be programmed to provide a suitable DLG RefClk frequency between - * a minimum of 20MHz and maximum of 50MHz - */ - if (*dchub_ref_freq_inKhz < 20000 || *dchub_ref_freq_inKhz > 50000) - ASSERT_CRITICAL(false); - - return; - } else { - *dchub_ref_freq_inKhz = dc_refclk_khz; - /*init sequence issue on bringup patch*/ - REG_UPDATE_2(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, 1, - DCHUBBUB_GLOBAL_TIMER_ENABLE, 1); - // HUBBUB global timer must be enabled. - ASSERT_CRITICAL(false); - return; - } -} - - -static bool hubbub35_program_watermarks( - struct hubbub *hubbub, - struct dcn_watermark_set *watermarks, - unsigned int refclk_mhz, - bool safe_to_lower) -{ - bool wm_pending = false; - struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub); - - if (hubbub32_program_urgent_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower)) - wm_pending = true; - - if (hubbub32_program_stutter_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower)) - wm_pending = true; - - if (hubbub32_program_pstate_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower)) - wm_pending = true; - - if (hubbub32_program_usr_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower)) - wm_pending = true; - - if (hubbub35_program_stutter_z8_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower)) - wm_pending = true; - - REG_SET(DCHUBBUB_ARB_SAT_LEVEL, 0, - DCHUBBUB_ARB_SAT_LEVEL, 60 * refclk_mhz); - REG_UPDATE_2(DCHUBBUB_ARB_DF_REQ_OUTSTAND, - DCHUBBUB_ARB_MIN_REQ_OUTSTAND, 0xFF, - DCHUBBUB_ARB_MIN_REQ_OUTSTAND_COMMIT_THRESHOLD, 0xA);/*hw delta*/ - REG_UPDATE(DCHUBBUB_ARB_HOSTVM_CNTL, DCHUBBUB_ARB_MAX_QOS_COMMIT_THRESHOLD, 0xF); - - hubbub1_allow_self_refresh_control(hubbub, !hubbub->ctx->dc->debug.disable_stutter); - - hubbub32_force_usr_retraining_allow(hubbub, hubbub->ctx->dc->debug.force_usr_allow); - - return wm_pending; -} - -/* Copy values from WM set A to all other sets */ -static void hubbub35_init_watermarks(struct hubbub *hubbub) -{ - struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub); - uint32_t reg; - - reg = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A); - REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, reg); - REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, reg); - REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, reg); - - reg = REG_READ(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A); - REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, reg); - REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C, reg); - REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D, reg); - - reg = REG_READ(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A); - REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, reg); - REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C, reg); - REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D, reg); - - reg = REG_READ(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A); - REG_WRITE(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, reg); - REG_WRITE(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C, reg); - REG_WRITE(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D, reg); - - reg = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A); - REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, reg); - REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, reg); - REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, reg); - - reg = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A); - REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, reg); - REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, reg); - REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, reg); - - reg = REG_READ(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A); - REG_WRITE(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B, reg); - REG_WRITE(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C, reg); - REG_WRITE(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D, reg); - - reg = REG_READ(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A); - REG_WRITE(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B, reg); - REG_WRITE(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C, reg); - REG_WRITE(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D, reg); - - reg = REG_READ(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A); - REG_WRITE(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B, reg); - REG_WRITE(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C, reg); - REG_WRITE(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D, reg); - - reg = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A); - REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B, reg); - REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C, reg); - REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D, reg); - - reg = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A); - REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B, reg); - REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C, reg); - REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D, reg); - -} - -static void hubbub35_wm_read_state(struct hubbub *hubbub, - struct dcn_hubbub_wm *wm) -{ - struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub); - struct dcn_hubbub_wm_set *s; - - memset(wm, 0, sizeof(struct dcn_hubbub_wm)); - - s = &wm->sets[0]; - s->wm_set = 0; - REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, - DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, &s->data_urgent); - - REG_GET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, - DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, &s->sr_enter); - - REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, - DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, &s->sr_exit); - - REG_GET(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A, - DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A, &s->dram_clk_change); - - REG_GET(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A, - DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A, &s->usr_retrain); - - REG_GET(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A, - DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A, &s->fclk_pstate_change); - - REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A, - DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A, &s->sr_enter_exit_Z8); - - REG_GET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A, - DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A, &s->sr_enter_Z8); - s = &wm->sets[1]; - s->wm_set = 1; - REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, - DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, &s->data_urgent); - - REG_GET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, - DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, &s->sr_enter); - - REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, - DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, &s->sr_exit); - - REG_GET(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B, - DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B, &s->dram_clk_change); - - REG_GET(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B, - DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B, &s->usr_retrain); - - REG_GET(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B, - DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B, &s->fclk_pstate_change); - - REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B, - DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B, &s->sr_enter_exit_Z8); - - REG_GET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B, - DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B, &s->sr_enter_Z8); - - s = &wm->sets[2]; - s->wm_set = 2; - REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, - DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, &s->data_urgent); - - REG_GET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, - DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, &s->sr_enter); - - REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, - DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, &s->sr_exit); - - REG_GET(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C, - DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C, &s->dram_clk_change); - - REG_GET(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C, - DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C, &s->usr_retrain); - - REG_GET(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C, - DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C, &s->fclk_pstate_change); - - REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C, - DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C, &s->sr_enter_exit_Z8); - - REG_GET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C, - DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C, &s->sr_enter_Z8); - - s = &wm->sets[3]; - s->wm_set = 3; - REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, - DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, &s->data_urgent); - - REG_GET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, - DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, &s->sr_enter); - - REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, - DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, &s->sr_exit); - - REG_GET(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D, - DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D, &s->dram_clk_change); - - REG_GET(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D, - DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D, &s->usr_retrain); - - REG_GET(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D, - DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D, &s->fclk_pstate_change); - - REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D, - DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D, &s->sr_enter_exit_Z8); - - REG_GET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D, - DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D, &s->sr_enter_Z8); -} - -static void hubbub35_set_fgcg(struct dcn20_hubbub *hubbub2, bool enable) -{ - REG_UPDATE(DCHUBBUB_CLOCK_CNTL, DCHUBBUB_FGCG_REP_DIS, !enable); -} - -static void hubbub35_init(struct hubbub *hubbub) -{ - struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub); - /*Enable clock gaters*/ - if (hubbub->ctx->dc->debug.disable_clock_gate) { - /*done in hwseq*/ - /*REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);*/ - - REG_UPDATE_2(DCHUBBUB_CLOCK_CNTL, - DISPCLK_R_DCHUBBUB_GATE_DIS, 1, - DCFCLK_R_DCHUBBUB_GATE_DIS, 1); - } - hubbub35_set_fgcg(hubbub2, - hubbub->ctx->dc->debug.enable_fine_grain_clock_gating - .bits.dchubbub); - /* - ignore the "df_pre_cstate_req" from the SDP port control. - only the DCN will determine when to connect the SDP port - */ - REG_UPDATE(DCHUBBUB_SDPIF_CFG0, - SDPIF_PORT_CONTROL, 1); - /*Set SDP's max outstanding request - When set to 1: Max outstanding is 512 - When set to 0: Max outstanding is 256 - must set the register back to 0 (max outstanding = 256) in zero frame buffer mode*/ - REG_UPDATE(DCHUBBUB_SDPIF_CFG1, - SDPIF_MAX_NUM_OUTSTANDING, 0); - - REG_UPDATE_2(DCHUBBUB_ARB_DF_REQ_OUTSTAND, - DCHUBBUB_ARB_MAX_REQ_OUTSTAND, 256, - DCHUBBUB_ARB_MIN_REQ_OUTSTAND, 256); - -} - -/*static void hubbub35_set_request_limit(struct hubbub *hubbub, - int memory_channel_count, - int words_per_channel) -{ - struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub); - - uint32_t request_limit = 3 * memory_channel_count * words_per_channel / 4; - - ASSERT((request_limit & (~0xFFF)) == 0); //field is only 24 bits long - ASSERT(request_limit > 0); //field is only 24 bits long - - if (request_limit > 0xFFF) - request_limit = 0xFFF; - - if (request_limit > 0) - REG_UPDATE(SDPIF_REQUEST_RATE_LIMIT, SDPIF_REQUEST_RATE_LIMIT, request_limit); -}*/ - -static const struct hubbub_funcs hubbub35_funcs = { - .update_dchub = hubbub2_update_dchub, - .init_dchub_sys_ctx = hubbub31_init_dchub_sys_ctx, - .init_vm_ctx = hubbub2_init_vm_ctx, - .dcc_support_swizzle = hubbub3_dcc_support_swizzle, - .dcc_support_pixel_format = hubbub2_dcc_support_pixel_format, - .get_dcc_compression_cap = hubbub3_get_dcc_compression_cap, - .wm_read_state = hubbub35_wm_read_state, - .get_dchub_ref_freq = hubbub35_get_dchub_ref_freq, - .program_watermarks = hubbub35_program_watermarks, - .allow_self_refresh_control = hubbub1_allow_self_refresh_control, - .is_allow_self_refresh_enabled = hubbub1_is_allow_self_refresh_enabled, - .verify_allow_pstate_change_high = hubbub1_verify_allow_pstate_change_high, - .force_wm_propagate_to_pipes = hubbub32_force_wm_propagate_to_pipes, - .force_pstate_change_control = hubbub3_force_pstate_change_control, - .init_watermarks = hubbub35_init_watermarks, - .program_det_size = dcn32_program_det_size, - .program_compbuf_size = dcn35_program_compbuf_size, - .init_crb = dcn35_init_crb, - .hubbub_read_state = hubbub2_read_state, - .force_usr_retraining_allow = hubbub32_force_usr_retraining_allow, - .dchubbub_init = hubbub35_init, -}; - -void hubbub35_construct(struct dcn20_hubbub *hubbub2, - struct dc_context *ctx, - const struct dcn_hubbub_registers *hubbub_regs, - const struct dcn_hubbub_shift *hubbub_shift, - const struct dcn_hubbub_mask *hubbub_mask, - int det_size_kb, - int pixel_chunk_size_kb, - int config_return_buffer_size_kb) -{ - hubbub2->base.ctx = ctx; - hubbub2->base.funcs = &hubbub35_funcs; - hubbub2->regs = hubbub_regs; - hubbub2->shifts = hubbub_shift; - hubbub2->masks = hubbub_mask; - - hubbub2->debug_test_index_pstate = 0xB; - hubbub2->detile_buf_size = det_size_kb * 1024; - hubbub2->pixel_chunk_size = pixel_chunk_size_kb * 1024; - hubbub2->crb_size_segs = config_return_buffer_size_kb / DCN35_CRB_SEGMENT_SIZE_KB; /*todo*/ -} diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_hubbub.h b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_hubbub.h deleted file mode 100644 index 54cf00ffceb8..000000000000 --- a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_hubbub.h +++ /dev/null @@ -1,155 +0,0 @@ -/* SPDX-License-Identifier: MIT */ -/* - * Copyright 2023 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -#ifndef __DC_HUBBUB_DCN35_H__ -#define __DC_HUBBUB_DCN35_H__ - -#include "dcn32/dcn32_hubbub.h" - -#define HUBBUB_REG_LIST_DCN35(id)\ - SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A),\ - SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B),\ - SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C),\ - SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D),\ - SR(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL),\ - SR(DCHUBBUB_ARB_DRAM_STATE_CNTL),\ - SR(DCHUBBUB_ARB_SAT_LEVEL),\ - SR(DCHUBBUB_ARB_DF_REQ_OUTSTAND),\ - SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ - SR(DCHUBBUB_SOFT_RESET),\ - SR(DCHUBBUB_CRC_CTRL), \ - SR(DCN_VM_FB_LOCATION_BASE),\ - SR(DCN_VM_FB_LOCATION_TOP),\ - SR(DCN_VM_FB_OFFSET),\ - SR(DCN_VM_AGP_BOT),\ - SR(DCN_VM_AGP_TOP),\ - SR(DCN_VM_AGP_BASE),\ - HUBBUB_SR_WATERMARK_REG_LIST(), \ - SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A),\ - SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B),\ - SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C),\ - SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D),\ - SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A),\ - SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B),\ - SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C),\ - SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D),\ - SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A),\ - SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B),\ - SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C),\ - SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D),\ - SR(DCHUBBUB_DET0_CTRL),\ - SR(DCHUBBUB_DET1_CTRL),\ - SR(DCHUBBUB_DET2_CTRL),\ - SR(DCHUBBUB_DET3_CTRL),\ - SR(DCHUBBUB_COMPBUF_CTRL),\ - SR(COMPBUF_RESERVED_SPACE),\ - SR(DCHUBBUB_DEBUG_CTRL_0),\ - SR(DCHUBBUB_ARB_USR_RETRAINING_CNTL),\ - SR(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A),\ - SR(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B),\ - SR(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C),\ - SR(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D),\ - SR(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A),\ - SR(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B),\ - SR(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C),\ - SR(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D),\ - SR(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A),\ - SR(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B),\ - SR(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C),\ - SR(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D),\ - SR(DCN_VM_FAULT_ADDR_MSB),\ - SR(DCN_VM_FAULT_ADDR_LSB),\ - SR(DCN_VM_FAULT_CNTL),\ - SR(DCN_VM_FAULT_STATUS),\ - SR(SDPIF_REQUEST_RATE_LIMIT),\ - SR(DCHUBBUB_CLOCK_CNTL),\ - SR(DCHUBBUB_SDPIF_CFG0),\ - SR(DCHUBBUB_SDPIF_CFG1),\ - SR(DCHUBBUB_MEM_PWR_MODE_CTRL),\ - SR(DCHUBBUB_ARB_HOSTVM_CNTL),\ - SR(DCHVM_CTRL0),\ - SR(DCHVM_MEM_CTRL),\ - SR(DCHVM_CLK_CTRL),\ - SR(DCHVM_RIOMMU_CTRL0),\ - SR(DCHVM_RIOMMU_STAT0),\ - SR(DCHUBBUB_COMPBUF_CTRL),\ - SR(COMPBUF_RESERVED_SPACE),\ - SR(DCHUBBUB_DEBUG_CTRL_0),\ - SR(DCHUBBUB_CLOCK_CNTL),\ - SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A),\ - SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A),\ - SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B),\ - SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B),\ - SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C),\ - SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C),\ - SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D),\ - SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D),\ - SR(DCHUBBUB_ARB_QOS_FORCE) - - -#define HUBBUB_MASK_SH_LIST_DCN35(mask_sh)\ - HUBBUB_MASK_SH_LIST_DCN32(mask_sh), \ - HUBBUB_SF(DCHVM_CTRL0, HOSTVM_INIT_REQ, mask_sh),\ - HUBBUB_SF(DCHVM_MEM_CTRL, HVM_GPUVMRET_PWR_REQ_DIS, mask_sh),\ - HUBBUB_SF(DCHVM_MEM_CTRL, HVM_GPUVMRET_FORCE_REQ, mask_sh),\ - HUBBUB_SF(DCHVM_MEM_CTRL, HVM_GPUVMRET_POWER_STATUS, mask_sh),\ - HUBBUB_SF(DCHVM_CLK_CTRL, HVM_DISPCLK_R_GATE_DIS, mask_sh),\ - HUBBUB_SF(DCHVM_CLK_CTRL, HVM_DISPCLK_G_GATE_DIS, mask_sh),\ - HUBBUB_SF(DCHVM_CLK_CTRL, HVM_DCFCLK_R_GATE_DIS, mask_sh),\ - HUBBUB_SF(DCHVM_CLK_CTRL, HVM_DCFCLK_G_GATE_DIS, mask_sh),\ - HUBBUB_SF(DCHVM_CLK_CTRL, TR_REQ_REQCLKREQ_MODE, mask_sh),\ - HUBBUB_SF(DCHVM_CLK_CTRL, TW_RSP_COMPCLKREQ_MODE, mask_sh),\ - HUBBUB_SF(DCHVM_RIOMMU_CTRL0, HOSTVM_PREFETCH_REQ, mask_sh),\ - HUBBUB_SF(DCHVM_RIOMMU_CTRL0, HOSTVM_POWERSTATUS, mask_sh),\ - HUBBUB_SF(DCHVM_RIOMMU_STAT0, RIOMMU_ACTIVE, mask_sh),\ - HUBBUB_SF(DCHVM_RIOMMU_STAT0, HOSTVM_PREFETCH_DONE, mask_sh),\ - HUBBUB_SF(DCHUBBUB_COMPBUF_CTRL, COMPBUF_SIZE, mask_sh),\ - HUBBUB_SF(DCHUBBUB_COMPBUF_CTRL, COMPBUF_SIZE_CURRENT, mask_sh),\ - HUBBUB_SF(DCHUBBUB_COMPBUF_CTRL, CONFIG_ERROR, mask_sh),\ - HUBBUB_SF(COMPBUF_RESERVED_SPACE, COMPBUF_RESERVED_SPACE_64B, mask_sh),\ - HUBBUB_SF(COMPBUF_RESERVED_SPACE, COMPBUF_RESERVED_SPACE_ZS, mask_sh),\ - HUBBUB_SF(DCHUBBUB_CLOCK_CNTL, DCHUBBUB_FGCG_REP_DIS, mask_sh),\ - HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A, DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A, mask_sh), \ - HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B, DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B, mask_sh), \ - HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C, DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C, mask_sh), \ - HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D, DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D, mask_sh), \ - HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A, DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A, mask_sh), \ - HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B, DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B, mask_sh), \ - HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C, DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C, mask_sh), \ - HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D, DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D, mask_sh), \ - HUBBUB_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_CSTATE_DEEPSLEEP_LEGACY_MODE, mask_sh), \ - HUBBUB_SF(DCHUBBUB_ARB_HOSTVM_CNTL, DCHUBBUB_ARB_MAX_QOS_COMMIT_THRESHOLD, mask_sh),\ - HUBBUB_SF(DCHUBBUB_ARB_DF_REQ_OUTSTAND, DCHUBBUB_ARB_MIN_REQ_OUTSTAND_COMMIT_THRESHOLD, mask_sh) - -void hubbub35_construct(struct dcn20_hubbub *hubbub2, - struct dc_context *ctx, - const struct dcn_hubbub_registers *hubbub_regs, - const struct dcn_hubbub_shift *hubbub_shift, - const struct dcn_hubbub_mask *hubbub_mask, - int det_size_kb, - int pixel_chunk_size_kb, - int config_return_buffer_size_kb); -#endif diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_hubp.c deleted file mode 100644 index 771fcd0d3b99..000000000000 --- a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_hubp.c +++ /dev/null @@ -1,241 +0,0 @@ -/* SPDX-License-Identifier: MIT */ -/* - * Copyright 2023 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -#include "dcn35_hubp.h" -#include "reg_helper.h" - -#define REG(reg)\ - hubp2->hubp_regs->reg - -#define CTX \ - hubp2->base.ctx - -#undef FN -#define FN(reg_name, field_name) \ - ((const struct dcn35_hubp2_shift *)hubp2->hubp_shift)->field_name, \ - ((const struct dcn35_hubp2_mask *)hubp2->hubp_mask)->field_name - -void hubp35_set_fgcg(struct hubp *hubp, bool enable) -{ - struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); - - REG_UPDATE(HUBP_CLK_CNTL, HUBP_FGCG_REP_DIS, !enable); -} - -static void hubp35_init(struct hubp *hubp) -{ - hubp3_init(hubp); - - hubp35_set_fgcg(hubp, hubp->ctx->dc->debug.enable_fine_grain_clock_gating.bits.dchub); - - /*do nothing for now for dcn3.5 or later*/ -} - -void hubp35_program_pixel_format( - struct hubp *hubp, - enum surface_pixel_format format) -{ - struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); - uint32_t green_bar = 1; - uint32_t red_bar = 3; - uint32_t blue_bar = 2; - - /* swap for ABGR format */ - if (format == SURFACE_PIXEL_FORMAT_GRPH_ABGR8888 - || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010 - || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS - || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616 - || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F) { - red_bar = 2; - blue_bar = 3; - } - - REG_UPDATE_3(HUBPRET_CONTROL, - CROSSBAR_SRC_Y_G, green_bar, - CROSSBAR_SRC_CB_B, blue_bar, - CROSSBAR_SRC_CR_R, red_bar); - - /* Mapping is same as ipp programming (cnvc) */ - - switch (format) { - case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: - REG_UPDATE(DCSURF_SURFACE_CONFIG, - SURFACE_PIXEL_FORMAT, 1); - break; - case SURFACE_PIXEL_FORMAT_GRPH_RGB565: - REG_UPDATE(DCSURF_SURFACE_CONFIG, - SURFACE_PIXEL_FORMAT, 3); - break; - case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: - case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: - REG_UPDATE(DCSURF_SURFACE_CONFIG, - SURFACE_PIXEL_FORMAT, 8); - break; - case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: - case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: - case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS: - REG_UPDATE(DCSURF_SURFACE_CONFIG, - SURFACE_PIXEL_FORMAT, 10); - break; - case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: - case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616: /* we use crossbar already */ - REG_UPDATE(DCSURF_SURFACE_CONFIG, - SURFACE_PIXEL_FORMAT, 26); /* ARGB16161616_UNORM */ - break; - case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: - case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:/*we use crossbar already*/ - REG_UPDATE(DCSURF_SURFACE_CONFIG, - SURFACE_PIXEL_FORMAT, 24); - break; - - case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: - REG_UPDATE(DCSURF_SURFACE_CONFIG, - SURFACE_PIXEL_FORMAT, 65); - break; - case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: - REG_UPDATE(DCSURF_SURFACE_CONFIG, - SURFACE_PIXEL_FORMAT, 64); - break; - case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: - REG_UPDATE(DCSURF_SURFACE_CONFIG, - SURFACE_PIXEL_FORMAT, 67); - break; - case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: - REG_UPDATE(DCSURF_SURFACE_CONFIG, - SURFACE_PIXEL_FORMAT, 66); - break; - case SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888: - REG_UPDATE(DCSURF_SURFACE_CONFIG, - SURFACE_PIXEL_FORMAT, 12); - break; - case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX: - REG_UPDATE(DCSURF_SURFACE_CONFIG, - SURFACE_PIXEL_FORMAT, 112); - break; - case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX: - REG_UPDATE(DCSURF_SURFACE_CONFIG, - SURFACE_PIXEL_FORMAT, 113); - break; - case SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010: - REG_UPDATE(DCSURF_SURFACE_CONFIG, - SURFACE_PIXEL_FORMAT, 114); - break; - case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT: - REG_UPDATE(DCSURF_SURFACE_CONFIG, - SURFACE_PIXEL_FORMAT, 118); - break; - case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT: - REG_UPDATE(DCSURF_SURFACE_CONFIG, - SURFACE_PIXEL_FORMAT, 119); - break; - case SURFACE_PIXEL_FORMAT_GRPH_RGBE: - REG_UPDATE_2(DCSURF_SURFACE_CONFIG, - SURFACE_PIXEL_FORMAT, 116, - ALPHA_PLANE_EN, 0); - break; - case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA: - REG_UPDATE_2(DCSURF_SURFACE_CONFIG, - SURFACE_PIXEL_FORMAT, 116, - ALPHA_PLANE_EN, 1); - break; - default: - BREAK_TO_DEBUGGER(); - break; - } - - /* don't see the need of program the xbar in DCN 1.0 */ -} - -void hubp35_program_surface_config( - struct hubp *hubp, - enum surface_pixel_format format, - union dc_tiling_info *tiling_info, - struct plane_size *plane_size, - enum dc_rotation_angle rotation, - struct dc_plane_dcc_param *dcc, - bool horizontal_mirror, - unsigned int compat_level) -{ - struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); - - hubp3_dcc_control_sienna_cichlid(hubp, dcc); - hubp3_program_tiling(hubp2, tiling_info, format); - hubp2_program_size(hubp, format, plane_size, dcc); - hubp2_program_rotation(hubp, rotation, horizontal_mirror); - hubp35_program_pixel_format(hubp, format); -} - -struct hubp_funcs dcn35_hubp_funcs = { - .hubp_enable_tripleBuffer = hubp2_enable_triplebuffer, - .hubp_is_triplebuffer_enabled = hubp2_is_triplebuffer_enabled, - .hubp_program_surface_flip_and_addr = hubp3_program_surface_flip_and_addr, - .hubp_program_surface_config = hubp35_program_surface_config, - .hubp_is_flip_pending = hubp2_is_flip_pending, - .hubp_setup = hubp3_setup, - .hubp_setup_interdependent = hubp2_setup_interdependent, - .hubp_set_vm_system_aperture_settings = hubp3_set_vm_system_aperture_settings, - .set_blank = hubp2_set_blank, - .dcc_control = hubp3_dcc_control, - .mem_program_viewport = min_set_viewport, - .set_cursor_attributes = hubp2_cursor_set_attributes, - .set_cursor_position = hubp2_cursor_set_position, - .hubp_clk_cntl = hubp2_clk_cntl, - .hubp_vtg_sel = hubp2_vtg_sel, - .dmdata_set_attributes = hubp3_dmdata_set_attributes, - .dmdata_load = hubp2_dmdata_load, - .dmdata_status_done = hubp2_dmdata_status_done, - .hubp_read_state = hubp3_read_state, - .hubp_clear_underflow = hubp2_clear_underflow, - .hubp_set_flip_control_surface_gsl = hubp2_set_flip_control_surface_gsl, - .hubp_init = hubp35_init, - .set_unbounded_requesting = hubp31_set_unbounded_requesting, - .hubp_soft_reset = hubp31_soft_reset, - .hubp_set_flip_int = hubp1_set_flip_int, - .hubp_in_blank = hubp1_in_blank, - .program_extended_blank = hubp31_program_extended_blank_value, -}; - -bool hubp35_construct( - struct dcn20_hubp *hubp2, - struct dc_context *ctx, - uint32_t inst, - const struct dcn_hubp2_registers *hubp_regs, - const struct dcn35_hubp2_shift *hubp_shift, - const struct dcn35_hubp2_mask *hubp_mask) -{ - hubp2->base.funcs = &dcn35_hubp_funcs; - hubp2->base.ctx = ctx; - hubp2->hubp_regs = hubp_regs; - hubp2->hubp_shift = (const struct dcn_hubp2_shift *)hubp_shift; - hubp2->hubp_mask = (const struct dcn_hubp2_mask *)hubp_mask; - hubp2->base.inst = inst; - hubp2->base.opp_id = OPP_ID_INVALID; - hubp2->base.mpcc_id = 0xf; - - return true; -} - - diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_hubp.h b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_hubp.h deleted file mode 100644 index 586b43aa5834..000000000000 --- a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_hubp.h +++ /dev/null @@ -1,75 +0,0 @@ -/* SPDX-License-Identifier: MIT */ -/* - * Copyright 2023 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -#ifndef __DC_HUBP_DCN35_H__ -#define __DC_HUBP_DCN35_H__ - -#include "dcn31/dcn31_hubp.h" -#include "dcn32/dcn32_hubp.h" -#define HUBP_MASK_SH_LIST_DCN35(mask_sh)\ - HUBP_MASK_SH_LIST_DCN32(mask_sh),\ - HUBP_SF(HUBP0_HUBP_CLK_CNTL, HUBP_FGCG_REP_DIS, mask_sh) - -#define DCN35_HUBP_REG_FIELD_VARIABLE_LIST(type) \ - struct { \ - DCN32_HUBP_REG_FIELD_VARIABLE_LIST(type); \ - type HUBP_FGCG_REP_DIS; \ - } - -struct dcn35_hubp2_shift { - DCN35_HUBP_REG_FIELD_VARIABLE_LIST(uint8_t); -}; - -struct dcn35_hubp2_mask { - DCN35_HUBP_REG_FIELD_VARIABLE_LIST(uint32_t); -}; - - -bool hubp35_construct( - struct dcn20_hubp *hubp2, - struct dc_context *ctx, - uint32_t inst, - const struct dcn_hubp2_registers *hubp_regs, - const struct dcn35_hubp2_shift *hubp_shift, - const struct dcn35_hubp2_mask *hubp_mask); - -void hubp35_set_fgcg(struct hubp *hubp, bool enable); - -void hubp35_program_pixel_format( - struct hubp *hubp, - enum surface_pixel_format format); - -void hubp35_program_surface_config( - struct hubp *hubp, - enum surface_pixel_format format, - union dc_tiling_info *tiling_info, - struct plane_size *plane_size, - enum dc_rotation_angle rotation, - struct dc_plane_dcc_param *dcc, - bool horizontal_mirror, - unsigned int compat_level); - -#endif /* __DC_HUBP_DCN35_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_mmhubbub.c b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_mmhubbub.c deleted file mode 100644 index 4317100564a4..000000000000 --- a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_mmhubbub.c +++ /dev/null @@ -1,59 +0,0 @@ -/* SPDX-License-Identifier: MIT */ -/* - * Copyright 2023 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -#include "dcn35_mmhubbub.h" -#include "reg_helper.h" - -#define REG(reg) \ - ((const struct dcn35_mmhubbub_registers *)(mcif_wb30->mcif_wb_regs)) \ - ->reg - -#define CTX mcif_wb30->base.ctx - -#undef FN -#define FN(reg_name, field_name) \ - ((const struct dcn35_mmhubbub_shift *)(mcif_wb30->mcif_wb_shift)) \ - ->field_name, \ - ((const struct dcn35_mmhubbub_mask *)(mcif_wb30->mcif_wb_mask)) \ - ->field_name - -void dcn35_mmhubbub_construct( - struct dcn30_mmhubbub *mcif_wb30, struct dc_context *ctx, - const struct dcn35_mmhubbub_registers *mcif_wb_regs, - const struct dcn35_mmhubbub_shift *mcif_wb_shift, - const struct dcn35_mmhubbub_mask *mcif_wb_mask, int inst) -{ - dcn32_mmhubbub_construct( - mcif_wb30, ctx, - (const struct dcn30_mmhubbub_registers *)(mcif_wb_regs), - (const struct dcn30_mmhubbub_shift *)(mcif_wb_shift), - (const struct dcn30_mmhubbub_mask *)(mcif_wb_mask), inst); -} - -void dcn35_mmhubbub_set_fgcg(struct dcn30_mmhubbub *mcif_wb30, bool enabled) -{ - REG_UPDATE(MMHUBBUB_CLOCK_CNTL, MMHUBBUB_FGCG_REP_DIS, !enabled); -} diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_mmhubbub.h b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_mmhubbub.h deleted file mode 100644 index 098e13e07272..000000000000 --- a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_mmhubbub.h +++ /dev/null @@ -1,75 +0,0 @@ -/* SPDX-License-Identifier: MIT */ -/* - * Copyright 2023 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -#ifndef __DCN35_MMHUBBUB_H -#define __DCN35_MMHUBBUB_H - -#include "mcif_wb.h" -#include "dcn32/dcn32_mmhubbub.h" - -#define MCIF_WB_REG_VARIABLE_LIST_DCN3_5 \ - MCIF_WB_REG_VARIABLE_LIST_DCN3_0; \ - uint32_t MMHUBBUB_CLOCK_CNTL - -#define MCIF_WB_COMMON_MASK_SH_LIST_DCN3_5(mask_sh) \ - MCIF_WB_COMMON_MASK_SH_LIST_DCN32(mask_sh), \ - SF(MMHUBBUB_CLOCK_CNTL, MMHUBBUB_TEST_CLK_SEL, mask_sh), \ - SF(MMHUBBUB_CLOCK_CNTL, DISPCLK_R_MMHUBBUB_GATE_DIS, mask_sh), \ - SF(MMHUBBUB_CLOCK_CNTL, DISPCLK_G_WBIF0_GATE_DIS, mask_sh), \ - SF(MMHUBBUB_CLOCK_CNTL, SOCCLK_G_WBIF0_GATE_DIS, mask_sh), \ - SF(MMHUBBUB_CLOCK_CNTL, MMHUBBUB_FGCG_REP_DIS, mask_sh) - -#define MCIF_WB_REG_FIELD_LIST_DCN3_5(type) \ - struct { \ - MCIF_WB_REG_FIELD_LIST_DCN3_0(type); \ - type MMHUBBUB_TEST_CLK_SEL; \ - type DISPCLK_R_MMHUBBUB_GATE_DIS; \ - type DISPCLK_G_WBIF0_GATE_DIS; \ - type SOCCLK_G_WBIF0_GATE_DIS; \ - type MMHUBBUB_FGCG_REP_DIS; \ - } - -struct dcn35_mmhubbub_registers { - MCIF_WB_REG_VARIABLE_LIST_DCN3_5; -}; - -struct dcn35_mmhubbub_mask { - MCIF_WB_REG_FIELD_LIST_DCN3_5(uint32_t); -}; - -struct dcn35_mmhubbub_shift { - MCIF_WB_REG_FIELD_LIST_DCN3_5(uint8_t); -}; - -void dcn35_mmhubbub_construct( - struct dcn30_mmhubbub *mcif_wb30, struct dc_context *ctx, - const struct dcn35_mmhubbub_registers *mcif_wb_regs, - const struct dcn35_mmhubbub_shift *mcif_wb_shift, - const struct dcn35_mmhubbub_mask *mcif_wb_mask, int inst); - -void dcn35_mmhubbub_set_fgcg(struct dcn30_mmhubbub *mcif_wb30, bool enabled); - -#endif // __DCN35_MMHUBBUB_H diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_opp.c b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_opp.c deleted file mode 100644 index 3542b51c9aac..000000000000 --- a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_opp.c +++ /dev/null @@ -1,53 +0,0 @@ -/* SPDX-License-Identifier: MIT */ -/* - * Copyright 2023 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -#include "dcn35_opp.h" -#include "reg_helper.h" - -#define REG(reg) ((const struct dcn35_opp_registers *)(oppn20->regs))->reg - -#undef FN -#define FN(reg_name, field_name) \ - ((const struct dcn35_opp_shift *)(oppn20->opp_shift))->field_name, \ - ((const struct dcn35_opp_mask *)(oppn20->opp_mask))->field_name - -#define CTX oppn20->base.ctx - -void dcn35_opp_construct(struct dcn20_opp *oppn20, struct dc_context *ctx, - uint32_t inst, const struct dcn35_opp_registers *regs, - const struct dcn35_opp_shift *opp_shift, - const struct dcn35_opp_mask *opp_mask) -{ - dcn20_opp_construct(oppn20, ctx, inst, - (const struct dcn20_opp_registers *)regs, - (const struct dcn20_opp_shift *)opp_shift, - (const struct dcn20_opp_mask *)opp_mask); -} - -void dcn35_opp_set_fgcg(struct dcn20_opp *oppn20, bool enable) -{ - REG_UPDATE(OPP_TOP_CLK_CONTROL, OPP_FGCG_REP_DIS, !enable); -} diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_opp.h b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_opp.h deleted file mode 100644 index a9a413527801..000000000000 --- a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_opp.h +++ /dev/null @@ -1,67 +0,0 @@ -/* SPDX-License-Identifier: MIT */ -/* - * Copyright 2023 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -#ifndef __DCN35_OPP_H -#define __DCN35_OPP_H - -#include "dcn20/dcn20_opp.h" - -#define OPP_REG_VARIABLE_LIST_DCN3_5 \ - OPP_REG_VARIABLE_LIST_DCN2_0; \ - uint32_t OPP_TOP_CLK_CONTROL - -#define OPP_MASK_SH_LIST_DCN35(mask_sh) \ - OPP_MASK_SH_LIST_DCN20(mask_sh), \ - OPP_SF(OPP_TOP_CLK_CONTROL, OPP_FGCG_REP_DIS, mask_sh) - -#define OPP_DCN35_REG_FIELD_LIST(type) \ - struct { \ - OPP_DCN20_REG_FIELD_LIST(type); \ - type OPP_FGCG_REP_DIS; \ - } - -struct dcn35_opp_registers { - OPP_REG_VARIABLE_LIST_DCN3_5; -}; - -struct dcn35_opp_shift { - OPP_DCN35_REG_FIELD_LIST(uint8_t); -}; - -struct dcn35_opp_mask { - OPP_DCN35_REG_FIELD_LIST(uint32_t); -}; - -void dcn35_opp_construct(struct dcn20_opp *oppn20, - struct dc_context *ctx, - uint32_t inst, - const struct dcn35_opp_registers *regs, - const struct dcn35_opp_shift *opp_shift, - const struct dcn35_opp_mask *opp_mask); - -void dcn35_opp_set_fgcg(struct dcn20_opp *oppn20, bool enable); - -#endif diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_pg_cntl.c b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_pg_cntl.c deleted file mode 100644 index 53bd0ae4bab5..000000000000 --- a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_pg_cntl.c +++ /dev/null @@ -1,551 +0,0 @@ -/* SPDX-License-Identifier: MIT */ -/* - * Copyright 2023 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -#include "reg_helper.h" -#include "core_types.h" -#include "dcn35_pg_cntl.h" -#include "dccg.h" - -#define TO_DCN_PG_CNTL(pg_cntl)\ - container_of(pg_cntl, struct dcn_pg_cntl, base) - -#define REG(reg) \ - (pg_cntl_dcn->regs->reg) - -#undef FN -#define FN(reg_name, field_name) \ - pg_cntl_dcn->pg_cntl_shift->field_name, pg_cntl_dcn->pg_cntl_mask->field_name - -#define CTX \ - pg_cntl_dcn->base.ctx -#define DC_LOGGER \ - pg_cntl->ctx->logger - -static bool pg_cntl35_dsc_pg_status(struct pg_cntl *pg_cntl, unsigned int dsc_inst) -{ - struct dcn_pg_cntl *pg_cntl_dcn = TO_DCN_PG_CNTL(pg_cntl); - uint32_t pwr_status = 0; - - if (pg_cntl->ctx->dc->debug.ignore_pg) - return true; - - switch (dsc_inst) { - case 0: /* DSC0 */ - REG_GET(DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, &pwr_status); - break; - case 1: /* DSC1 */ - REG_GET(DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, &pwr_status); - break; - case 2: /* DSC2 */ - REG_GET(DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, &pwr_status); - break; - case 3: /* DSC3 */ - REG_GET(DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, &pwr_status); - break; - default: - BREAK_TO_DEBUGGER(); - break; - } - - return pwr_status == 0; -} - -void pg_cntl35_dsc_pg_control(struct pg_cntl *pg_cntl, unsigned int dsc_inst, bool power_on) -{ - struct dcn_pg_cntl *pg_cntl_dcn = TO_DCN_PG_CNTL(pg_cntl); - uint32_t power_gate = power_on ? 0 : 1; - uint32_t pwr_status = power_on ? 0 : 2; - uint32_t org_ip_request_cntl = 0; - bool block_enabled; - - /*need to enable dscclk regardless DSC_PG*/ - if (pg_cntl->ctx->dc->res_pool->dccg->funcs->enable_dsc && power_on) - pg_cntl->ctx->dc->res_pool->dccg->funcs->enable_dsc( - pg_cntl->ctx->dc->res_pool->dccg, dsc_inst); - - if (pg_cntl->ctx->dc->debug.ignore_pg || - pg_cntl->ctx->dc->debug.disable_dsc_power_gate || - pg_cntl->ctx->dc->idle_optimizations_allowed) - return; - - block_enabled = pg_cntl35_dsc_pg_status(pg_cntl, dsc_inst); - if (power_on) { - if (block_enabled) - return; - } else { - if (!block_enabled) - return; - } - - REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); - if (org_ip_request_cntl == 0) - REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); - - switch (dsc_inst) { - case 0: /* DSC0 */ - REG_UPDATE(DOMAIN16_PG_CONFIG, - DOMAIN_POWER_GATE, power_gate); - - REG_WAIT(DOMAIN16_PG_STATUS, - DOMAIN_PGFSM_PWR_STATUS, pwr_status, - 1, 1000); - break; - case 1: /* DSC1 */ - REG_UPDATE(DOMAIN17_PG_CONFIG, - DOMAIN_POWER_GATE, power_gate); - - REG_WAIT(DOMAIN17_PG_STATUS, - DOMAIN_PGFSM_PWR_STATUS, pwr_status, - 1, 1000); - break; - case 2: /* DSC2 */ - REG_UPDATE(DOMAIN18_PG_CONFIG, - DOMAIN_POWER_GATE, power_gate); - - REG_WAIT(DOMAIN18_PG_STATUS, - DOMAIN_PGFSM_PWR_STATUS, pwr_status, - 1, 1000); - break; - case 3: /* DSC3 */ - REG_UPDATE(DOMAIN19_PG_CONFIG, - DOMAIN_POWER_GATE, power_gate); - - REG_WAIT(DOMAIN19_PG_STATUS, - DOMAIN_PGFSM_PWR_STATUS, pwr_status, - 1, 1000); - break; - default: - BREAK_TO_DEBUGGER(); - break; - } - - if (dsc_inst < MAX_PIPES) - pg_cntl->pg_pipe_res_enable[PG_DSC][dsc_inst] = power_on; - - if (pg_cntl->ctx->dc->res_pool->dccg->funcs->disable_dsc && !power_on) { - /*this is to disable dscclk*/ - pg_cntl->ctx->dc->res_pool->dccg->funcs->disable_dsc( - pg_cntl->ctx->dc->res_pool->dccg, dsc_inst); - } -} - -static bool pg_cntl35_hubp_dpp_pg_status(struct pg_cntl *pg_cntl, unsigned int hubp_dpp_inst) -{ - struct dcn_pg_cntl *pg_cntl_dcn = TO_DCN_PG_CNTL(pg_cntl); - uint32_t pwr_status = 0; - - switch (hubp_dpp_inst) { - case 0: - /* DPP0 & HUBP0 */ - REG_GET(DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, &pwr_status); - break; - case 1: - /* DPP1 & HUBP1 */ - REG_GET(DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, &pwr_status); - break; - case 2: - /* DPP2 & HUBP2 */ - REG_GET(DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, &pwr_status); - break; - case 3: - /* DPP3 & HUBP3 */ - REG_GET(DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, &pwr_status); - break; - default: - BREAK_TO_DEBUGGER(); - break; - } - - return pwr_status == 0; -} - -void pg_cntl35_hubp_dpp_pg_control(struct pg_cntl *pg_cntl, unsigned int hubp_dpp_inst, bool power_on) -{ - struct dcn_pg_cntl *pg_cntl_dcn = TO_DCN_PG_CNTL(pg_cntl); - uint32_t power_gate = power_on ? 0 : 1; - uint32_t pwr_status = power_on ? 0 : 2; - uint32_t org_ip_request_cntl; - bool block_enabled; - - if (pg_cntl->ctx->dc->debug.ignore_pg || - pg_cntl->ctx->dc->debug.disable_hubp_power_gate || - pg_cntl->ctx->dc->debug.disable_dpp_power_gate || - pg_cntl->ctx->dc->idle_optimizations_allowed) - return; - - block_enabled = pg_cntl35_hubp_dpp_pg_status(pg_cntl, hubp_dpp_inst); - if (power_on) { - if (block_enabled) - return; - } else { - if (!block_enabled) - return; - } - - REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); - if (org_ip_request_cntl == 0) - REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); - - switch (hubp_dpp_inst) { - case 0: - /* DPP0 & HUBP0 */ - REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, power_gate); - REG_WAIT(DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); - break; - case 1: - /* DPP1 & HUBP1 */ - REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, power_gate); - REG_WAIT(DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); - break; - case 2: - /* DPP2 & HUBP2 */ - REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, power_gate); - REG_WAIT(DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); - break; - case 3: - /* DPP3 & HUBP3 */ - REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, power_gate); - REG_WAIT(DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); - break; - default: - BREAK_TO_DEBUGGER(); - break; - } - - DC_LOG_DEBUG("HUBP DPP instance %d, power %s", hubp_dpp_inst, - power_on ? "ON" : "OFF"); - - if (hubp_dpp_inst < MAX_PIPES) { - pg_cntl->pg_pipe_res_enable[PG_HUBP][hubp_dpp_inst] = power_on; - pg_cntl->pg_pipe_res_enable[PG_DPP][hubp_dpp_inst] = power_on; - } -} - -static bool pg_cntl35_hpo_pg_status(struct pg_cntl *pg_cntl) -{ - struct dcn_pg_cntl *pg_cntl_dcn = TO_DCN_PG_CNTL(pg_cntl); - uint32_t pwr_status = 0; - - REG_GET(DOMAIN25_PG_STATUS, - DOMAIN_PGFSM_PWR_STATUS, &pwr_status); - - return pwr_status == 0; -} - -void pg_cntl35_hpo_pg_control(struct pg_cntl *pg_cntl, bool power_on) -{ - struct dcn_pg_cntl *pg_cntl_dcn = TO_DCN_PG_CNTL(pg_cntl); - uint32_t power_gate = power_on ? 0 : 1; - uint32_t pwr_status = power_on ? 0 : 2; - uint32_t org_ip_request_cntl; - uint32_t power_forceon; - bool block_enabled; - - if (pg_cntl->ctx->dc->debug.ignore_pg || - pg_cntl->ctx->dc->debug.disable_hpo_power_gate || - pg_cntl->ctx->dc->idle_optimizations_allowed) - return; - - block_enabled = pg_cntl35_hpo_pg_status(pg_cntl); - if (power_on) { - if (block_enabled) - return; - } else { - if (!block_enabled) - return; - } - - REG_GET(DOMAIN25_PG_CONFIG, DOMAIN_POWER_FORCEON, &power_forceon); - if (power_forceon) - return; - - REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); - if (org_ip_request_cntl == 0) - REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); - - REG_UPDATE(DOMAIN25_PG_CONFIG, DOMAIN_POWER_GATE, power_gate); - REG_WAIT(DOMAIN25_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); - - pg_cntl->pg_res_enable[PG_HPO] = power_on; -} - -static bool pg_cntl35_io_clk_status(struct pg_cntl *pg_cntl) -{ - struct dcn_pg_cntl *pg_cntl_dcn = TO_DCN_PG_CNTL(pg_cntl); - uint32_t pwr_status = 0; - - REG_GET(DOMAIN22_PG_STATUS, - DOMAIN_PGFSM_PWR_STATUS, &pwr_status); - - return pwr_status == 0; -} - -void pg_cntl35_io_clk_pg_control(struct pg_cntl *pg_cntl, bool power_on) -{ - struct dcn_pg_cntl *pg_cntl_dcn = TO_DCN_PG_CNTL(pg_cntl); - uint32_t power_gate = power_on ? 0 : 1; - uint32_t pwr_status = power_on ? 0 : 2; - uint32_t org_ip_request_cntl; - uint32_t power_forceon; - bool block_enabled; - - if (pg_cntl->ctx->dc->debug.ignore_pg || - pg_cntl->ctx->dc->idle_optimizations_allowed) - return; - - block_enabled = pg_cntl35_io_clk_status(pg_cntl); - if (power_on) { - if (block_enabled) - return; - } else { - if (!block_enabled) - return; - } - - REG_GET(DOMAIN22_PG_CONFIG, DOMAIN_POWER_FORCEON, &power_forceon); - if (power_forceon) - return; - - REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); - if (org_ip_request_cntl == 0) - REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); - - /* DCCG, DIO, DCIO */ - REG_UPDATE(DOMAIN22_PG_CONFIG, DOMAIN_POWER_GATE, power_gate); - REG_WAIT(DOMAIN22_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); - - pg_cntl->pg_res_enable[PG_DCCG] = power_on; - pg_cntl->pg_res_enable[PG_DIO] = power_on; - pg_cntl->pg_res_enable[PG_DCIO] = power_on; -} - -static bool pg_cntl35_plane_otg_status(struct pg_cntl *pg_cntl) -{ - struct dcn_pg_cntl *pg_cntl_dcn = TO_DCN_PG_CNTL(pg_cntl); - uint32_t pwr_status = 0; - - REG_GET(DOMAIN24_PG_STATUS, - DOMAIN_PGFSM_PWR_STATUS, &pwr_status); - - return pwr_status == 0; -} - -void pg_cntl35_mpcc_pg_control(struct pg_cntl *pg_cntl, - unsigned int mpcc_inst, bool power_on) -{ - if (pg_cntl->ctx->dc->idle_optimizations_allowed) - return; - - if (mpcc_inst >= 0 && mpcc_inst < MAX_PIPES) - pg_cntl->pg_pipe_res_enable[PG_MPCC][mpcc_inst] = power_on; -} - -void pg_cntl35_opp_pg_control(struct pg_cntl *pg_cntl, - unsigned int opp_inst, bool power_on) -{ - if (pg_cntl->ctx->dc->idle_optimizations_allowed) - return; - - if (opp_inst >= 0 && opp_inst < MAX_PIPES) - pg_cntl->pg_pipe_res_enable[PG_OPP][opp_inst] = power_on; -} - -void pg_cntl35_optc_pg_control(struct pg_cntl *pg_cntl, - unsigned int optc_inst, bool power_on) -{ - if (pg_cntl->ctx->dc->idle_optimizations_allowed) - return; - - if (optc_inst >= 0 && optc_inst < MAX_PIPES) - pg_cntl->pg_pipe_res_enable[PG_OPTC][optc_inst] = power_on; -} - -void pg_cntl35_plane_otg_pg_control(struct pg_cntl *pg_cntl, bool power_on) -{ - struct dcn_pg_cntl *pg_cntl_dcn = TO_DCN_PG_CNTL(pg_cntl); - uint32_t power_gate = power_on ? 0 : 1; - uint32_t pwr_status = power_on ? 0 : 2; - uint32_t org_ip_request_cntl; - int i; - bool block_enabled; - bool all_mpcc_disabled = true, all_opp_disabled = true; - bool all_optc_disabled = true, all_stream_disabled = true; - - if (pg_cntl->ctx->dc->debug.ignore_pg || - pg_cntl->ctx->dc->debug.disable_optc_power_gate || - pg_cntl->ctx->dc->idle_optimizations_allowed) - return; - - block_enabled = pg_cntl35_plane_otg_status(pg_cntl); - if (power_on) { - if (block_enabled) - return; - } else { - if (!block_enabled) - return; - } - - for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) { - struct pipe_ctx *pipe_ctx = &pg_cntl->ctx->dc->current_state->res_ctx.pipe_ctx[i]; - - if (pipe_ctx) { - if (pipe_ctx->stream) - all_stream_disabled = false; - } - - if (pg_cntl->pg_pipe_res_enable[PG_MPCC][i]) - all_mpcc_disabled = false; - - if (pg_cntl->pg_pipe_res_enable[PG_OPP][i]) - all_opp_disabled = false; - - if (pg_cntl->pg_pipe_res_enable[PG_OPTC][i]) - all_optc_disabled = false; - } - - if (!power_on) { - if (!all_mpcc_disabled || !all_opp_disabled || !all_optc_disabled - || !all_stream_disabled || pg_cntl->pg_res_enable[PG_DWB]) - return; - } - - REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); - if (org_ip_request_cntl == 0) - REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); - - /* MPC, OPP, OPTC, DWB */ - REG_UPDATE(DOMAIN24_PG_CONFIG, DOMAIN_POWER_GATE, power_gate); - REG_WAIT(DOMAIN24_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); - - for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) { - pg_cntl->pg_pipe_res_enable[PG_MPCC][i] = power_on; - pg_cntl->pg_pipe_res_enable[PG_OPP][i] = power_on; - pg_cntl->pg_pipe_res_enable[PG_OPTC][i] = power_on; - } - pg_cntl->pg_res_enable[PG_DWB] = power_on; -} - -void pg_cntl35_dwb_pg_control(struct pg_cntl *pg_cntl, bool power_on) -{ - if (pg_cntl->ctx->dc->idle_optimizations_allowed) - return; - - pg_cntl->pg_res_enable[PG_DWB] = power_on; -} - -static bool pg_cntl35_mem_status(struct pg_cntl *pg_cntl) -{ - struct dcn_pg_cntl *pg_cntl_dcn = TO_DCN_PG_CNTL(pg_cntl); - uint32_t pwr_status = 0; - - REG_GET(DOMAIN23_PG_STATUS, - DOMAIN_PGFSM_PWR_STATUS, &pwr_status); - - return pwr_status == 0; -} - -void pg_cntl35_init_pg_status(struct pg_cntl *pg_cntl) -{ - int i = 0; - bool block_enabled; - - pg_cntl->pg_res_enable[PG_HPO] = pg_cntl35_hpo_pg_status(pg_cntl); - - block_enabled = pg_cntl35_io_clk_status(pg_cntl); - pg_cntl->pg_res_enable[PG_DCCG] = block_enabled; - pg_cntl->pg_res_enable[PG_DIO] = block_enabled; - pg_cntl->pg_res_enable[PG_DCIO] = block_enabled; - - block_enabled = pg_cntl35_mem_status(pg_cntl); - pg_cntl->pg_res_enable[PG_DCHUBBUB] = block_enabled; - pg_cntl->pg_res_enable[PG_DCHVM] = block_enabled; - - for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) { - block_enabled = pg_cntl35_hubp_dpp_pg_status(pg_cntl, i); - pg_cntl->pg_pipe_res_enable[PG_HUBP][i] = block_enabled; - pg_cntl->pg_pipe_res_enable[PG_DPP][i] = block_enabled; - - block_enabled = pg_cntl35_dsc_pg_status(pg_cntl, i); - pg_cntl->pg_pipe_res_enable[PG_DSC][i] = block_enabled; - } - - block_enabled = pg_cntl35_plane_otg_status(pg_cntl); - for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) { - pg_cntl->pg_pipe_res_enable[PG_MPCC][i] = block_enabled; - pg_cntl->pg_pipe_res_enable[PG_OPP][i] = block_enabled; - pg_cntl->pg_pipe_res_enable[PG_OPTC][i] = block_enabled; - } - pg_cntl->pg_res_enable[PG_DWB] = block_enabled; -} - -static const struct pg_cntl_funcs pg_cntl35_funcs = { - .init_pg_status = pg_cntl35_init_pg_status, - .dsc_pg_control = pg_cntl35_dsc_pg_control, - .hubp_dpp_pg_control = pg_cntl35_hubp_dpp_pg_control, - .hpo_pg_control = pg_cntl35_hpo_pg_control, - .io_clk_pg_control = pg_cntl35_io_clk_pg_control, - .plane_otg_pg_control = pg_cntl35_plane_otg_pg_control, - .mpcc_pg_control = pg_cntl35_mpcc_pg_control, - .opp_pg_control = pg_cntl35_opp_pg_control, - .optc_pg_control = pg_cntl35_optc_pg_control, - .dwb_pg_control = pg_cntl35_dwb_pg_control -}; - -struct pg_cntl *pg_cntl35_create( - struct dc_context *ctx, - const struct pg_cntl_registers *regs, - const struct pg_cntl_shift *pg_cntl_shift, - const struct pg_cntl_mask *pg_cntl_mask) -{ - struct dcn_pg_cntl *pg_cntl_dcn = kzalloc(sizeof(*pg_cntl_dcn), GFP_KERNEL); - struct pg_cntl *base; - - if (pg_cntl_dcn == NULL) { - BREAK_TO_DEBUGGER(); - return NULL; - } - - base = &pg_cntl_dcn->base; - base->ctx = ctx; - base->funcs = &pg_cntl35_funcs; - - pg_cntl_dcn->regs = regs; - pg_cntl_dcn->pg_cntl_shift = pg_cntl_shift; - pg_cntl_dcn->pg_cntl_mask = pg_cntl_mask; - - memset(base->pg_pipe_res_enable, 0, PG_HW_PIPE_RESOURCES_NUM_ELEMENT * MAX_PIPES * sizeof(bool)); - memset(base->pg_res_enable, 0, PG_HW_RESOURCES_NUM_ELEMENT * sizeof(bool)); - - return &pg_cntl_dcn->base; -} - -void dcn_pg_cntl_destroy(struct pg_cntl **pg_cntl) -{ - struct dcn_pg_cntl *pg_cntl_dcn = TO_DCN_PG_CNTL(*pg_cntl); - - kfree(pg_cntl_dcn); - *pg_cntl = NULL; -} diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_pg_cntl.h b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_pg_cntl.h deleted file mode 100644 index 3de240884d22..000000000000 --- a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_pg_cntl.h +++ /dev/null @@ -1,195 +0,0 @@ -/* SPDX-License-Identifier: MIT */ -/* - * Copyright 2023 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -#ifndef _DCN35_PG_CNTL_H_ -#define _DCN35_PG_CNTL_H_ - -#include "pg_cntl.h" - -#define PG_CNTL_REG_LIST_DCN35()\ - SR(DOMAIN0_PG_CONFIG), \ - SR(DOMAIN1_PG_CONFIG), \ - SR(DOMAIN2_PG_CONFIG), \ - SR(DOMAIN3_PG_CONFIG), \ - SR(DOMAIN16_PG_CONFIG), \ - SR(DOMAIN17_PG_CONFIG), \ - SR(DOMAIN18_PG_CONFIG), \ - SR(DOMAIN19_PG_CONFIG), \ - SR(DOMAIN22_PG_CONFIG), \ - SR(DOMAIN23_PG_CONFIG), \ - SR(DOMAIN24_PG_CONFIG), \ - SR(DOMAIN25_PG_CONFIG), \ - SR(DOMAIN0_PG_STATUS), \ - SR(DOMAIN1_PG_STATUS), \ - SR(DOMAIN2_PG_STATUS), \ - SR(DOMAIN3_PG_STATUS), \ - SR(DOMAIN16_PG_STATUS), \ - SR(DOMAIN17_PG_STATUS), \ - SR(DOMAIN18_PG_STATUS), \ - SR(DOMAIN19_PG_STATUS), \ - SR(DOMAIN22_PG_STATUS), \ - SR(DOMAIN23_PG_STATUS), \ - SR(DOMAIN24_PG_STATUS), \ - SR(DOMAIN25_PG_STATUS), \ - SR(DC_IP_REQUEST_CNTL) - -#define PG_CNTL_SF(reg_name, field_name, post_fix)\ - .field_name = reg_name ## __ ## field_name ## post_fix - -#define PG_CNTL_MASK_SH_LIST_DCN35(mask_sh) \ - PG_CNTL_SF(DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ - PG_CNTL_SF(DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ - PG_CNTL_SF(DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ - PG_CNTL_SF(DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ - PG_CNTL_SF(DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ - PG_CNTL_SF(DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ - PG_CNTL_SF(DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ - PG_CNTL_SF(DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ - PG_CNTL_SF(DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ - PG_CNTL_SF(DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ - PG_CNTL_SF(DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ - PG_CNTL_SF(DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ - PG_CNTL_SF(DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ - PG_CNTL_SF(DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ - PG_CNTL_SF(DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ - PG_CNTL_SF(DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ - PG_CNTL_SF(DOMAIN22_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ - PG_CNTL_SF(DOMAIN22_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ - PG_CNTL_SF(DOMAIN23_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ - PG_CNTL_SF(DOMAIN23_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ - PG_CNTL_SF(DOMAIN24_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ - PG_CNTL_SF(DOMAIN24_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ - PG_CNTL_SF(DOMAIN25_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ - PG_CNTL_SF(DOMAIN25_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ - PG_CNTL_SF(DOMAIN0_PG_STATUS, DOMAIN_DESIRED_PWR_STATE, mask_sh), \ - PG_CNTL_SF(DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ - PG_CNTL_SF(DOMAIN1_PG_STATUS, DOMAIN_DESIRED_PWR_STATE, mask_sh), \ - PG_CNTL_SF(DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ - PG_CNTL_SF(DOMAIN2_PG_STATUS, DOMAIN_DESIRED_PWR_STATE, mask_sh), \ - PG_CNTL_SF(DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ - PG_CNTL_SF(DOMAIN3_PG_STATUS, DOMAIN_DESIRED_PWR_STATE, mask_sh), \ - PG_CNTL_SF(DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ - PG_CNTL_SF(DOMAIN16_PG_STATUS, DOMAIN_DESIRED_PWR_STATE, mask_sh), \ - PG_CNTL_SF(DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ - PG_CNTL_SF(DOMAIN17_PG_STATUS, DOMAIN_DESIRED_PWR_STATE, mask_sh), \ - PG_CNTL_SF(DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ - PG_CNTL_SF(DOMAIN18_PG_STATUS, DOMAIN_DESIRED_PWR_STATE, mask_sh), \ - PG_CNTL_SF(DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ - PG_CNTL_SF(DOMAIN19_PG_STATUS, DOMAIN_DESIRED_PWR_STATE, mask_sh), \ - PG_CNTL_SF(DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ - PG_CNTL_SF(DOMAIN22_PG_STATUS, DOMAIN_DESIRED_PWR_STATE, mask_sh), \ - PG_CNTL_SF(DOMAIN22_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ - PG_CNTL_SF(DOMAIN23_PG_STATUS, DOMAIN_DESIRED_PWR_STATE, mask_sh), \ - PG_CNTL_SF(DOMAIN23_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ - PG_CNTL_SF(DOMAIN24_PG_STATUS, DOMAIN_DESIRED_PWR_STATE, mask_sh), \ - PG_CNTL_SF(DOMAIN24_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ - PG_CNTL_SF(DOMAIN25_PG_STATUS, DOMAIN_DESIRED_PWR_STATE, mask_sh), \ - PG_CNTL_SF(DOMAIN25_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ - PG_CNTL_SF(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh) - -#define PG_CNTL_REG_FIELD_LIST(type) \ - type IPS2;\ - type IPS1;\ - type IPS0;\ - type IPS0_All - -#define PG_CNTL_DCN35_REG_FIELD_LIST(type) \ - type IP_REQUEST_EN; \ - type DOMAIN_POWER_FORCEON; \ - type DOMAIN_POWER_GATE; \ - type DOMAIN_DESIRED_PWR_STATE; \ - type DOMAIN_PGFSM_PWR_STATUS - -struct pg_cntl_shift { - PG_CNTL_REG_FIELD_LIST(uint8_t); - PG_CNTL_DCN35_REG_FIELD_LIST(uint8_t); -}; - -struct pg_cntl_mask { - PG_CNTL_REG_FIELD_LIST(uint32_t); - PG_CNTL_DCN35_REG_FIELD_LIST(uint32_t); -}; - -struct pg_cntl_registers { - uint32_t LONO_STATE; - uint32_t DC_IP_REQUEST_CNTL; - uint32_t DOMAIN0_PG_CONFIG; - uint32_t DOMAIN1_PG_CONFIG; - uint32_t DOMAIN2_PG_CONFIG; - uint32_t DOMAIN3_PG_CONFIG; - uint32_t DOMAIN16_PG_CONFIG; - uint32_t DOMAIN17_PG_CONFIG; - uint32_t DOMAIN18_PG_CONFIG; - uint32_t DOMAIN19_PG_CONFIG; - uint32_t DOMAIN22_PG_CONFIG; - uint32_t DOMAIN23_PG_CONFIG; - uint32_t DOMAIN24_PG_CONFIG; - uint32_t DOMAIN25_PG_CONFIG; - uint32_t DOMAIN0_PG_STATUS; - uint32_t DOMAIN1_PG_STATUS; - uint32_t DOMAIN2_PG_STATUS; - uint32_t DOMAIN3_PG_STATUS; - uint32_t DOMAIN16_PG_STATUS; - uint32_t DOMAIN17_PG_STATUS; - uint32_t DOMAIN18_PG_STATUS; - uint32_t DOMAIN19_PG_STATUS; - uint32_t DOMAIN22_PG_STATUS; - uint32_t DOMAIN23_PG_STATUS; - uint32_t DOMAIN24_PG_STATUS; - uint32_t DOMAIN25_PG_STATUS; -}; - -struct dcn_pg_cntl { - struct pg_cntl base; - const struct pg_cntl_registers *regs; - const struct pg_cntl_shift *pg_cntl_shift; - const struct pg_cntl_mask *pg_cntl_mask; -}; - -void pg_cntl35_dsc_pg_control(struct pg_cntl *pg_cntl, unsigned int dsc_inst, bool power_on); -void pg_cntl35_hubp_dpp_pg_control(struct pg_cntl *pg_cntl, - unsigned int hubp_dpp_inst, bool power_on); -void pg_cntl35_hpo_pg_control(struct pg_cntl *pg_cntl, bool power_on); -void pg_cntl35_io_clk_pg_control(struct pg_cntl *pg_cntl, bool power_on); -void pg_cntl35_plane_otg_pg_control(struct pg_cntl *pg_cntl, bool power_on); -void pg_cntl35_mpcc_pg_control(struct pg_cntl *pg_cntl, - unsigned int mpcc_inst, bool power_on); -void pg_cntl35_opp_pg_control(struct pg_cntl *pg_cntl, - unsigned int opp_inst, bool power_on); -void pg_cntl35_optc_pg_control(struct pg_cntl *pg_cntl, - unsigned int optc_inst, bool power_on); -void pg_cntl35_dwb_pg_control(struct pg_cntl *pg_cntl, bool power_on); -void pg_cntl35_init_pg_status(struct pg_cntl *pg_cntl); - -struct pg_cntl *pg_cntl35_create( - struct dc_context *ctx, - const struct pg_cntl_registers *regs, - const struct pg_cntl_shift *pg_cntl_shift, - const struct pg_cntl_mask *pg_cntl_mask); - -void dcn_pg_cntl_destroy(struct pg_cntl **pg_cntl); - -#endif /* DCN35_PG_CNTL */ |