diff options
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_pch_display.c')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_pch_display.c | 21 |
1 files changed, 11 insertions, 10 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c index 1743ebf551cb..3456c794e0e7 100644 --- a/drivers/gpu/drm/i915/display/intel_pch_display.c +++ b/drivers/gpu/drm/i915/display/intel_pch_display.c @@ -10,6 +10,7 @@ #include "intel_crt.h" #include "intel_crt_regs.h" #include "intel_de.h" +#include "intel_display_regs.h" #include "intel_display_types.h" #include "intel_dpll.h" #include "intel_fdi.h" @@ -251,7 +252,7 @@ static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state) u32 val, pipeconf_val; /* Make sure PCH DPLL is enabled */ - assert_shared_dpll_enabled(display, crtc_state->shared_dpll); + assert_dpll_enabled(display, crtc_state->intel_dpll); /* FDI must be feeding us bits for PCH ports */ assert_fdi_tx_enabled(display, pipe); @@ -381,8 +382,8 @@ void ilk_pch_enable(struct intel_atomic_state *state, temp = intel_de_read(display, PCH_DPLL_SEL); temp |= TRANS_DPLL_ENABLE(pipe); sel = TRANS_DPLLB_SEL(pipe); - if (crtc_state->shared_dpll == - intel_get_shared_dpll_by_id(display, DPLL_ID_PCH_PLL_B)) + if (crtc_state->intel_dpll == + intel_get_dpll_by_id(display, DPLL_ID_PCH_PLL_B)) temp |= sel; else temp &= ~sel; @@ -394,11 +395,11 @@ void ilk_pch_enable(struct intel_atomic_state *state, * transcoder, and we actually should do this to not upset any PCH * transcoder that already use the clock when we share it. * - * Note that enable_shared_dpll tries to do the right thing, but - * get_shared_dpll unconditionally resets the pll - we need that + * Note that dpll_enable tries to do the right thing, but + * get_dpll unconditionally resets the pll - we need that * to have the right LVDS enable sequence. */ - intel_enable_shared_dpll(crtc_state); + intel_dpll_enable(crtc_state); /* set transcoder timing, panel must allow it */ assert_pps_unlocked(display, pipe); @@ -472,7 +473,7 @@ void ilk_pch_post_disable(struct intel_atomic_state *state, ilk_fdi_pll_disable(crtc); - intel_disable_shared_dpll(old_crtc_state); + intel_dpll_disable(old_crtc_state); } static void ilk_pch_clock_get(struct intel_crtc_state *crtc_state) @@ -496,7 +497,7 @@ void ilk_pch_get_config(struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(crtc_state); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct intel_shared_dpll *pll; + struct intel_dpll *pll; enum pipe pipe = crtc->pipe; enum intel_dpll_id pll_id; bool pll_active; @@ -528,8 +529,8 @@ void ilk_pch_get_config(struct intel_crtc_state *crtc_state) pll_id = DPLL_ID_PCH_PLL_A; } - crtc_state->shared_dpll = intel_get_shared_dpll_by_id(display, pll_id); - pll = crtc_state->shared_dpll; + crtc_state->intel_dpll = intel_get_dpll_by_id(display, pll_id); + pll = crtc_state->intel_dpll; pll_active = intel_dpll_get_hw_state(display, pll, &crtc_state->dpll_hw_state); |