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path: root/drivers/gpu/drm/i915/gem/i915_gem_domain.c
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Diffstat (limited to 'drivers/gpu/drm/i915/gem/i915_gem_domain.c')
-rw-r--r--drivers/gpu/drm/i915/gem/i915_gem_domain.c20
1 files changed, 5 insertions, 15 deletions
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_domain.c b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
index 3770828f2eaf..7a0cc51923b3 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_domain.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
@@ -1,6 +1,5 @@
+// SPDX-License-Identifier: MIT
/*
- * SPDX-License-Identifier: MIT
- *
* Copyright © 2014-2016 Intel Corporation
*/
@@ -18,8 +17,6 @@
#include "i915_gem_object_frontbuffer.h"
#include "i915_vma.h"
-#define VTD_GUARD (168u * I915_GTT_PAGE_SIZE) /* 168 or tile-row PTE padding */
-
static bool gpu_write_needs_clflush(struct drm_i915_gem_object *obj)
{
struct drm_i915_private *i915 = to_i915(obj->base.dev);
@@ -276,7 +273,7 @@ int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
* For objects created by userspace through GEM_CREATE with pat_index
* set by set_pat extension, simply return 0 here without touching
* the cache setting, because such objects should have an immutable
- * cache setting by desgin and always managed by userspace.
+ * cache setting by design and always managed by userspace.
*/
if (i915_gem_object_has_cache_level(obj, cache_level))
return 0;
@@ -424,7 +421,7 @@ out:
struct i915_vma *
i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
struct i915_gem_ww_ctx *ww,
- u32 alignment,
+ u32 alignment, unsigned int guard,
const struct i915_gtt_view *view,
unsigned int flags)
{
@@ -453,15 +450,8 @@ i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
return ERR_PTR(ret);
/* VT-d may overfetch before/after the vma, so pad with scratch */
- if (intel_scanout_needs_vtd_wa(i915)) {
- unsigned int guard = VTD_GUARD;
-
- if (i915_gem_object_is_tiled(obj))
- guard = max(guard,
- i915_gem_object_get_tile_row_size(obj));
-
- flags |= PIN_OFFSET_GUARD | guard;
- }
+ if (guard)
+ flags |= PIN_OFFSET_GUARD | (guard * I915_GTT_PAGE_SIZE);
/*
* As the user may map the buffer once pinned in the display plane