diff options
Diffstat (limited to 'drivers/net/ethernet/hisilicon/hns3')
34 files changed, 2991 insertions, 2734 deletions
diff --git a/drivers/net/ethernet/hisilicon/hns3/Makefile b/drivers/net/ethernet/hisilicon/hns3/Makefile index e214bfaece1f..e8af26da1fc1 100644 --- a/drivers/net/ethernet/hisilicon/hns3/Makefile +++ b/drivers/net/ethernet/hisilicon/hns3/Makefile @@ -3,7 +3,7 @@ # Makefile for the HISILICON network device drivers. # -ccflags-y += -I$(srctree)/$(src) +ccflags-y += -I$(src) ccflags-y += -I$(srctree)/drivers/net/ethernet/hisilicon/hns3/hns3pf ccflags-y += -I$(srctree)/drivers/net/ethernet/hisilicon/hns3/hns3vf ccflags-y += -I$(srctree)/drivers/net/ethernet/hisilicon/hns3/hns3_common @@ -15,15 +15,14 @@ hns3-objs = hns3_enet.o hns3_ethtool.o hns3_debugfs.o hns3-$(CONFIG_HNS3_DCB) += hns3_dcbnl.o -obj-$(CONFIG_HNS3_HCLGEVF) += hclgevf.o +obj-$(CONFIG_HNS3_HCLGEVF) += hclgevf.o hclge-common.o -hclgevf-objs = hns3vf/hclgevf_main.o hns3vf/hclgevf_mbx.o hns3vf/hclgevf_devlink.o hns3vf/hclgevf_regs.o \ - hns3_common/hclge_comm_cmd.o hns3_common/hclge_comm_rss.o hns3_common/hclge_comm_tqp_stats.o +hclge-common-objs += hns3_common/hclge_comm_cmd.o hns3_common/hclge_comm_rss.o hns3_common/hclge_comm_tqp_stats.o -obj-$(CONFIG_HNS3_HCLGE) += hclge.o +hclgevf-objs = hns3vf/hclgevf_main.o hns3vf/hclgevf_mbx.o hns3vf/hclgevf_devlink.o hns3vf/hclgevf_regs.o + +obj-$(CONFIG_HNS3_HCLGE) += hclge.o hclge-common.o hclge-objs = hns3pf/hclge_main.o hns3pf/hclge_mdio.o hns3pf/hclge_tm.o hns3pf/hclge_regs.o \ hns3pf/hclge_mbx.o hns3pf/hclge_err.o hns3pf/hclge_debugfs.o hns3pf/hclge_ptp.o hns3pf/hclge_devlink.o \ - hns3_common/hclge_comm_cmd.o hns3_common/hclge_comm_rss.o hns3_common/hclge_comm_tqp_stats.o - hclge-$(CONFIG_HNS3_DCB) += hns3pf/hclge_dcb.o diff --git a/drivers/net/ethernet/hisilicon/hns3/hnae3.c b/drivers/net/ethernet/hisilicon/hns3/hnae3.c index 67b0bf310daa..b25fb400f476 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hnae3.c +++ b/drivers/net/ethernet/hisilicon/hns3/hnae3.c @@ -25,8 +25,11 @@ void hnae3_unregister_ae_algo_prepare(struct hnae3_ae_algo *ae_algo) pci_id = pci_match_id(ae_algo->pdev_id_table, ae_dev->pdev); if (!pci_id) continue; - if (IS_ENABLED(CONFIG_PCI_IOV)) + if (IS_ENABLED(CONFIG_PCI_IOV)) { + device_lock(&ae_dev->pdev->dev); pci_disable_sriov(ae_dev->pdev); + device_unlock(&ae_dev->pdev->dev); + } } } EXPORT_SYMBOL(hnae3_unregister_ae_algo_prepare); @@ -37,6 +40,21 @@ EXPORT_SYMBOL(hnae3_unregister_ae_algo_prepare); */ static DEFINE_MUTEX(hnae3_common_lock); +/* ensure the drivers being unloaded one by one */ +static DEFINE_MUTEX(hnae3_unload_lock); + +void hnae3_acquire_unload_lock(void) +{ + mutex_lock(&hnae3_unload_lock); +} +EXPORT_SYMBOL(hnae3_acquire_unload_lock); + +void hnae3_release_unload_lock(void) +{ + mutex_unlock(&hnae3_unload_lock); +} +EXPORT_SYMBOL(hnae3_release_unload_lock); + static bool hnae3_client_match(enum hnae3_client_type client_type) { if (client_type == HNAE3_CLIENT_KNIC || diff --git a/drivers/net/ethernet/hisilicon/hns3/hnae3.h b/drivers/net/ethernet/hisilicon/hns3/hnae3.h index f19f1e1d1f9f..3b548f71fa8a 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hnae3.h +++ b/drivers/net/ethernet/hisilicon/hns3/hnae3.h @@ -104,6 +104,7 @@ enum HNAE3_DEV_CAP_BITS { HNAE3_DEV_SUPPORT_WOL_B, HNAE3_DEV_SUPPORT_TM_FLUSH_B, HNAE3_DEV_SUPPORT_VF_FAULT_B, + HNAE3_DEV_SUPPORT_ERR_MOD_GEN_REG_B, }; #define hnae3_ae_dev_fd_supported(ae_dev) \ @@ -181,6 +182,9 @@ enum HNAE3_DEV_CAP_BITS { #define hnae3_ae_dev_vf_fault_supported(ae_dev) \ test_bit(HNAE3_DEV_SUPPORT_VF_FAULT_B, (ae_dev)->caps) +#define hnae3_ae_dev_gen_reg_dfx_supported(hdev) \ + test_bit(HNAE3_DEV_SUPPORT_ERR_MOD_GEN_REG_B, (hdev)->ae_dev->caps) + enum HNAE3_PF_CAP_BITS { HNAE3_PF_SUPPORT_VLAN_FLTR_MDF_B = 0, }; @@ -335,6 +339,10 @@ enum hnae3_dbg_cmd { HNAE3_DBG_CMD_UNKNOWN, }; +#define hnae3_seq_file_to_ae_dev(s) (dev_get_drvdata((s)->private)) +#define hnae3_seq_file_to_handle(s) \ + (((struct hnae3_ae_dev *)hnae3_seq_file_to_ae_dev(s))->handle) + enum hnae3_tc_map_mode { HNAE3_TC_MAP_MODE_PRIO, HNAE3_TC_MAP_MODE_DSCP, @@ -362,6 +370,15 @@ struct hnae3_vector_info { #define HNAE3_FW_VERSION_BYTE0_SHIFT 0 #define HNAE3_FW_VERSION_BYTE0_MASK GENMASK(7, 0) +#define HNAE3_SCC_VERSION_BYTE3_SHIFT 24 +#define HNAE3_SCC_VERSION_BYTE3_MASK GENMASK(31, 24) +#define HNAE3_SCC_VERSION_BYTE2_SHIFT 16 +#define HNAE3_SCC_VERSION_BYTE2_MASK GENMASK(23, 16) +#define HNAE3_SCC_VERSION_BYTE1_SHIFT 8 +#define HNAE3_SCC_VERSION_BYTE1_MASK GENMASK(15, 8) +#define HNAE3_SCC_VERSION_BYTE0_SHIFT 0 +#define HNAE3_SCC_VERSION_BYTE0_MASK GENMASK(7, 0) + struct hnae3_ring_chain_node { struct hnae3_ring_chain_node *next; u32 tqp_index; @@ -421,8 +438,11 @@ struct hnae3_ae_dev { u32 dev_version; DECLARE_BITMAP(caps, HNAE3_DEV_CAPS_MAX_NUM); void *priv; + struct hnae3_handle *handle; }; +typedef int (*read_func)(struct seq_file *s, void *data); + /* This struct defines the operation on the handle. * * init_ae_dev(): (mandatory) @@ -567,8 +587,6 @@ struct hnae3_ae_dev { * Delete clsflower rule * cls_flower_active * Check if any cls flower rule exist - * dbg_read_cmd - * Execute debugfs read command. * set_tx_hwts_info * Save information for 1588 tx packet * get_rx_hwts @@ -581,6 +599,8 @@ struct hnae3_ae_dev { * Get wake on lan info * set_wol * Config wake on lan + * dbg_get_read_func + * Return the read func for debugfs seq file */ struct hnae3_ae_ops { int (*init_ae_dev)(struct hnae3_ae_dev *ae_dev); @@ -664,7 +684,7 @@ struct hnae3_ae_ops { void (*get_mac_stats)(struct hnae3_handle *handle, struct hns3_mac_stats *mac_stats); void (*get_strings)(struct hnae3_handle *handle, - u32 stringset, u8 *data); + u32 stringset, u8 **data); int (*get_sset_count)(struct hnae3_handle *handle, int stringset); void (*get_regs)(struct hnae3_handle *handle, u32 *version, @@ -677,9 +697,9 @@ struct hnae3_ae_ops { int (*set_rss)(struct hnae3_handle *handle, const u32 *indir, const u8 *key, const u8 hfunc); int (*set_rss_tuple)(struct hnae3_handle *handle, - struct ethtool_rxnfc *cmd); + const struct ethtool_rxfh_fields *cmd); int (*get_rss_tuple)(struct hnae3_handle *handle, - struct ethtool_rxnfc *cmd); + struct ethtool_rxfh_fields *cmd); int (*get_tc_size)(struct hnae3_handle *handle); @@ -735,8 +755,6 @@ struct hnae3_ae_ops { void (*enable_fd)(struct hnae3_handle *handle, bool enable); int (*add_arfs_entry)(struct hnae3_handle *handle, u16 queue_id, u16 flow_id, struct flow_keys *fkeys); - int (*dbg_read_cmd)(struct hnae3_handle *handle, enum hnae3_dbg_cmd cmd, - char *buf, int len); pci_ers_result_t (*handle_hw_ras_error)(struct hnae3_ae_dev *ae_dev); bool (*get_hw_reset_stat)(struct hnae3_handle *handle); bool (*ae_dev_resetting)(struct hnae3_handle *handle); @@ -773,7 +791,7 @@ struct hnae3_ae_ops { void (*get_rx_hwts)(struct hnae3_handle *handle, struct sk_buff *skb, u32 nsec, u32 sec); int (*get_ts_info)(struct hnae3_handle *handle, - struct ethtool_ts_info *info); + struct kernel_ethtool_ts_info *info); int (*get_link_diagnosis_info)(struct hnae3_handle *handle, u32 *status_code); void (*clean_vf_config)(struct hnae3_ae_dev *ae_dev, int num_vfs); @@ -783,6 +801,9 @@ struct hnae3_ae_ops { struct ethtool_wolinfo *wol); int (*set_wol)(struct hnae3_handle *handle, struct ethtool_wolinfo *wol); + int (*dbg_get_read_func)(struct hnae3_handle *handle, + enum hnae3_dbg_cmd cmd, + read_func *func); }; struct hnae3_dcb_ops { @@ -897,15 +918,12 @@ struct hnae3_handle { struct hnae3_roce_private_info rinfo; }; - u32 numa_node_mask; /* for multi-chip support */ + nodemask_t numa_node_mask; /* for multi-chip support */ enum hnae3_port_base_vlan_state port_base_vlan_state; u8 netdev_flags; struct dentry *hnae3_dbgfs; - /* protects concurrent contention between debugfs commands */ - struct mutex dbgfs_lock; - char **dbgfs_buf; /* Network interface message level enabled bits */ u32 msg_enable; @@ -953,4 +971,6 @@ int hnae3_register_client(struct hnae3_client *client); void hnae3_set_client_init_flag(struct hnae3_client *client, struct hnae3_ae_dev *ae_dev, unsigned int inited); +void hnae3_acquire_unload_lock(void); +void hnae3_release_unload_lock(void); #endif diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.c b/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.c index 652d71326231..37396ca4ecfc 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.c +++ b/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.c @@ -48,6 +48,7 @@ void hclge_comm_cmd_reuse_desc(struct hclge_desc *desc, bool is_read) else desc->flag &= cpu_to_le16(~HCLGE_COMM_CMD_FLAG_WR); } +EXPORT_SYMBOL_GPL(hclge_comm_cmd_reuse_desc); static void hclge_comm_set_default_capability(struct hnae3_ae_dev *ae_dev, bool is_pf) @@ -72,6 +73,7 @@ void hclge_comm_cmd_setup_basic_desc(struct hclge_desc *desc, if (is_read) desc->flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_WR); } +EXPORT_SYMBOL_GPL(hclge_comm_cmd_setup_basic_desc); int hclge_comm_firmware_compat_config(struct hnae3_ae_dev *ae_dev, struct hclge_comm_hw *hw, bool en) @@ -158,6 +160,7 @@ static const struct hclge_comm_caps_bit_map hclge_pf_cmd_caps[] = { {HCLGE_COMM_CAP_WOL_B, HNAE3_DEV_SUPPORT_WOL_B}, {HCLGE_COMM_CAP_TM_FLUSH_B, HNAE3_DEV_SUPPORT_TM_FLUSH_B}, {HCLGE_COMM_CAP_VF_FAULT_B, HNAE3_DEV_SUPPORT_VF_FAULT_B}, + {HCLGE_COMM_CAP_ERR_MOD_GEN_REG_B, HNAE3_DEV_SUPPORT_ERR_MOD_GEN_REG_B}, }; static const struct hclge_comm_caps_bit_map hclge_vf_cmd_caps[] = { @@ -345,7 +348,7 @@ static int hclge_comm_cmd_csq_clean(struct hclge_comm_hw *hw) static int hclge_comm_cmd_csq_done(struct hclge_comm_hw *hw) { u32 head = hclge_comm_read_dev(hw, HCLGE_COMM_NIC_CSQ_HEAD_REG); - return head == hw->cmq.csq.next_to_use; + return head == (u32)hw->cmq.csq.next_to_use; } static u32 hclge_get_cmdq_tx_timeout(u16 opcode, u32 tx_timeout) @@ -470,10 +473,14 @@ static int hclge_comm_cmd_check_result(struct hclge_comm_hw *hw, int hclge_comm_cmd_send(struct hclge_comm_hw *hw, struct hclge_desc *desc, int num) { + bool is_special = hclge_comm_is_special_opcode(le16_to_cpu(desc->opcode)); struct hclge_comm_cmq_ring *csq = &hw->cmq.csq; int ret; int ntc; + if (hw->cmq.ops.trace_cmd_send) + hw->cmq.ops.trace_cmd_send(hw, desc, num, is_special); + spin_lock_bh(&hw->cmq.csq.lock); if (test_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hw->comm_state)) { @@ -507,8 +514,12 @@ int hclge_comm_cmd_send(struct hclge_comm_hw *hw, struct hclge_desc *desc, spin_unlock_bh(&hw->cmq.csq.lock); + if (hw->cmq.ops.trace_cmd_get) + hw->cmq.ops.trace_cmd_get(hw, desc, num, is_special); + return ret; } +EXPORT_SYMBOL_GPL(hclge_comm_cmd_send); static void hclge_comm_cmd_uninit_regs(struct hclge_comm_hw *hw) { @@ -545,6 +556,7 @@ void hclge_comm_cmd_uninit(struct hnae3_ae_dev *ae_dev, hclge_comm_free_cmd_desc(&cmdq->csq); hclge_comm_free_cmd_desc(&cmdq->crq); } +EXPORT_SYMBOL_GPL(hclge_comm_cmd_uninit); int hclge_comm_cmd_queue_init(struct pci_dev *pdev, struct hclge_comm_hw *hw) { @@ -583,6 +595,19 @@ err_csq: hclge_comm_free_cmd_desc(&hw->cmq.csq); return ret; } +EXPORT_SYMBOL_GPL(hclge_comm_cmd_queue_init); + +void hclge_comm_cmd_init_ops(struct hclge_comm_hw *hw, + const struct hclge_comm_cmq_ops *ops) +{ + struct hclge_comm_cmq *cmdq = &hw->cmq; + + if (ops) { + cmdq->ops.trace_cmd_send = ops->trace_cmd_send; + cmdq->ops.trace_cmd_get = ops->trace_cmd_get; + } +} +EXPORT_SYMBOL_GPL(hclge_comm_cmd_init_ops); int hclge_comm_cmd_init(struct hnae3_ae_dev *ae_dev, struct hclge_comm_hw *hw, u32 *fw_version, bool is_pf, @@ -653,3 +678,8 @@ err_cmd_init: return ret; } +EXPORT_SYMBOL_GPL(hclge_comm_cmd_init); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("HNS3: Hisilicon Ethernet PF/VF Common Library"); +MODULE_AUTHOR("Huawei Tech. Co., Ltd."); diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h index 552396518e08..2c2a2f1e0d7a 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h +++ b/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h @@ -91,6 +91,7 @@ enum hclge_opcode_type { HCLGE_OPC_DFX_RCB_REG = 0x004D, HCLGE_OPC_DFX_TQP_REG = 0x004E, HCLGE_OPC_DFX_SSU_REG_2 = 0x004F, + HCLGE_OPC_DFX_GEN_REG = 0x7038, HCLGE_OPC_QUERY_DEV_SPECS = 0x0050, HCLGE_OPC_GET_QUEUE_ERR_VF = 0x0067, @@ -246,6 +247,9 @@ enum hclge_opcode_type { HCLGE_OPC_QCN_AJUST_INIT = 0x1A07, HCLGE_OPC_QCN_DFX_CNT_STATUS = 0x1A08, + /* SCC commands */ + HCLGE_OPC_QUERY_SCC_VER = 0x1A84, + /* Mailbox command */ HCLGEVF_OPC_MBX_PF_TO_VF = 0x2000, HCLGEVF_OPC_MBX_VF_TO_PF = 0x2001, @@ -353,6 +357,7 @@ enum HCLGE_COMM_CAP_BITS { HCLGE_COMM_CAP_LANE_NUM_B = 27, HCLGE_COMM_CAP_WOL_B = 28, HCLGE_COMM_CAP_TM_FLUSH_B = 31, + HCLGE_COMM_CAP_ERR_MOD_GEN_REG_B = 32, }; enum HCLGE_COMM_API_CAP_BITS { @@ -392,6 +397,11 @@ struct hclge_comm_query_version_cmd { __le32 caps[HCLGE_COMM_QUERY_CAP_LENGTH]; /* capabilities of device */ }; +struct hclge_comm_query_scc_cmd { + __le32 scc_version; + u8 rsv[20]; +}; + #define HCLGE_DESC_DATA_LEN 6 struct hclge_desc { __le16 opcode; @@ -423,11 +433,22 @@ enum hclge_comm_cmd_status { HCLGE_COMM_ERR_CSQ_ERROR = -3, }; +struct hclge_comm_hw; +struct hclge_comm_cmq_ops { + void (*trace_cmd_send)(struct hclge_comm_hw *hw, + struct hclge_desc *desc, + int num, bool is_special); + void (*trace_cmd_get)(struct hclge_comm_hw *hw, + struct hclge_desc *desc, + int num, bool is_special); +}; + struct hclge_comm_cmq { struct hclge_comm_cmq_ring csq; struct hclge_comm_cmq_ring crq; u16 tx_timeout; enum hclge_comm_cmd_status last_status; + struct hclge_comm_cmq_ops ops; }; struct hclge_comm_hw { @@ -474,5 +495,6 @@ int hclge_comm_cmd_queue_init(struct pci_dev *pdev, struct hclge_comm_hw *hw); int hclge_comm_cmd_init(struct hnae3_ae_dev *ae_dev, struct hclge_comm_hw *hw, u32 *fw_version, bool is_pf, unsigned long reset_pending); - +void hclge_comm_cmd_init_ops(struct hclge_comm_hw *hw, + const struct hclge_comm_cmq_ops *ops); #endif diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_rss.c b/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_rss.c index b4ae2160aff4..1eca53aaf598 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_rss.c +++ b/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_rss.c @@ -62,6 +62,7 @@ int hclge_comm_rss_init_cfg(struct hnae3_handle *nic, return 0; } +EXPORT_SYMBOL_GPL(hclge_comm_rss_init_cfg); void hclge_comm_get_rss_tc_info(u16 rss_size, u8 hw_tc_map, u16 *tc_offset, u16 *tc_valid, u16 *tc_size) @@ -78,6 +79,7 @@ void hclge_comm_get_rss_tc_info(u16 rss_size, u8 hw_tc_map, u16 *tc_offset, tc_offset[i] = (hw_tc_map & BIT(i)) ? rss_size * i : 0; } } +EXPORT_SYMBOL_GPL(hclge_comm_get_rss_tc_info); int hclge_comm_set_rss_tc_mode(struct hclge_comm_hw *hw, u16 *tc_offset, u16 *tc_valid, u16 *tc_size) @@ -113,6 +115,7 @@ int hclge_comm_set_rss_tc_mode(struct hclge_comm_hw *hw, u16 *tc_offset, return ret; } +EXPORT_SYMBOL_GPL(hclge_comm_set_rss_tc_mode); int hclge_comm_set_rss_hash_key(struct hclge_comm_rss_cfg *rss_cfg, struct hclge_comm_hw *hw, const u8 *key, @@ -143,11 +146,12 @@ int hclge_comm_set_rss_hash_key(struct hclge_comm_rss_cfg *rss_cfg, return 0; } +EXPORT_SYMBOL_GPL(hclge_comm_set_rss_hash_key); int hclge_comm_set_rss_tuple(struct hnae3_ae_dev *ae_dev, struct hclge_comm_hw *hw, struct hclge_comm_rss_cfg *rss_cfg, - struct ethtool_rxnfc *nfc) + const struct ethtool_rxfh_fields *nfc) { struct hclge_comm_rss_input_tuple_cmd *req; struct hclge_desc desc; @@ -185,11 +189,13 @@ int hclge_comm_set_rss_tuple(struct hnae3_ae_dev *ae_dev, rss_cfg->rss_tuple_sets.ipv6_fragment_en = req->ipv6_fragment_en; return 0; } +EXPORT_SYMBOL_GPL(hclge_comm_set_rss_tuple); u32 hclge_comm_get_rss_key_size(struct hnae3_handle *handle) { return HCLGE_COMM_RSS_KEY_SIZE; } +EXPORT_SYMBOL_GPL(hclge_comm_get_rss_key_size); int hclge_comm_parse_rss_hfunc(struct hclge_comm_rss_cfg *rss_cfg, const u8 hfunc, u8 *hash_algo) @@ -217,6 +223,7 @@ void hclge_comm_rss_indir_init_cfg(struct hnae3_ae_dev *ae_dev, for (i = 0; i < ae_dev->dev_specs.rss_ind_tbl_size; i++) rss_cfg->rss_indirection_tbl[i] = i % rss_cfg->rss_size; } +EXPORT_SYMBOL_GPL(hclge_comm_rss_indir_init_cfg); int hclge_comm_get_rss_tuple(struct hclge_comm_rss_cfg *rss_cfg, int flow_type, u8 *tuple_sets) @@ -250,6 +257,7 @@ int hclge_comm_get_rss_tuple(struct hclge_comm_rss_cfg *rss_cfg, int flow_type, return 0; } +EXPORT_SYMBOL_GPL(hclge_comm_get_rss_tuple); static void hclge_comm_append_rss_msb_info(struct hclge_comm_rss_ind_tbl_cmd *req, @@ -304,6 +312,7 @@ int hclge_comm_set_rss_indir_table(struct hnae3_ae_dev *ae_dev, } return 0; } +EXPORT_SYMBOL_GPL(hclge_comm_set_rss_indir_table); int hclge_comm_set_rss_input_tuple(struct hclge_comm_hw *hw, struct hclge_comm_rss_cfg *rss_cfg) @@ -332,6 +341,7 @@ int hclge_comm_set_rss_input_tuple(struct hclge_comm_hw *hw, "failed to configure rss input, ret = %d.\n", ret); return ret; } +EXPORT_SYMBOL_GPL(hclge_comm_set_rss_input_tuple); void hclge_comm_get_rss_hash_info(struct hclge_comm_rss_cfg *rss_cfg, u8 *key, u8 *hfunc) @@ -355,6 +365,7 @@ void hclge_comm_get_rss_hash_info(struct hclge_comm_rss_cfg *rss_cfg, u8 *key, if (key) memcpy(key, rss_cfg->rss_hash_key, HCLGE_COMM_RSS_KEY_SIZE); } +EXPORT_SYMBOL_GPL(hclge_comm_get_rss_hash_info); void hclge_comm_get_rss_indir_tbl(struct hclge_comm_rss_cfg *rss_cfg, u32 *indir, u16 rss_ind_tbl_size) @@ -367,6 +378,7 @@ void hclge_comm_get_rss_indir_tbl(struct hclge_comm_rss_cfg *rss_cfg, for (i = 0; i < rss_ind_tbl_size; i++) indir[i] = rss_cfg->rss_indirection_tbl[i]; } +EXPORT_SYMBOL_GPL(hclge_comm_get_rss_indir_tbl); int hclge_comm_set_rss_algo_key(struct hclge_comm_hw *hw, const u8 hfunc, const u8 *key) @@ -408,8 +420,9 @@ int hclge_comm_set_rss_algo_key(struct hclge_comm_hw *hw, const u8 hfunc, return 0; } +EXPORT_SYMBOL_GPL(hclge_comm_set_rss_algo_key); -static u8 hclge_comm_get_rss_hash_bits(struct ethtool_rxnfc *nfc) +static u8 hclge_comm_get_rss_hash_bits(const struct ethtool_rxfh_fields *nfc) { u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGE_COMM_S_PORT_BIT : 0; @@ -435,7 +448,7 @@ static u8 hclge_comm_get_rss_hash_bits(struct ethtool_rxnfc *nfc) } int hclge_comm_init_rss_tuple_cmd(struct hclge_comm_rss_cfg *rss_cfg, - struct ethtool_rxnfc *nfc, + const struct ethtool_rxfh_fields *nfc, struct hnae3_ae_dev *ae_dev, struct hclge_comm_rss_input_tuple_cmd *req) { @@ -502,3 +515,4 @@ u64 hclge_comm_convert_rss_tuple(u8 tuple_sets) return tuple_data; } +EXPORT_SYMBOL_GPL(hclge_comm_convert_rss_tuple); diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_rss.h b/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_rss.h index cdafa63fe38b..cbc02b50c6e7 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_rss.h +++ b/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_rss.h @@ -108,7 +108,7 @@ void hclge_comm_get_rss_indir_tbl(struct hclge_comm_rss_cfg *rss_cfg, int hclge_comm_set_rss_algo_key(struct hclge_comm_hw *hw, const u8 hfunc, const u8 *key); int hclge_comm_init_rss_tuple_cmd(struct hclge_comm_rss_cfg *rss_cfg, - struct ethtool_rxnfc *nfc, + const struct ethtool_rxfh_fields *nfc, struct hnae3_ae_dev *ae_dev, struct hclge_comm_rss_input_tuple_cmd *req); u64 hclge_comm_convert_rss_tuple(u8 tuple_sets); @@ -129,5 +129,5 @@ int hclge_comm_set_rss_hash_key(struct hclge_comm_rss_cfg *rss_cfg, int hclge_comm_set_rss_tuple(struct hnae3_ae_dev *ae_dev, struct hclge_comm_hw *hw, struct hclge_comm_rss_cfg *rss_cfg, - struct ethtool_rxnfc *nfc); + const struct ethtool_rxfh_fields *nfc); #endif diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_tqp_stats.c b/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_tqp_stats.c index f3c9395d8351..f9a3d6fc4416 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_tqp_stats.c +++ b/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_tqp_stats.c @@ -26,6 +26,7 @@ u64 *hclge_comm_tqps_get_stats(struct hnae3_handle *handle, u64 *data) return buff; } +EXPORT_SYMBOL_GPL(hclge_comm_tqps_get_stats); int hclge_comm_tqps_get_sset_count(struct hnae3_handle *handle) { @@ -33,29 +34,26 @@ int hclge_comm_tqps_get_sset_count(struct hnae3_handle *handle) return kinfo->num_tqps * HCLGE_COMM_QUEUE_PAIR_SIZE; } +EXPORT_SYMBOL_GPL(hclge_comm_tqps_get_sset_count); -u8 *hclge_comm_tqps_get_strings(struct hnae3_handle *handle, u8 *data) +void hclge_comm_tqps_get_strings(struct hnae3_handle *handle, u8 **data) { struct hnae3_knic_private_info *kinfo = &handle->kinfo; - u8 *buff = data; u16 i; for (i = 0; i < kinfo->num_tqps; i++) { struct hclge_comm_tqp *tqp = container_of(kinfo->tqp[i], struct hclge_comm_tqp, q); - snprintf(buff, ETH_GSTRING_LEN, "txq%u_pktnum_rcd", tqp->index); - buff += ETH_GSTRING_LEN; + ethtool_sprintf(data, "txq%u_pktnum_rcd", tqp->index); } for (i = 0; i < kinfo->num_tqps; i++) { struct hclge_comm_tqp *tqp = container_of(kinfo->tqp[i], struct hclge_comm_tqp, q); - snprintf(buff, ETH_GSTRING_LEN, "rxq%u_pktnum_rcd", tqp->index); - buff += ETH_GSTRING_LEN; + ethtool_sprintf(data, "rxq%u_pktnum_rcd", tqp->index); } - - return buff; } +EXPORT_SYMBOL_GPL(hclge_comm_tqps_get_strings); int hclge_comm_tqps_update_stats(struct hnae3_handle *handle, struct hclge_comm_hw *hw) @@ -85,7 +83,7 @@ int hclge_comm_tqps_update_stats(struct hnae3_handle *handle, hclge_comm_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_TX_STATS, true); - desc.data[0] = cpu_to_le32(tqp->index & 0x1ff); + desc.data[0] = cpu_to_le32(tqp->index); ret = hclge_comm_cmd_send(hw, &desc, 1); if (ret) { dev_err(&hw->cmq.csq.pdev->dev, @@ -99,6 +97,7 @@ int hclge_comm_tqps_update_stats(struct hnae3_handle *handle, return 0; } +EXPORT_SYMBOL_GPL(hclge_comm_tqps_update_stats); void hclge_comm_reset_tqp_stats(struct hnae3_handle *handle) { @@ -113,3 +112,4 @@ void hclge_comm_reset_tqp_stats(struct hnae3_handle *handle) memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats)); } } +EXPORT_SYMBOL_GPL(hclge_comm_reset_tqp_stats); diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_tqp_stats.h b/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_tqp_stats.h index a46350162ee8..b9ff424c0bc2 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_tqp_stats.h +++ b/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_tqp_stats.h @@ -32,7 +32,7 @@ struct hclge_comm_tqp { u64 *hclge_comm_tqps_get_stats(struct hnae3_handle *handle, u64 *data); int hclge_comm_tqps_get_sset_count(struct hnae3_handle *handle); -u8 *hclge_comm_tqps_get_strings(struct hnae3_handle *handle, u8 *data); +void hclge_comm_tqps_get_strings(struct hnae3_handle *handle, u8 **data); void hclge_comm_reset_tqp_stats(struct hnae3_handle *handle); int hclge_comm_tqps_update_stats(struct hnae3_handle *handle, struct hclge_comm_hw *hw); diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c b/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c index 807eb3bbb11c..0255c8acb744 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c +++ b/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c @@ -3,6 +3,8 @@ #include <linux/debugfs.h> #include <linux/device.h> +#include <linux/seq_file.h> +#include <linux/string_choices.h> #include "hnae3.h" #include "hns3_debugfs.h" @@ -39,323 +41,279 @@ static struct hns3_dbg_dentry_info hns3_dbg_dentry[] = { }; static int hns3_dbg_bd_file_init(struct hnae3_handle *handle, u32 cmd); -static int hns3_dbg_common_file_init(struct hnae3_handle *handle, u32 cmd); +static int hns3_dbg_common_init_t1(struct hnae3_handle *handle, u32 cmd); +static int hns3_dbg_common_init_t2(struct hnae3_handle *handle, u32 cmd); static struct hns3_dbg_cmd_info hns3_dbg_cmd[] = { { .name = "tm_nodes", .cmd = HNAE3_DBG_CMD_TM_NODES, .dentry = HNS3_DBG_DENTRY_TM, - .buf_len = HNS3_DBG_READ_LEN, - .init = hns3_dbg_common_file_init, + .init = hns3_dbg_common_init_t2, }, { .name = "tm_priority", .cmd = HNAE3_DBG_CMD_TM_PRI, .dentry = HNS3_DBG_DENTRY_TM, - .buf_len = HNS3_DBG_READ_LEN, - .init = hns3_dbg_common_file_init, + .init = hns3_dbg_common_init_t2, }, { .name = "tm_qset", .cmd = HNAE3_DBG_CMD_TM_QSET, .dentry = HNS3_DBG_DENTRY_TM, - .buf_len = HNS3_DBG_READ_LEN, - .init = hns3_dbg_common_file_init, + .init = hns3_dbg_common_init_t2, }, { .name = "tm_map", .cmd = HNAE3_DBG_CMD_TM_MAP, .dentry = HNS3_DBG_DENTRY_TM, - .buf_len = HNS3_DBG_READ_LEN_1MB, - .init = hns3_dbg_common_file_init, + .init = hns3_dbg_common_init_t2, }, { .name = "tm_pg", .cmd = HNAE3_DBG_CMD_TM_PG, .dentry = HNS3_DBG_DENTRY_TM, - .buf_len = HNS3_DBG_READ_LEN, - .init = hns3_dbg_common_file_init, + .init = hns3_dbg_common_init_t2, }, { .name = "tm_port", .cmd = HNAE3_DBG_CMD_TM_PORT, .dentry = HNS3_DBG_DENTRY_TM, - .buf_len = HNS3_DBG_READ_LEN, - .init = hns3_dbg_common_file_init, + .init = hns3_dbg_common_init_t2, }, { .name = "tc_sch_info", .cmd = HNAE3_DBG_CMD_TC_SCH_INFO, .dentry = HNS3_DBG_DENTRY_TM, - .buf_len = HNS3_DBG_READ_LEN, - .init = hns3_dbg_common_file_init, + .init = hns3_dbg_common_init_t2, }, { .name = "qos_pause_cfg", .cmd = HNAE3_DBG_CMD_QOS_PAUSE_CFG, .dentry = HNS3_DBG_DENTRY_TM, - .buf_len = HNS3_DBG_READ_LEN, - .init = hns3_dbg_common_file_init, + .init = hns3_dbg_common_init_t2, }, { .name = "qos_pri_map", .cmd = HNAE3_DBG_CMD_QOS_PRI_MAP, .dentry = HNS3_DBG_DENTRY_TM, - .buf_len = HNS3_DBG_READ_LEN, - .init = hns3_dbg_common_file_init, + .init = hns3_dbg_common_init_t2, }, { .name = "qos_dscp_map", .cmd = HNAE3_DBG_CMD_QOS_DSCP_MAP, .dentry = HNS3_DBG_DENTRY_TM, - .buf_len = HNS3_DBG_READ_LEN, - .init = hns3_dbg_common_file_init, + .init = hns3_dbg_common_init_t2, }, { .name = "qos_buf_cfg", .cmd = HNAE3_DBG_CMD_QOS_BUF_CFG, .dentry = HNS3_DBG_DENTRY_TM, - .buf_len = HNS3_DBG_READ_LEN, - .init = hns3_dbg_common_file_init, + .init = hns3_dbg_common_init_t2, }, { .name = "dev_info", .cmd = HNAE3_DBG_CMD_DEV_INFO, .dentry = HNS3_DBG_DENTRY_COMMON, - .buf_len = HNS3_DBG_READ_LEN, - .init = hns3_dbg_common_file_init, + .init = hns3_dbg_common_init_t1, }, { .name = "tx_bd_queue", .cmd = HNAE3_DBG_CMD_TX_BD, .dentry = HNS3_DBG_DENTRY_TX_BD, - .buf_len = HNS3_DBG_READ_LEN_5MB, .init = hns3_dbg_bd_file_init, }, { .name = "rx_bd_queue", .cmd = HNAE3_DBG_CMD_RX_BD, .dentry = HNS3_DBG_DENTRY_RX_BD, - .buf_len = HNS3_DBG_READ_LEN_4MB, .init = hns3_dbg_bd_file_init, }, { .name = "uc", .cmd = HNAE3_DBG_CMD_MAC_UC, .dentry = HNS3_DBG_DENTRY_MAC, - .buf_len = HNS3_DBG_READ_LEN_128KB, - .init = hns3_dbg_common_file_init, + .init = hns3_dbg_common_init_t2, }, { .name = "mc", .cmd = HNAE3_DBG_CMD_MAC_MC, .dentry = HNS3_DBG_DENTRY_MAC, - .buf_len = HNS3_DBG_READ_LEN, - .init = hns3_dbg_common_file_init, + .init = hns3_dbg_common_init_t2, }, { .name = "mng_tbl", .cmd = HNAE3_DBG_CMD_MNG_TBL, .dentry = HNS3_DBG_DENTRY_COMMON, - .buf_len = HNS3_DBG_READ_LEN, - .init = hns3_dbg_common_file_init, + .init = hns3_dbg_common_init_t2, }, { .name = "loopback", .cmd = HNAE3_DBG_CMD_LOOPBACK, .dentry = HNS3_DBG_DENTRY_COMMON, - .buf_len = HNS3_DBG_READ_LEN, - .init = hns3_dbg_common_file_init, + .init = hns3_dbg_common_init_t2, }, { .name = "interrupt_info", .cmd = HNAE3_DBG_CMD_INTERRUPT_INFO, .dentry = HNS3_DBG_DENTRY_COMMON, - .buf_len = HNS3_DBG_READ_LEN, - .init = hns3_dbg_common_file_init, + .init = hns3_dbg_common_init_t2, }, { .name = "reset_info", .cmd = HNAE3_DBG_CMD_RESET_INFO, .dentry = HNS3_DBG_DENTRY_COMMON, - .buf_len = HNS3_DBG_READ_LEN, - .init = hns3_dbg_common_file_init, + .init = hns3_dbg_common_init_t2, }, { .name = "imp_info", .cmd = HNAE3_DBG_CMD_IMP_INFO, .dentry = HNS3_DBG_DENTRY_COMMON, - .buf_len = HNS3_DBG_READ_LEN, - .init = hns3_dbg_common_file_init, + .init = hns3_dbg_common_init_t2, }, { .name = "ncl_config", .cmd = HNAE3_DBG_CMD_NCL_CONFIG, .dentry = HNS3_DBG_DENTRY_COMMON, - .buf_len = HNS3_DBG_READ_LEN_128KB, - .init = hns3_dbg_common_file_init, + .init = hns3_dbg_common_init_t2, }, { .name = "mac_tnl_status", .cmd = HNAE3_DBG_CMD_MAC_TNL_STATUS, .dentry = HNS3_DBG_DENTRY_COMMON, - .buf_len = HNS3_DBG_READ_LEN, - .init = hns3_dbg_common_file_init, + .init = hns3_dbg_common_init_t2, }, { .name = "bios_common", .cmd = HNAE3_DBG_CMD_REG_BIOS_COMMON, .dentry = HNS3_DBG_DENTRY_REG, - .buf_len = HNS3_DBG_READ_LEN, - .init = hns3_dbg_common_file_init, + .init = hns3_dbg_common_init_t2, }, { .name = "ssu", .cmd = HNAE3_DBG_CMD_REG_SSU, .dentry = HNS3_DBG_DENTRY_REG, - .buf_len = HNS3_DBG_READ_LEN, - .init = hns3_dbg_common_file_init, + .init = hns3_dbg_common_init_t2, }, { .name = "igu_egu", .cmd = HNAE3_DBG_CMD_REG_IGU_EGU, .dentry = HNS3_DBG_DENTRY_REG, - .buf_len = HNS3_DBG_READ_LEN, - .init = hns3_dbg_common_file_init, + .init = hns3_dbg_common_init_t2, }, { .name = "rpu", .cmd = HNAE3_DBG_CMD_REG_RPU, .dentry = HNS3_DBG_DENTRY_REG, - .buf_len = HNS3_DBG_READ_LEN, - .init = hns3_dbg_common_file_init, + .init = hns3_dbg_common_init_t2, }, { .name = "ncsi", .cmd = HNAE3_DBG_CMD_REG_NCSI, .dentry = HNS3_DBG_DENTRY_REG, - .buf_len = HNS3_DBG_READ_LEN, - .init = hns3_dbg_common_file_init, + .init = hns3_dbg_common_init_t2, }, { .name = "rtc", .cmd = HNAE3_DBG_CMD_REG_RTC, .dentry = HNS3_DBG_DENTRY_REG, - .buf_len = HNS3_DBG_READ_LEN, - .init = hns3_dbg_common_file_init, + .init = hns3_dbg_common_init_t2, }, { .name = "ppp", .cmd = HNAE3_DBG_CMD_REG_PPP, .dentry = HNS3_DBG_DENTRY_REG, - .buf_len = HNS3_DBG_READ_LEN, - .init = hns3_dbg_common_file_init, + .init = hns3_dbg_common_init_t2, }, { .name = "rcb", .cmd = HNAE3_DBG_CMD_REG_RCB, .dentry = HNS3_DBG_DENTRY_REG, - .buf_len = HNS3_DBG_READ_LEN, - .init = hns3_dbg_common_file_init, + .init = hns3_dbg_common_init_t2, }, { .name = "tqp", .cmd = HNAE3_DBG_CMD_REG_TQP, .dentry = HNS3_DBG_DENTRY_REG, - .buf_len = HNS3_DBG_READ_LEN_128KB, - .init = hns3_dbg_common_file_init, + .init = hns3_dbg_common_init_t2, }, { .name = "mac", .cmd = HNAE3_DBG_CMD_REG_MAC, .dentry = HNS3_DBG_DENTRY_REG, - .buf_len = HNS3_DBG_READ_LEN, - .init = hns3_dbg_common_file_init, + .init = hns3_dbg_common_init_t2, }, { .name = "dcb", .cmd = HNAE3_DBG_CMD_REG_DCB, .dentry = HNS3_DBG_DENTRY_REG, - .buf_len = HNS3_DBG_READ_LEN, - .init = hns3_dbg_common_file_init, + .init = hns3_dbg_common_init_t2, }, { .name = "queue_map", .cmd = HNAE3_DBG_CMD_QUEUE_MAP, .dentry = HNS3_DBG_DENTRY_QUEUE, - .buf_len = HNS3_DBG_READ_LEN, - .init = hns3_dbg_common_file_init, + .init = hns3_dbg_common_init_t1, }, { .name = "rx_queue_info", .cmd = HNAE3_DBG_CMD_RX_QUEUE_INFO, .dentry = HNS3_DBG_DENTRY_QUEUE, - .buf_len = HNS3_DBG_READ_LEN_1MB, - .init = hns3_dbg_common_file_init, + .init = hns3_dbg_common_init_t1, }, { .name = "tx_queue_info", .cmd = HNAE3_DBG_CMD_TX_QUEUE_INFO, .dentry = HNS3_DBG_DENTRY_QUEUE, - .buf_len = HNS3_DBG_READ_LEN_1MB, - .init = hns3_dbg_common_file_init, + .init = hns3_dbg_common_init_t1, }, { .name = "fd_tcam", .cmd = HNAE3_DBG_CMD_FD_TCAM, .dentry = HNS3_DBG_DENTRY_FD, - .buf_len = HNS3_DBG_READ_LEN_1MB, - .init = hns3_dbg_common_file_init, + .init = hns3_dbg_common_init_t2, }, { .name = "service_task_info", .cmd = HNAE3_DBG_CMD_SERV_INFO, .dentry = HNS3_DBG_DENTRY_COMMON, - .buf_len = HNS3_DBG_READ_LEN, - .init = hns3_dbg_common_file_init, + .init = hns3_dbg_common_init_t2, }, { .name = "vlan_config", .cmd = HNAE3_DBG_CMD_VLAN_CONFIG, .dentry = HNS3_DBG_DENTRY_COMMON, - .buf_len = HNS3_DBG_READ_LEN, - .init = hns3_dbg_common_file_init, + .init = hns3_dbg_common_init_t2, }, { .name = "ptp_info", .cmd = HNAE3_DBG_CMD_PTP_INFO, .dentry = HNS3_DBG_DENTRY_COMMON, - .buf_len = HNS3_DBG_READ_LEN, - .init = hns3_dbg_common_file_init, + .init = hns3_dbg_common_init_t2, }, { .name = "fd_counter", .cmd = HNAE3_DBG_CMD_FD_COUNTER, .dentry = HNS3_DBG_DENTRY_FD, - .buf_len = HNS3_DBG_READ_LEN, - .init = hns3_dbg_common_file_init, + .init = hns3_dbg_common_init_t2, }, { .name = "umv_info", .cmd = HNAE3_DBG_CMD_UMV_INFO, .dentry = HNS3_DBG_DENTRY_COMMON, - .buf_len = HNS3_DBG_READ_LEN, - .init = hns3_dbg_common_file_init, + .init = hns3_dbg_common_init_t2, }, { .name = "page_pool_info", .cmd = HNAE3_DBG_CMD_PAGE_POOL_INFO, .dentry = HNS3_DBG_DENTRY_COMMON, - .buf_len = HNS3_DBG_READ_LEN, - .init = hns3_dbg_common_file_init, + .init = hns3_dbg_common_init_t1, }, { .name = "coalesce_info", .cmd = HNAE3_DBG_CMD_COAL_INFO, .dentry = HNS3_DBG_DENTRY_COMMON, - .buf_len = HNS3_DBG_READ_LEN_1MB, - .init = hns3_dbg_common_file_init, + .init = hns3_dbg_common_init_t1, }, }; @@ -420,71 +378,17 @@ static struct hns3_dbg_cap_info hns3_dbg_cap[] = { } }; -static const struct hns3_dbg_item coal_info_items[] = { - { "VEC_ID", 2 }, - { "ALGO_STATE", 2 }, - { "PROFILE_ID", 2 }, - { "CQE_MODE", 2 }, - { "TUNE_STATE", 2 }, - { "STEPS_LEFT", 2 }, - { "STEPS_RIGHT", 2 }, - { "TIRED", 2 }, - { "SW_GL", 2 }, - { "SW_QL", 2 }, - { "HW_GL", 2 }, - { "HW_QL", 2 }, -}; - static const char * const dim_cqe_mode_str[] = { "EQE", "CQE" }; static const char * const dim_state_str[] = { "START", "IN_PROG", "APPLY" }; static const char * const dim_tune_stat_str[] = { "ON_TOP", "TIRED", "RIGHT", "LEFT" }; -static void hns3_dbg_fill_content(char *content, u16 len, - const struct hns3_dbg_item *items, - const char **result, u16 size) -{ -#define HNS3_DBG_LINE_END_LEN 2 - char *pos = content; - u16 item_len; - u16 i; - - if (!len) { - return; - } else if (len <= HNS3_DBG_LINE_END_LEN) { - *pos++ = '\0'; - return; - } - - memset(content, ' ', len); - len -= HNS3_DBG_LINE_END_LEN; - - for (i = 0; i < size; i++) { - item_len = strlen(items[i].name) + items[i].interval; - if (len < item_len) - break; - - if (result) { - if (item_len < strlen(result[i])) - break; - memcpy(pos, result[i], strlen(result[i])); - } else { - memcpy(pos, items[i].name, strlen(items[i].name)); - } - pos += item_len; - len -= item_len; - } - *pos++ = '\n'; - *pos++ = '\0'; -} - static void hns3_get_coal_info(struct hns3_enet_tqp_vector *tqp_vector, - char **result, int i, bool is_tx) + struct seq_file *s, int i, bool is_tx) { unsigned int gl_offset, ql_offset; struct hns3_enet_coalesce *coal; unsigned int reg_val; - unsigned int j = 0; struct dim *dim; bool ql_enable; @@ -502,191 +406,96 @@ static void hns3_get_coal_info(struct hns3_enet_tqp_vector *tqp_vector, ql_enable = tqp_vector->rx_group.coal.ql_enable; } - sprintf(result[j++], "%d", i); - sprintf(result[j++], "%s", dim->state < ARRAY_SIZE(dim_state_str) ? - dim_state_str[dim->state] : "unknown"); - sprintf(result[j++], "%u", dim->profile_ix); - sprintf(result[j++], "%s", dim->mode < ARRAY_SIZE(dim_cqe_mode_str) ? - dim_cqe_mode_str[dim->mode] : "unknown"); - sprintf(result[j++], "%s", - dim->tune_state < ARRAY_SIZE(dim_tune_stat_str) ? - dim_tune_stat_str[dim->tune_state] : "unknown"); - sprintf(result[j++], "%u", dim->steps_left); - sprintf(result[j++], "%u", dim->steps_right); - sprintf(result[j++], "%u", dim->tired); - sprintf(result[j++], "%u", coal->int_gl); - sprintf(result[j++], "%u", coal->int_ql); + seq_printf(s, "%-8d", i); + seq_printf(s, "%-12s", dim->state < ARRAY_SIZE(dim_state_str) ? + dim_state_str[dim->state] : "unknown"); + seq_printf(s, "%-12u", dim->profile_ix); + seq_printf(s, "%-10s", dim->mode < ARRAY_SIZE(dim_cqe_mode_str) ? + dim_cqe_mode_str[dim->mode] : "unknown"); + seq_printf(s, "%-12s", dim->tune_state < ARRAY_SIZE(dim_tune_stat_str) ? + dim_tune_stat_str[dim->tune_state] : "unknown"); + seq_printf(s, "%-12u%-13u%-7u%-7u%-7u", dim->steps_left, + dim->steps_right, dim->tired, coal->int_gl, coal->int_ql); reg_val = readl(tqp_vector->mask_addr + gl_offset) & HNS3_VECTOR_GL_MASK; - sprintf(result[j++], "%u", reg_val); + seq_printf(s, "%-7u", reg_val); if (ql_enable) { reg_val = readl(tqp_vector->mask_addr + ql_offset) & HNS3_VECTOR_QL_MASK; - sprintf(result[j++], "%u", reg_val); + seq_printf(s, "%u\n", reg_val); } else { - sprintf(result[j++], "NA"); + seq_puts(s, "NA\n"); } } -static void hns3_dump_coal_info(struct hnae3_handle *h, char *buf, int len, - int *pos, bool is_tx) +static void hns3_dump_coal_info(struct seq_file *s, bool is_tx) { - char data_str[ARRAY_SIZE(coal_info_items)][HNS3_DBG_DATA_STR_LEN]; - char *result[ARRAY_SIZE(coal_info_items)]; + struct hnae3_handle *h = hnae3_seq_file_to_handle(s); struct hns3_enet_tqp_vector *tqp_vector; struct hns3_nic_priv *priv = h->priv; - char content[HNS3_DBG_INFO_LEN]; unsigned int i; - for (i = 0; i < ARRAY_SIZE(coal_info_items); i++) - result[i] = &data_str[i][0]; + seq_printf(s, "%s interrupt coalesce info:\n", is_tx ? "tx" : "rx"); - *pos += scnprintf(buf + *pos, len - *pos, - "%s interrupt coalesce info:\n", - is_tx ? "tx" : "rx"); - hns3_dbg_fill_content(content, sizeof(content), coal_info_items, - NULL, ARRAY_SIZE(coal_info_items)); - *pos += scnprintf(buf + *pos, len - *pos, "%s", content); + seq_puts(s, "VEC_ID ALGO_STATE PROFILE_ID CQE_MODE TUNE_STATE "); + seq_puts(s, "STEPS_LEFT STEPS_RIGHT TIRED SW_GL SW_QL "); + seq_puts(s, "HW_GL HW_QL\n"); for (i = 0; i < priv->vector_num; i++) { tqp_vector = &priv->tqp_vector[i]; - hns3_get_coal_info(tqp_vector, result, i, is_tx); - hns3_dbg_fill_content(content, sizeof(content), coal_info_items, - (const char **)result, - ARRAY_SIZE(coal_info_items)); - *pos += scnprintf(buf + *pos, len - *pos, "%s", content); + hns3_get_coal_info(tqp_vector, s, i, is_tx); } } -static int hns3_dbg_coal_info(struct hnae3_handle *h, char *buf, int len) +static int hns3_dbg_coal_info(struct seq_file *s, void *data) { - int pos = 0; - - hns3_dump_coal_info(h, buf, len, &pos, true); - pos += scnprintf(buf + pos, len - pos, "\n"); - hns3_dump_coal_info(h, buf, len, &pos, false); + hns3_dump_coal_info(s, true); + seq_puts(s, "\n"); + hns3_dump_coal_info(s, false); return 0; } -static const struct hns3_dbg_item tx_spare_info_items[] = { - { "QUEUE_ID", 2 }, - { "COPYBREAK", 2 }, - { "LEN", 7 }, - { "NTU", 4 }, - { "NTC", 4 }, - { "LTC", 4 }, - { "DMA", 17 }, -}; - -static void hns3_dbg_tx_spare_info(struct hns3_enet_ring *ring, char *buf, - int len, u32 ring_num, int *pos) -{ - char data_str[ARRAY_SIZE(tx_spare_info_items)][HNS3_DBG_DATA_STR_LEN]; - struct hns3_tx_spare *tx_spare = ring->tx_spare; - char *result[ARRAY_SIZE(tx_spare_info_items)]; - char content[HNS3_DBG_INFO_LEN]; - u32 i, j; - - if (!tx_spare) { - *pos += scnprintf(buf + *pos, len - *pos, - "tx spare buffer is not enabled\n"); - return; - } - - for (i = 0; i < ARRAY_SIZE(tx_spare_info_items); i++) - result[i] = &data_str[i][0]; - - *pos += scnprintf(buf + *pos, len - *pos, "tx spare buffer info\n"); - hns3_dbg_fill_content(content, sizeof(content), tx_spare_info_items, - NULL, ARRAY_SIZE(tx_spare_info_items)); - *pos += scnprintf(buf + *pos, len - *pos, "%s", content); - - for (i = 0; i < ring_num; i++) { - j = 0; - sprintf(result[j++], "%u", i); - sprintf(result[j++], "%u", ring->tx_copybreak); - sprintf(result[j++], "%u", tx_spare->len); - sprintf(result[j++], "%u", tx_spare->next_to_use); - sprintf(result[j++], "%u", tx_spare->next_to_clean); - sprintf(result[j++], "%u", tx_spare->last_to_clean); - sprintf(result[j++], "%pad", &tx_spare->dma); - hns3_dbg_fill_content(content, sizeof(content), - tx_spare_info_items, - (const char **)result, - ARRAY_SIZE(tx_spare_info_items)); - *pos += scnprintf(buf + *pos, len - *pos, "%s", content); - } -} - -static const struct hns3_dbg_item rx_queue_info_items[] = { - { "QUEUE_ID", 2 }, - { "BD_NUM", 2 }, - { "BD_LEN", 2 }, - { "TAIL", 2 }, - { "HEAD", 2 }, - { "FBDNUM", 2 }, - { "PKTNUM", 5 }, - { "COPYBREAK", 2 }, - { "RING_EN", 2 }, - { "RX_RING_EN", 2 }, - { "BASE_ADDR", 10 }, -}; - static void hns3_dump_rx_queue_info(struct hns3_enet_ring *ring, - struct hnae3_ae_dev *ae_dev, char **result, - u32 index) + struct seq_file *s, u32 index) { + struct hnae3_ae_dev *ae_dev = hnae3_seq_file_to_ae_dev(s); + void __iomem *base = ring->tqp->io_base; u32 base_add_l, base_add_h; - u32 j = 0; - - sprintf(result[j++], "%u", index); - - sprintf(result[j++], "%u", readl_relaxed(ring->tqp->io_base + - HNS3_RING_RX_RING_BD_NUM_REG)); - - sprintf(result[j++], "%u", readl_relaxed(ring->tqp->io_base + - HNS3_RING_RX_RING_BD_LEN_REG)); - - sprintf(result[j++], "%u", readl_relaxed(ring->tqp->io_base + - HNS3_RING_RX_RING_TAIL_REG)); - - sprintf(result[j++], "%u", readl_relaxed(ring->tqp->io_base + - HNS3_RING_RX_RING_HEAD_REG)); - - sprintf(result[j++], "%u", readl_relaxed(ring->tqp->io_base + - HNS3_RING_RX_RING_FBDNUM_REG)); - - sprintf(result[j++], "%u", readl_relaxed(ring->tqp->io_base + - HNS3_RING_RX_RING_PKTNUM_RECORD_REG)); - sprintf(result[j++], "%u", ring->rx_copybreak); - sprintf(result[j++], "%s", readl_relaxed(ring->tqp->io_base + - HNS3_RING_EN_REG) ? "on" : "off"); + seq_printf(s, "%-10u", index); + seq_printf(s, "%-8u", + readl_relaxed(base + HNS3_RING_RX_RING_BD_NUM_REG)); + seq_printf(s, "%-8u", + readl_relaxed(base + HNS3_RING_RX_RING_BD_LEN_REG)); + seq_printf(s, "%-6u", + readl_relaxed(base + HNS3_RING_RX_RING_TAIL_REG)); + seq_printf(s, "%-6u", + readl_relaxed(base + HNS3_RING_RX_RING_HEAD_REG)); + seq_printf(s, "%-8u", + readl_relaxed(base + HNS3_RING_RX_RING_FBDNUM_REG)); + seq_printf(s, "%-11u", readl_relaxed(base + + HNS3_RING_RX_RING_PKTNUM_RECORD_REG)); + seq_printf(s, "%-11u", ring->rx_copybreak); + seq_printf(s, "%-9s", + str_on_off(readl_relaxed(base + HNS3_RING_EN_REG))); if (hnae3_ae_dev_tqp_txrx_indep_supported(ae_dev)) - sprintf(result[j++], "%s", readl_relaxed(ring->tqp->io_base + - HNS3_RING_RX_EN_REG) ? "on" : "off"); + seq_printf(s, "%-12s", str_on_off(readl_relaxed(base + + HNS3_RING_RX_EN_REG))); else - sprintf(result[j++], "%s", "NA"); + seq_printf(s, "%-12s", "NA"); - base_add_h = readl_relaxed(ring->tqp->io_base + - HNS3_RING_RX_RING_BASEADDR_H_REG); - base_add_l = readl_relaxed(ring->tqp->io_base + - HNS3_RING_RX_RING_BASEADDR_L_REG); - sprintf(result[j++], "0x%08x%08x", base_add_h, base_add_l); + base_add_h = readl_relaxed(base + HNS3_RING_RX_RING_BASEADDR_H_REG); + base_add_l = readl_relaxed(base + HNS3_RING_RX_RING_BASEADDR_L_REG); + seq_printf(s, "0x%08x%08x\n", base_add_h, base_add_l); } -static int hns3_dbg_rx_queue_info(struct hnae3_handle *h, - char *buf, int len) +static int hns3_dbg_rx_queue_info(struct seq_file *s, void *data) { - char data_str[ARRAY_SIZE(rx_queue_info_items)][HNS3_DBG_DATA_STR_LEN]; - struct hnae3_ae_dev *ae_dev = pci_get_drvdata(h->pdev); - char *result[ARRAY_SIZE(rx_queue_info_items)]; + struct hnae3_handle *h = hnae3_seq_file_to_handle(s); struct hns3_nic_priv *priv = h->priv; - char content[HNS3_DBG_INFO_LEN]; struct hns3_enet_ring *ring; - int pos = 0; u32 i; if (!priv->ring) { @@ -694,12 +503,9 @@ static int hns3_dbg_rx_queue_info(struct hnae3_handle *h, return -EFAULT; } - for (i = 0; i < ARRAY_SIZE(rx_queue_info_items); i++) - result[i] = &data_str[i][0]; + seq_puts(s, "QUEUE_ID BD_NUM BD_LEN TAIL HEAD FBDNUM "); + seq_puts(s, "PKTNUM COPYBREAK RING_EN RX_RING_EN BASE_ADDR\n"); - hns3_dbg_fill_content(content, sizeof(content), rx_queue_info_items, - NULL, ARRAY_SIZE(rx_queue_info_items)); - pos += scnprintf(buf + pos, len - pos, "%s", content); for (i = 0; i < h->kinfo.num_tqps; i++) { /* Each cycle needs to determine whether the instance is reset, * to prevent reference to invalid memory. And need to ensure @@ -710,86 +516,51 @@ static int hns3_dbg_rx_queue_info(struct hnae3_handle *h, return -EPERM; ring = &priv->ring[(u32)(i + h->kinfo.num_tqps)]; - hns3_dump_rx_queue_info(ring, ae_dev, result, i); - hns3_dbg_fill_content(content, sizeof(content), - rx_queue_info_items, - (const char **)result, - ARRAY_SIZE(rx_queue_info_items)); - pos += scnprintf(buf + pos, len - pos, "%s", content); + hns3_dump_rx_queue_info(ring, s, i); } return 0; } -static const struct hns3_dbg_item tx_queue_info_items[] = { - { "QUEUE_ID", 2 }, - { "BD_NUM", 2 }, - { "TC", 2 }, - { "TAIL", 2 }, - { "HEAD", 2 }, - { "FBDNUM", 2 }, - { "OFFSET", 2 }, - { "PKTNUM", 5 }, - { "RING_EN", 2 }, - { "TX_RING_EN", 2 }, - { "BASE_ADDR", 10 }, -}; - static void hns3_dump_tx_queue_info(struct hns3_enet_ring *ring, - struct hnae3_ae_dev *ae_dev, char **result, - u32 index) + struct seq_file *s, u32 index) { + struct hnae3_ae_dev *ae_dev = hnae3_seq_file_to_ae_dev(s); + void __iomem *base = ring->tqp->io_base; u32 base_add_l, base_add_h; - u32 j = 0; - - sprintf(result[j++], "%u", index); - sprintf(result[j++], "%u", readl_relaxed(ring->tqp->io_base + - HNS3_RING_TX_RING_BD_NUM_REG)); - - sprintf(result[j++], "%u", readl_relaxed(ring->tqp->io_base + - HNS3_RING_TX_RING_TC_REG)); - - sprintf(result[j++], "%u", readl_relaxed(ring->tqp->io_base + - HNS3_RING_TX_RING_TAIL_REG)); - - sprintf(result[j++], "%u", readl_relaxed(ring->tqp->io_base + - HNS3_RING_TX_RING_HEAD_REG)); - - sprintf(result[j++], "%u", readl_relaxed(ring->tqp->io_base + - HNS3_RING_TX_RING_FBDNUM_REG)); - - sprintf(result[j++], "%u", readl_relaxed(ring->tqp->io_base + - HNS3_RING_TX_RING_OFFSET_REG)); - sprintf(result[j++], "%u", readl_relaxed(ring->tqp->io_base + - HNS3_RING_TX_RING_PKTNUM_RECORD_REG)); - - sprintf(result[j++], "%s", readl_relaxed(ring->tqp->io_base + - HNS3_RING_EN_REG) ? "on" : "off"); + seq_printf(s, "%-10u", index); + seq_printf(s, "%-8u", + readl_relaxed(base + HNS3_RING_TX_RING_BD_NUM_REG)); + seq_printf(s, "%-4u", readl_relaxed(base + HNS3_RING_TX_RING_TC_REG)); + seq_printf(s, "%-6u", readl_relaxed(base + HNS3_RING_TX_RING_TAIL_REG)); + seq_printf(s, "%-6u", readl_relaxed(base + HNS3_RING_TX_RING_HEAD_REG)); + seq_printf(s, "%-8u", + readl_relaxed(base + HNS3_RING_TX_RING_FBDNUM_REG)); + seq_printf(s, "%-8u", + readl_relaxed(base + HNS3_RING_TX_RING_OFFSET_REG)); + seq_printf(s, "%-11u", + readl_relaxed(base + HNS3_RING_TX_RING_PKTNUM_RECORD_REG)); + seq_printf(s, "%-9s", + str_on_off(readl_relaxed(base + HNS3_RING_EN_REG))); if (hnae3_ae_dev_tqp_txrx_indep_supported(ae_dev)) - sprintf(result[j++], "%s", readl_relaxed(ring->tqp->io_base + - HNS3_RING_TX_EN_REG) ? "on" : "off"); + seq_printf(s, "%-12s", + str_on_off(readl_relaxed(base + + HNS3_RING_TX_EN_REG))); else - sprintf(result[j++], "%s", "NA"); + seq_printf(s, "%-12s", "NA"); - base_add_h = readl_relaxed(ring->tqp->io_base + - HNS3_RING_TX_RING_BASEADDR_H_REG); - base_add_l = readl_relaxed(ring->tqp->io_base + - HNS3_RING_TX_RING_BASEADDR_L_REG); - sprintf(result[j++], "0x%08x%08x", base_add_h, base_add_l); + base_add_h = readl_relaxed(base + HNS3_RING_TX_RING_BASEADDR_H_REG); + base_add_l = readl_relaxed(base + HNS3_RING_TX_RING_BASEADDR_L_REG); + seq_printf(s, "0x%08x%08x\n", base_add_h, base_add_l); } -static int hns3_dbg_tx_queue_info(struct hnae3_handle *h, - char *buf, int len) +static int hns3_dbg_tx_queue_info(struct seq_file *s, void *data) { - char data_str[ARRAY_SIZE(tx_queue_info_items)][HNS3_DBG_DATA_STR_LEN]; - struct hnae3_ae_dev *ae_dev = pci_get_drvdata(h->pdev); - char *result[ARRAY_SIZE(tx_queue_info_items)]; + struct hnae3_handle *h = hnae3_seq_file_to_handle(s); struct hns3_nic_priv *priv = h->priv; - char content[HNS3_DBG_INFO_LEN]; struct hns3_enet_ring *ring; - int pos = 0; u32 i; if (!priv->ring) { @@ -797,12 +568,8 @@ static int hns3_dbg_tx_queue_info(struct hnae3_handle *h, return -EFAULT; } - for (i = 0; i < ARRAY_SIZE(tx_queue_info_items); i++) - result[i] = &data_str[i][0]; - - hns3_dbg_fill_content(content, sizeof(content), tx_queue_info_items, - NULL, ARRAY_SIZE(tx_queue_info_items)); - pos += scnprintf(buf + pos, len - pos, "%s", content); + seq_puts(s, "QUEUE_ID BD_NUM TC TAIL HEAD FBDNUM OFFSET "); + seq_puts(s, "PKTNUM RING_EN TX_RING_EN BASE_ADDR\n"); for (i = 0; i < h->kinfo.num_tqps; i++) { /* Each cycle needs to determine whether the instance is reset, @@ -814,339 +581,213 @@ static int hns3_dbg_tx_queue_info(struct hnae3_handle *h, return -EPERM; ring = &priv->ring[i]; - hns3_dump_tx_queue_info(ring, ae_dev, result, i); - hns3_dbg_fill_content(content, sizeof(content), - tx_queue_info_items, - (const char **)result, - ARRAY_SIZE(tx_queue_info_items)); - pos += scnprintf(buf + pos, len - pos, "%s", content); + hns3_dump_tx_queue_info(ring, s, i); } - hns3_dbg_tx_spare_info(ring, buf, len, h->kinfo.num_tqps, &pos); - return 0; } -static const struct hns3_dbg_item queue_map_items[] = { - { "local_queue_id", 2 }, - { "global_queue_id", 2 }, - { "vector_id", 2 }, -}; - -static int hns3_dbg_queue_map(struct hnae3_handle *h, char *buf, int len) +static int hns3_dbg_queue_map(struct seq_file *s, void *data) { - char data_str[ARRAY_SIZE(queue_map_items)][HNS3_DBG_DATA_STR_LEN]; - char *result[ARRAY_SIZE(queue_map_items)]; + struct hnae3_handle *h = hnae3_seq_file_to_handle(s); struct hns3_nic_priv *priv = h->priv; - char content[HNS3_DBG_INFO_LEN]; - int pos = 0; - int j; u32 i; if (!h->ae_algo->ops->get_global_queue_id) return -EOPNOTSUPP; - for (i = 0; i < ARRAY_SIZE(queue_map_items); i++) - result[i] = &data_str[i][0]; + seq_puts(s, "local_queue_id global_queue_id vector_id\n"); - hns3_dbg_fill_content(content, sizeof(content), queue_map_items, - NULL, ARRAY_SIZE(queue_map_items)); - pos += scnprintf(buf + pos, len - pos, "%s", content); for (i = 0; i < h->kinfo.num_tqps; i++) { if (!priv->ring || !priv->ring[i].tqp_vector) continue; - j = 0; - sprintf(result[j++], "%u", i); - sprintf(result[j++], "%u", - h->ae_algo->ops->get_global_queue_id(h, i)); - sprintf(result[j++], "%d", - priv->ring[i].tqp_vector->vector_irq); - hns3_dbg_fill_content(content, sizeof(content), queue_map_items, - (const char **)result, - ARRAY_SIZE(queue_map_items)); - pos += scnprintf(buf + pos, len - pos, "%s", content); + seq_printf(s, "%-16u%-17u%d\n", i, + h->ae_algo->ops->get_global_queue_id(h, i), + priv->ring[i].tqp_vector->vector_irq); } return 0; } -static const struct hns3_dbg_item rx_bd_info_items[] = { - { "BD_IDX", 3 }, - { "L234_INFO", 2 }, - { "PKT_LEN", 3 }, - { "SIZE", 4 }, - { "RSS_HASH", 4 }, - { "FD_ID", 2 }, - { "VLAN_TAG", 2 }, - { "O_DM_VLAN_ID_FB", 2 }, - { "OT_VLAN_TAG", 2 }, - { "BD_BASE_INFO", 2 }, - { "PTYPE", 2 }, - { "HW_CSUM", 2 }, -}; - static void hns3_dump_rx_bd_info(struct hns3_nic_priv *priv, - struct hns3_desc *desc, char **result, int idx) + struct hns3_desc *desc, struct seq_file *s, + int idx) { - unsigned int j = 0; - - sprintf(result[j++], "%d", idx); - sprintf(result[j++], "%#x", le32_to_cpu(desc->rx.l234_info)); - sprintf(result[j++], "%u", le16_to_cpu(desc->rx.pkt_len)); - sprintf(result[j++], "%u", le16_to_cpu(desc->rx.size)); - sprintf(result[j++], "%#x", le32_to_cpu(desc->rx.rss_hash)); - sprintf(result[j++], "%u", le16_to_cpu(desc->rx.fd_id)); - sprintf(result[j++], "%u", le16_to_cpu(desc->rx.vlan_tag)); - sprintf(result[j++], "%u", le16_to_cpu(desc->rx.o_dm_vlan_id_fb)); - sprintf(result[j++], "%u", le16_to_cpu(desc->rx.ot_vlan_tag)); - sprintf(result[j++], "%#x", le32_to_cpu(desc->rx.bd_base_info)); + seq_printf(s, "%-9d%#-11x%-10u%-8u%#-12x%-7u%-10u%-17u%-13u%#-14x", + idx, le32_to_cpu(desc->rx.l234_info), + le16_to_cpu(desc->rx.pkt_len), le16_to_cpu(desc->rx.size), + le32_to_cpu(desc->rx.rss_hash), le16_to_cpu(desc->rx.fd_id), + le16_to_cpu(desc->rx.vlan_tag), + le16_to_cpu(desc->rx.o_dm_vlan_id_fb), + le16_to_cpu(desc->rx.ot_vlan_tag), + le32_to_cpu(desc->rx.bd_base_info)); + if (test_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state)) { u32 ol_info = le32_to_cpu(desc->rx.ol_info); - sprintf(result[j++], "%5lu", hnae3_get_field(ol_info, - HNS3_RXD_PTYPE_M, - HNS3_RXD_PTYPE_S)); - sprintf(result[j++], "%7u", le16_to_cpu(desc->csum)); + seq_printf(s, "%-7lu%-9u\n", + hnae3_get_field(ol_info, HNS3_RXD_PTYPE_M, + HNS3_RXD_PTYPE_S), + le16_to_cpu(desc->csum)); } else { - sprintf(result[j++], "NA"); - sprintf(result[j++], "NA"); + seq_puts(s, "NA NA\n"); } } -static int hns3_dbg_rx_bd_info(struct hns3_dbg_data *d, char *buf, int len) +static int hns3_dbg_rx_bd_info(struct seq_file *s, void *private) { - char data_str[ARRAY_SIZE(rx_bd_info_items)][HNS3_DBG_DATA_STR_LEN]; - struct hns3_nic_priv *priv = d->handle->priv; - char *result[ARRAY_SIZE(rx_bd_info_items)]; - char content[HNS3_DBG_INFO_LEN]; + struct hns3_dbg_data *data = s->private; + struct hnae3_handle *h = data->handle; + struct hns3_nic_priv *priv = h->priv; struct hns3_enet_ring *ring; struct hns3_desc *desc; unsigned int i; - int pos = 0; - if (d->qid >= d->handle->kinfo.num_tqps) { - dev_err(&d->handle->pdev->dev, - "queue%u is not in use\n", d->qid); + if (data->qid >= h->kinfo.num_tqps) { + dev_err(&h->pdev->dev, "queue%u is not in use\n", data->qid); return -EINVAL; } - for (i = 0; i < ARRAY_SIZE(rx_bd_info_items); i++) - result[i] = &data_str[i][0]; + seq_printf(s, "Queue %u rx bd info:\n", data->qid); + seq_puts(s, "BD_IDX L234_INFO PKT_LEN SIZE "); + seq_puts(s, "RSS_HASH FD_ID VLAN_TAG O_DM_VLAN_ID_FB "); + seq_puts(s, "OT_VLAN_TAG BD_BASE_INFO PTYPE HW_CSUM\n"); - pos += scnprintf(buf + pos, len - pos, - "Queue %u rx bd info:\n", d->qid); - hns3_dbg_fill_content(content, sizeof(content), rx_bd_info_items, - NULL, ARRAY_SIZE(rx_bd_info_items)); - pos += scnprintf(buf + pos, len - pos, "%s", content); - - ring = &priv->ring[d->qid + d->handle->kinfo.num_tqps]; + ring = &priv->ring[data->qid + data->handle->kinfo.num_tqps]; for (i = 0; i < ring->desc_num; i++) { desc = &ring->desc[i]; - hns3_dump_rx_bd_info(priv, desc, result, i); - hns3_dbg_fill_content(content, sizeof(content), - rx_bd_info_items, (const char **)result, - ARRAY_SIZE(rx_bd_info_items)); - pos += scnprintf(buf + pos, len - pos, "%s", content); + hns3_dump_rx_bd_info(priv, desc, s, i); } return 0; } -static const struct hns3_dbg_item tx_bd_info_items[] = { - { "BD_IDX", 2 }, - { "ADDRESS", 13 }, - { "VLAN_TAG", 2 }, - { "SIZE", 2 }, - { "T_CS_VLAN_TSO", 2 }, - { "OT_VLAN_TAG", 3 }, - { "TV", 5 }, - { "OLT_VLAN_LEN", 2 }, - { "PAYLEN_OL4CS", 2 }, - { "BD_FE_SC_VLD", 2 }, - { "MSS_HW_CSUM", 0 }, -}; - -static void hns3_dump_tx_bd_info(struct hns3_desc *desc, char **result, int idx) +static void hns3_dump_tx_bd_info(struct hns3_desc *desc, struct seq_file *s, + int idx) { - unsigned int j = 0; - - sprintf(result[j++], "%d", idx); - sprintf(result[j++], "%#llx", le64_to_cpu(desc->addr)); - sprintf(result[j++], "%u", le16_to_cpu(desc->tx.vlan_tag)); - sprintf(result[j++], "%u", le16_to_cpu(desc->tx.send_size)); - sprintf(result[j++], "%#x", - le32_to_cpu(desc->tx.type_cs_vlan_tso_len)); - sprintf(result[j++], "%u", le16_to_cpu(desc->tx.outer_vlan_tag)); - sprintf(result[j++], "%u", le16_to_cpu(desc->tx.tv)); - sprintf(result[j++], "%u", - le32_to_cpu(desc->tx.ol_type_vlan_len_msec)); - sprintf(result[j++], "%#x", le32_to_cpu(desc->tx.paylen_ol4cs)); - sprintf(result[j++], "%#x", le16_to_cpu(desc->tx.bdtp_fe_sc_vld_ra_ri)); - sprintf(result[j++], "%u", le16_to_cpu(desc->tx.mss_hw_csum)); + seq_printf(s, "%-8d%#-20llx%-10u%-6u%#-15x%-14u%-7u%-16u%#-14x%#-14x%-11u\n", + idx, le64_to_cpu(desc->addr), + le16_to_cpu(desc->tx.vlan_tag), + le16_to_cpu(desc->tx.send_size), + le32_to_cpu(desc->tx.type_cs_vlan_tso_len), + le16_to_cpu(desc->tx.outer_vlan_tag), + le16_to_cpu(desc->tx.tv), + le32_to_cpu(desc->tx.ol_type_vlan_len_msec), + le32_to_cpu(desc->tx.paylen_ol4cs), + le16_to_cpu(desc->tx.bdtp_fe_sc_vld_ra_ri), + le16_to_cpu(desc->tx.mss_hw_csum)); } -static int hns3_dbg_tx_bd_info(struct hns3_dbg_data *d, char *buf, int len) +static int hns3_dbg_tx_bd_info(struct seq_file *s, void *private) { - char data_str[ARRAY_SIZE(tx_bd_info_items)][HNS3_DBG_DATA_STR_LEN]; - struct hns3_nic_priv *priv = d->handle->priv; - char *result[ARRAY_SIZE(tx_bd_info_items)]; - char content[HNS3_DBG_INFO_LEN]; + struct hns3_dbg_data *data = s->private; + struct hnae3_handle *h = data->handle; + struct hns3_nic_priv *priv = h->priv; struct hns3_enet_ring *ring; struct hns3_desc *desc; unsigned int i; - int pos = 0; - if (d->qid >= d->handle->kinfo.num_tqps) { - dev_err(&d->handle->pdev->dev, - "queue%u is not in use\n", d->qid); + if (data->qid >= h->kinfo.num_tqps) { + dev_err(&h->pdev->dev, "queue%u is not in use\n", data->qid); return -EINVAL; } - for (i = 0; i < ARRAY_SIZE(tx_bd_info_items); i++) - result[i] = &data_str[i][0]; - - pos += scnprintf(buf + pos, len - pos, - "Queue %u tx bd info:\n", d->qid); - hns3_dbg_fill_content(content, sizeof(content), tx_bd_info_items, - NULL, ARRAY_SIZE(tx_bd_info_items)); - pos += scnprintf(buf + pos, len - pos, "%s", content); + seq_printf(s, "Queue %u tx bd info:\n", data->qid); + seq_puts(s, "BD_IDX ADDRESS VLAN_TAG SIZE "); + seq_puts(s, "T_CS_VLAN_TSO OT_VLAN_TAG TV OLT_VLAN_LEN "); + seq_puts(s, "PAYLEN_OL4CS BD_FE_SC_VLD MSS_HW_CSUM\n"); - ring = &priv->ring[d->qid]; + ring = &priv->ring[data->qid]; for (i = 0; i < ring->desc_num; i++) { desc = &ring->desc[i]; - hns3_dump_tx_bd_info(desc, result, i); - hns3_dbg_fill_content(content, sizeof(content), - tx_bd_info_items, (const char **)result, - ARRAY_SIZE(tx_bd_info_items)); - pos += scnprintf(buf + pos, len - pos, "%s", content); + hns3_dump_tx_bd_info(desc, s, i); } return 0; } -static void -hns3_dbg_dev_caps(struct hnae3_handle *h, char *buf, int len, int *pos) +static void hns3_dbg_dev_caps(struct hnae3_handle *h, struct seq_file *s) { - struct hnae3_ae_dev *ae_dev = pci_get_drvdata(h->pdev); - const char * const str[] = {"no", "yes"}; + struct hnae3_ae_dev *ae_dev = hns3_get_ae_dev(h); unsigned long *caps = ae_dev->caps; u32 i, state; - *pos += scnprintf(buf + *pos, len - *pos, "dev capability:\n"); + seq_puts(s, "dev capability:\n"); for (i = 0; i < ARRAY_SIZE(hns3_dbg_cap); i++) { state = test_bit(hns3_dbg_cap[i].cap_bit, caps); - *pos += scnprintf(buf + *pos, len - *pos, "%s: %s\n", - hns3_dbg_cap[i].name, str[state]); + seq_printf(s, "%s: %s\n", hns3_dbg_cap[i].name, + str_yes_no(state)); } - *pos += scnprintf(buf + *pos, len - *pos, "\n"); + seq_puts(s, "\n"); } -static void -hns3_dbg_dev_specs(struct hnae3_handle *h, char *buf, int len, int *pos) +static void hns3_dbg_dev_specs(struct hnae3_handle *h, struct seq_file *s) { struct hnae3_ae_dev *ae_dev = pci_get_drvdata(h->pdev); struct hnae3_dev_specs *dev_specs = &ae_dev->dev_specs; struct hnae3_knic_private_info *kinfo = &h->kinfo; struct net_device *dev = kinfo->netdev; - *pos += scnprintf(buf + *pos, len - *pos, "dev_spec:\n"); - *pos += scnprintf(buf + *pos, len - *pos, "MAC entry num: %u\n", - dev_specs->mac_entry_num); - *pos += scnprintf(buf + *pos, len - *pos, "MNG entry num: %u\n", - dev_specs->mng_entry_num); - *pos += scnprintf(buf + *pos, len - *pos, "MAX non tso bd num: %u\n", - dev_specs->max_non_tso_bd_num); - *pos += scnprintf(buf + *pos, len - *pos, "RSS ind tbl size: %u\n", - dev_specs->rss_ind_tbl_size); - *pos += scnprintf(buf + *pos, len - *pos, "RSS key size: %u\n", - dev_specs->rss_key_size); - *pos += scnprintf(buf + *pos, len - *pos, "RSS size: %u\n", - kinfo->rss_size); - *pos += scnprintf(buf + *pos, len - *pos, "Allocated RSS size: %u\n", - kinfo->req_rss_size); - *pos += scnprintf(buf + *pos, len - *pos, - "Task queue pairs numbers: %u\n", - kinfo->num_tqps); - *pos += scnprintf(buf + *pos, len - *pos, "RX buffer length: %u\n", - kinfo->rx_buf_len); - *pos += scnprintf(buf + *pos, len - *pos, "Desc num per TX queue: %u\n", - kinfo->num_tx_desc); - *pos += scnprintf(buf + *pos, len - *pos, "Desc num per RX queue: %u\n", - kinfo->num_rx_desc); - *pos += scnprintf(buf + *pos, len - *pos, - "Total number of enabled TCs: %u\n", - kinfo->tc_info.num_tc); - *pos += scnprintf(buf + *pos, len - *pos, "MAX INT QL: %u\n", - dev_specs->int_ql_max); - *pos += scnprintf(buf + *pos, len - *pos, "MAX INT GL: %u\n", - dev_specs->max_int_gl); - *pos += scnprintf(buf + *pos, len - *pos, "MAX TM RATE: %u\n", - dev_specs->max_tm_rate); - *pos += scnprintf(buf + *pos, len - *pos, "MAX QSET number: %u\n", - dev_specs->max_qset_num); - *pos += scnprintf(buf + *pos, len - *pos, "umv size: %u\n", - dev_specs->umv_size); - *pos += scnprintf(buf + *pos, len - *pos, "mc mac size: %u\n", - dev_specs->mc_mac_size); - *pos += scnprintf(buf + *pos, len - *pos, "MAC statistics number: %u\n", - dev_specs->mac_stats_num); - *pos += scnprintf(buf + *pos, len - *pos, - "TX timeout threshold: %d seconds\n", - dev->watchdog_timeo / HZ); - *pos += scnprintf(buf + *pos, len - *pos, "Hilink Version: %u\n", - dev_specs->hilink_version); + seq_puts(s, "dev_spec:\n"); + seq_printf(s, "MAC entry num: %u\n", dev_specs->mac_entry_num); + seq_printf(s, "MNG entry num: %u\n", dev_specs->mng_entry_num); + seq_printf(s, "MAX non tso bd num: %u\n", + dev_specs->max_non_tso_bd_num); + seq_printf(s, "RSS ind tbl size: %u\n", dev_specs->rss_ind_tbl_size); + seq_printf(s, "RSS key size: %u\n", dev_specs->rss_key_size); + seq_printf(s, "RSS size: %u\n", kinfo->rss_size); + seq_printf(s, "Allocated RSS size: %u\n", kinfo->req_rss_size); + seq_printf(s, "Task queue pairs numbers: %u\n", kinfo->num_tqps); + seq_printf(s, "RX buffer length: %u\n", kinfo->rx_buf_len); + seq_printf(s, "Desc num per TX queue: %u\n", kinfo->num_tx_desc); + seq_printf(s, "Desc num per RX queue: %u\n", kinfo->num_rx_desc); + seq_printf(s, "Total number of enabled TCs: %u\n", + kinfo->tc_info.num_tc); + seq_printf(s, "MAX INT QL: %u\n", dev_specs->int_ql_max); + seq_printf(s, "MAX INT GL: %u\n", dev_specs->max_int_gl); + seq_printf(s, "MAX TM RATE: %u\n", dev_specs->max_tm_rate); + seq_printf(s, "MAX QSET number: %u\n", dev_specs->max_qset_num); + seq_printf(s, "umv size: %u\n", dev_specs->umv_size); + seq_printf(s, "mc mac size: %u\n", dev_specs->mc_mac_size); + seq_printf(s, "MAC statistics number: %u\n", dev_specs->mac_stats_num); + seq_printf(s, "TX timeout threshold: %d seconds\n", + dev->watchdog_timeo / HZ); + seq_printf(s, "mac tunnel number: %u\n", dev_specs->tnl_num); + seq_printf(s, "Hilink Version: %u\n", dev_specs->hilink_version); } -static int hns3_dbg_dev_info(struct hnae3_handle *h, char *buf, int len) +static int hns3_dbg_dev_info(struct seq_file *s, void *data) { - int pos = 0; - - hns3_dbg_dev_caps(h, buf, len, &pos); + struct hnae3_handle *h = hnae3_seq_file_to_handle(s); - hns3_dbg_dev_specs(h, buf, len, &pos); + hns3_dbg_dev_caps(h, s); + hns3_dbg_dev_specs(h, s); return 0; } -static const struct hns3_dbg_item page_pool_info_items[] = { - { "QUEUE_ID", 2 }, - { "ALLOCATE_CNT", 2 }, - { "FREE_CNT", 6 }, - { "POOL_SIZE(PAGE_NUM)", 2 }, - { "ORDER", 2 }, - { "NUMA_ID", 2 }, - { "MAX_LEN", 2 }, -}; - static void hns3_dump_page_pool_info(struct hns3_enet_ring *ring, - char **result, u32 index) + struct seq_file *s, u32 index) { - u32 j = 0; - - sprintf(result[j++], "%u", index); - sprintf(result[j++], "%u", - READ_ONCE(ring->page_pool->pages_state_hold_cnt)); - sprintf(result[j++], "%d", - atomic_read(&ring->page_pool->pages_state_release_cnt)); - sprintf(result[j++], "%u", ring->page_pool->p.pool_size); - sprintf(result[j++], "%u", ring->page_pool->p.order); - sprintf(result[j++], "%d", ring->page_pool->p.nid); - sprintf(result[j++], "%uK", ring->page_pool->p.max_len / 1024); + seq_printf(s, "%-10u%-14u%-14d%-21u%-7u%-9d%uK\n", + index, + READ_ONCE(ring->page_pool->pages_state_hold_cnt), + atomic_read(&ring->page_pool->pages_state_release_cnt), + ring->page_pool->p.pool_size, + ring->page_pool->p.order, + ring->page_pool->p.nid, + ring->page_pool->p.max_len / 1024); } -static int -hns3_dbg_page_pool_info(struct hnae3_handle *h, char *buf, int len) +static int hns3_dbg_page_pool_info(struct seq_file *s, void *data) { - char data_str[ARRAY_SIZE(page_pool_info_items)][HNS3_DBG_DATA_STR_LEN]; - char *result[ARRAY_SIZE(page_pool_info_items)]; + struct hnae3_handle *h = hnae3_seq_file_to_handle(s); struct hns3_nic_priv *priv = h->priv; - char content[HNS3_DBG_INFO_LEN]; struct hns3_enet_ring *ring; - int pos = 0; u32 i; if (!priv->ring) { @@ -1159,176 +800,44 @@ hns3_dbg_page_pool_info(struct hnae3_handle *h, char *buf, int len) return -EFAULT; } - for (i = 0; i < ARRAY_SIZE(page_pool_info_items); i++) - result[i] = &data_str[i][0]; + seq_puts(s, "QUEUE_ID ALLOCATE_CNT FREE_CNT "); + seq_puts(s, "POOL_SIZE(PAGE_NUM) ORDER NUMA_ID MAX_LEN\n"); - hns3_dbg_fill_content(content, sizeof(content), page_pool_info_items, - NULL, ARRAY_SIZE(page_pool_info_items)); - pos += scnprintf(buf + pos, len - pos, "%s", content); for (i = 0; i < h->kinfo.num_tqps; i++) { if (!test_bit(HNS3_NIC_STATE_INITED, &priv->state) || test_bit(HNS3_NIC_STATE_RESETTING, &priv->state)) return -EPERM; + ring = &priv->ring[(u32)(i + h->kinfo.num_tqps)]; - hns3_dump_page_pool_info(ring, result, i); - hns3_dbg_fill_content(content, sizeof(content), - page_pool_info_items, - (const char **)result, - ARRAY_SIZE(page_pool_info_items)); - pos += scnprintf(buf + pos, len - pos, "%s", content); + hns3_dump_page_pool_info(ring, s, i); } return 0; } -static int hns3_dbg_get_cmd_index(struct hns3_dbg_data *dbg_data, u32 *index) -{ - u32 i; - - for (i = 0; i < ARRAY_SIZE(hns3_dbg_cmd); i++) { - if (hns3_dbg_cmd[i].cmd == dbg_data->cmd) { - *index = i; - return 0; - } - } - - dev_err(&dbg_data->handle->pdev->dev, "unknown command(%d)\n", - dbg_data->cmd); - return -EINVAL; -} - -static const struct hns3_dbg_func hns3_dbg_cmd_func[] = { - { - .cmd = HNAE3_DBG_CMD_QUEUE_MAP, - .dbg_dump = hns3_dbg_queue_map, - }, - { - .cmd = HNAE3_DBG_CMD_DEV_INFO, - .dbg_dump = hns3_dbg_dev_info, - }, - { - .cmd = HNAE3_DBG_CMD_TX_BD, - .dbg_dump_bd = hns3_dbg_tx_bd_info, - }, - { - .cmd = HNAE3_DBG_CMD_RX_BD, - .dbg_dump_bd = hns3_dbg_rx_bd_info, - }, - { - .cmd = HNAE3_DBG_CMD_RX_QUEUE_INFO, - .dbg_dump = hns3_dbg_rx_queue_info, - }, - { - .cmd = HNAE3_DBG_CMD_TX_QUEUE_INFO, - .dbg_dump = hns3_dbg_tx_queue_info, - }, - { - .cmd = HNAE3_DBG_CMD_PAGE_POOL_INFO, - .dbg_dump = hns3_dbg_page_pool_info, - }, - { - .cmd = HNAE3_DBG_CMD_COAL_INFO, - .dbg_dump = hns3_dbg_coal_info, - }, -}; - -static int hns3_dbg_read_cmd(struct hns3_dbg_data *dbg_data, - enum hnae3_dbg_cmd cmd, char *buf, int len) -{ - const struct hnae3_ae_ops *ops = dbg_data->handle->ae_algo->ops; - const struct hns3_dbg_func *cmd_func; - u32 i; - - for (i = 0; i < ARRAY_SIZE(hns3_dbg_cmd_func); i++) { - if (cmd == hns3_dbg_cmd_func[i].cmd) { - cmd_func = &hns3_dbg_cmd_func[i]; - if (cmd_func->dbg_dump) - return cmd_func->dbg_dump(dbg_data->handle, buf, - len); - else - return cmd_func->dbg_dump_bd(dbg_data, buf, - len); - } - } - - if (!ops->dbg_read_cmd) - return -EOPNOTSUPP; - - return ops->dbg_read_cmd(dbg_data->handle, cmd, buf, len); -} - -static ssize_t hns3_dbg_read(struct file *filp, char __user *buffer, - size_t count, loff_t *ppos) +static int hns3_dbg_bd_info_show(struct seq_file *s, void *private) { - struct hns3_dbg_data *dbg_data = filp->private_data; - struct hnae3_handle *handle = dbg_data->handle; - struct hns3_nic_priv *priv = handle->priv; - ssize_t size = 0; - char **save_buf; - char *read_buf; - u32 index; - int ret; - - ret = hns3_dbg_get_cmd_index(dbg_data, &index); - if (ret) - return ret; - - mutex_lock(&handle->dbgfs_lock); - save_buf = &handle->dbgfs_buf[index]; + struct hns3_dbg_data *data = s->private; + struct hnae3_handle *h = data->handle; + struct hns3_nic_priv *priv = h->priv; if (!test_bit(HNS3_NIC_STATE_INITED, &priv->state) || - test_bit(HNS3_NIC_STATE_RESETTING, &priv->state)) { - ret = -EBUSY; - goto out; - } - - if (*save_buf) { - read_buf = *save_buf; - } else { - read_buf = kvzalloc(hns3_dbg_cmd[index].buf_len, GFP_KERNEL); - if (!read_buf) { - ret = -ENOMEM; - goto out; - } + test_bit(HNS3_NIC_STATE_RESETTING, &priv->state)) + return -EBUSY; - /* save the buffer addr until the last read operation */ - *save_buf = read_buf; + if (data->cmd == HNAE3_DBG_CMD_TX_BD) + return hns3_dbg_tx_bd_info(s, private); + else if (data->cmd == HNAE3_DBG_CMD_RX_BD) + return hns3_dbg_rx_bd_info(s, private); - /* get data ready for the first time to read */ - ret = hns3_dbg_read_cmd(dbg_data, hns3_dbg_cmd[index].cmd, - read_buf, hns3_dbg_cmd[index].buf_len); - if (ret) - goto out; - } - - size = simple_read_from_buffer(buffer, count, ppos, read_buf, - strlen(read_buf)); - if (size > 0) { - mutex_unlock(&handle->dbgfs_lock); - return size; - } - -out: - /* free the buffer for the last read operation */ - if (*save_buf) { - kvfree(*save_buf); - *save_buf = NULL; - } - - mutex_unlock(&handle->dbgfs_lock); - return ret; + return -EOPNOTSUPP; } - -static const struct file_operations hns3_dbg_fops = { - .owner = THIS_MODULE, - .open = simple_open, - .read = hns3_dbg_read, -}; +DEFINE_SHOW_ATTRIBUTE(hns3_dbg_bd_info); static int hns3_dbg_bd_file_init(struct hnae3_handle *handle, u32 cmd) { - struct dentry *entry_dir; struct hns3_dbg_data *data; + struct dentry *entry_dir; u16 max_queue_num; unsigned int i; @@ -1347,45 +856,77 @@ static int hns3_dbg_bd_file_init(struct hnae3_handle *handle, u32 cmd) data[i].qid = i; sprintf(name, "%s%u", hns3_dbg_cmd[cmd].name, i); debugfs_create_file(name, 0400, entry_dir, &data[i], - &hns3_dbg_fops); + &hns3_dbg_bd_info_fops); } return 0; } -static int -hns3_dbg_common_file_init(struct hnae3_handle *handle, u32 cmd) +static int hns3_dbg_common_init_t1(struct hnae3_handle *handle, u32 cmd) { - struct hns3_dbg_data *data; + struct device *dev = &handle->pdev->dev; struct dentry *entry_dir; + read_func func = NULL; + + switch (hns3_dbg_cmd[cmd].cmd) { + case HNAE3_DBG_CMD_TX_QUEUE_INFO: + func = hns3_dbg_tx_queue_info; + break; + case HNAE3_DBG_CMD_RX_QUEUE_INFO: + func = hns3_dbg_rx_queue_info; + break; + case HNAE3_DBG_CMD_QUEUE_MAP: + func = hns3_dbg_queue_map; + break; + case HNAE3_DBG_CMD_PAGE_POOL_INFO: + func = hns3_dbg_page_pool_info; + break; + case HNAE3_DBG_CMD_COAL_INFO: + func = hns3_dbg_coal_info; + break; + case HNAE3_DBG_CMD_DEV_INFO: + func = hns3_dbg_dev_info; + break; + default: + return -EINVAL; + } - data = devm_kzalloc(&handle->pdev->dev, sizeof(*data), GFP_KERNEL); - if (!data) - return -ENOMEM; + entry_dir = hns3_dbg_dentry[hns3_dbg_cmd[cmd].dentry].dentry; + debugfs_create_devm_seqfile(dev, hns3_dbg_cmd[cmd].name, entry_dir, + func); + + return 0; +} + +static int hns3_dbg_common_init_t2(struct hnae3_handle *handle, u32 cmd) +{ + const struct hnae3_ae_ops *ops = hns3_get_ops(handle); + struct device *dev = &handle->pdev->dev; + struct dentry *entry_dir; + read_func func; + int ret; + + if (!ops->dbg_get_read_func) + return 0; + + ret = ops->dbg_get_read_func(handle, hns3_dbg_cmd[cmd].cmd, &func); + if (ret) + return ret; - data->handle = handle; - data->cmd = hns3_dbg_cmd[cmd].cmd; entry_dir = hns3_dbg_dentry[hns3_dbg_cmd[cmd].dentry].dentry; - debugfs_create_file(hns3_dbg_cmd[cmd].name, 0400, entry_dir, - data, &hns3_dbg_fops); + debugfs_create_devm_seqfile(dev, hns3_dbg_cmd[cmd].name, entry_dir, + func); return 0; } int hns3_dbg_init(struct hnae3_handle *handle) { - struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); + struct hnae3_ae_dev *ae_dev = hns3_get_ae_dev(handle); const char *name = pci_name(handle->pdev); int ret; u32 i; - handle->dbgfs_buf = devm_kcalloc(&handle->pdev->dev, - ARRAY_SIZE(hns3_dbg_cmd), - sizeof(*handle->dbgfs_buf), - GFP_KERNEL); - if (!handle->dbgfs_buf) - return -ENOMEM; - hns3_dbg_dentry[HNS3_DBG_DENTRY_COMMON].dentry = debugfs_create_dir(name, hns3_dbgfs_root); handle->hnae3_dbgfs = hns3_dbg_dentry[HNS3_DBG_DENTRY_COMMON].dentry; @@ -1395,8 +936,6 @@ int hns3_dbg_init(struct hnae3_handle *handle) debugfs_create_dir(hns3_dbg_dentry[i].name, handle->hnae3_dbgfs); - mutex_init(&handle->dbgfs_lock); - for (i = 0; i < ARRAY_SIZE(hns3_dbg_cmd); i++) { if ((hns3_dbg_cmd[i].cmd == HNAE3_DBG_CMD_TM_NODES && ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2) || @@ -1425,24 +964,13 @@ int hns3_dbg_init(struct hnae3_handle *handle) out: debugfs_remove_recursive(handle->hnae3_dbgfs); handle->hnae3_dbgfs = NULL; - mutex_destroy(&handle->dbgfs_lock); return ret; } void hns3_dbg_uninit(struct hnae3_handle *handle) { - u32 i; - debugfs_remove_recursive(handle->hnae3_dbgfs); handle->hnae3_dbgfs = NULL; - - for (i = 0; i < ARRAY_SIZE(hns3_dbg_cmd); i++) - if (handle->dbgfs_buf[i]) { - kvfree(handle->dbgfs_buf[i]); - handle->dbgfs_buf[i] = NULL; - } - - mutex_destroy(&handle->dbgfs_lock); } void hns3_dbg_register_debugfs(const char *debugfs_dir_name) diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.h b/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.h index 4a5ef8a90a10..57c9d3fc1b27 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.h +++ b/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.h @@ -6,15 +6,6 @@ #include "hnae3.h" -#define HNS3_DBG_READ_LEN 65536 -#define HNS3_DBG_READ_LEN_128KB 0x20000 -#define HNS3_DBG_READ_LEN_1MB 0x100000 -#define HNS3_DBG_READ_LEN_4MB 0x400000 -#define HNS3_DBG_READ_LEN_5MB 0x500000 -#define HNS3_DBG_WRITE_LEN 1024 - -#define HNS3_DBG_DATA_STR_LEN 32 -#define HNS3_DBG_INFO_LEN 256 #define HNS3_DBG_ITEM_NAME_LEN 32 #define HNS3_DBG_FILE_NAME_LEN 16 @@ -49,16 +40,9 @@ struct hns3_dbg_cmd_info { const char *name; enum hnae3_dbg_cmd cmd; enum hns3_dbg_dentry_type dentry; - u32 buf_len; int (*init)(struct hnae3_handle *handle, unsigned int cmd); }; -struct hns3_dbg_func { - enum hnae3_dbg_cmd cmd; - int (*dbg_dump)(struct hnae3_handle *handle, char *buf, int len); - int (*dbg_dump_bd)(struct hns3_dbg_data *data, char *buf, int len); -}; - struct hns3_dbg_cap_info { const char *name; enum HNAE3_DEV_CAP_BITS cap_bit; diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c index 19668a8d22f7..bfa5568baa92 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c +++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c @@ -11,6 +11,7 @@ #include <linux/irq.h> #include <linux/ip.h> #include <linux/ipv6.h> +#include <linux/iommu.h> #include <linux/module.h> #include <linux/pci.h> #include <linux/skbuff.h> @@ -473,20 +474,14 @@ static void hns3_mask_vector_irq(struct hns3_enet_tqp_vector *tqp_vector, writel(mask_en, tqp_vector->mask_addr); } -static void hns3_vector_enable(struct hns3_enet_tqp_vector *tqp_vector) +static void hns3_irq_enable(struct hns3_enet_tqp_vector *tqp_vector) { napi_enable(&tqp_vector->napi); enable_irq(tqp_vector->vector_irq); - - /* enable vector */ - hns3_mask_vector_irq(tqp_vector, 1); } -static void hns3_vector_disable(struct hns3_enet_tqp_vector *tqp_vector) +static void hns3_irq_disable(struct hns3_enet_tqp_vector *tqp_vector) { - /* disable vector */ - hns3_mask_vector_irq(tqp_vector, 0); - disable_irq(tqp_vector->vector_irq); napi_disable(&tqp_vector->napi); cancel_work_sync(&tqp_vector->rx_group.dim.work); @@ -553,9 +548,9 @@ void hns3_set_vector_coalesce_rx_ql(struct hns3_enet_tqp_vector *tqp_vector, static void hns3_vector_coalesce_init(struct hns3_enet_tqp_vector *tqp_vector, struct hns3_nic_priv *priv) { - struct hnae3_ae_dev *ae_dev = pci_get_drvdata(priv->ae_handle->pdev); struct hns3_enet_coalesce *tx_coal = &tqp_vector->tx_group.coal; struct hns3_enet_coalesce *rx_coal = &tqp_vector->rx_group.coal; + struct hnae3_ae_dev *ae_dev = hns3_get_ae_dev(priv->ae_handle); struct hns3_enet_coalesce *ptx_coal = &priv->tx_coal; struct hns3_enet_coalesce *prx_coal = &priv->rx_coal; @@ -707,11 +702,42 @@ static int hns3_set_rx_cpu_rmap(struct net_device *netdev) return 0; } +static void hns3_enable_irqs_and_tqps(struct net_device *netdev) +{ + struct hns3_nic_priv *priv = netdev_priv(netdev); + struct hnae3_handle *h = priv->ae_handle; + u16 i; + + for (i = 0; i < priv->vector_num; i++) + hns3_irq_enable(&priv->tqp_vector[i]); + + for (i = 0; i < priv->vector_num; i++) + hns3_mask_vector_irq(&priv->tqp_vector[i], 1); + + for (i = 0; i < h->kinfo.num_tqps; i++) + hns3_tqp_enable(h->kinfo.tqp[i]); +} + +static void hns3_disable_irqs_and_tqps(struct net_device *netdev) +{ + struct hns3_nic_priv *priv = netdev_priv(netdev); + struct hnae3_handle *h = priv->ae_handle; + u16 i; + + for (i = 0; i < h->kinfo.num_tqps; i++) + hns3_tqp_disable(h->kinfo.tqp[i]); + + for (i = 0; i < priv->vector_num; i++) + hns3_mask_vector_irq(&priv->tqp_vector[i], 0); + + for (i = 0; i < priv->vector_num; i++) + hns3_irq_disable(&priv->tqp_vector[i]); +} + static int hns3_nic_net_up(struct net_device *netdev) { struct hns3_nic_priv *priv = netdev_priv(netdev); struct hnae3_handle *h = priv->ae_handle; - int i, j; int ret; ret = hns3_nic_reset_all_ring(h); @@ -720,23 +746,13 @@ static int hns3_nic_net_up(struct net_device *netdev) clear_bit(HNS3_NIC_STATE_DOWN, &priv->state); - /* enable the vectors */ - for (i = 0; i < priv->vector_num; i++) - hns3_vector_enable(&priv->tqp_vector[i]); - - /* enable rcb */ - for (j = 0; j < h->kinfo.num_tqps; j++) - hns3_tqp_enable(h->kinfo.tqp[j]); + hns3_enable_irqs_and_tqps(netdev); /* start the ae_dev */ ret = h->ae_algo->ops->start ? h->ae_algo->ops->start(h) : 0; if (ret) { set_bit(HNS3_NIC_STATE_DOWN, &priv->state); - while (j--) - hns3_tqp_disable(h->kinfo.tqp[j]); - - for (j = i - 1; j >= 0; j--) - hns3_vector_disable(&priv->tqp_vector[j]); + hns3_disable_irqs_and_tqps(netdev); } return ret; @@ -823,17 +839,9 @@ static void hns3_reset_tx_queue(struct hnae3_handle *h) static void hns3_nic_net_down(struct net_device *netdev) { struct hns3_nic_priv *priv = netdev_priv(netdev); - struct hnae3_handle *h = hns3_get_handle(netdev); const struct hnae3_ae_ops *ops; - int i; - - /* disable vectors */ - for (i = 0; i < priv->vector_num; i++) - hns3_vector_disable(&priv->tqp_vector[i]); - /* disable rcb */ - for (i = 0; i < h->kinfo.num_tqps; i++) - hns3_tqp_disable(h->kinfo.tqp[i]); + hns3_disable_irqs_and_tqps(netdev); /* stop ae_dev */ ops = priv->ae_handle->ae_algo->ops; @@ -953,7 +961,7 @@ static void hns3_nic_set_rx_mode(struct net_device *netdev) void hns3_request_update_promisc_mode(struct hnae3_handle *handle) { - const struct hnae3_ae_ops *ops = handle->ae_algo->ops; + const struct hnae3_ae_ops *ops = hns3_get_ops(handle); if (ops->request_update_promisc_mode) ops->request_update_promisc_mode(handle); @@ -1032,6 +1040,8 @@ static bool hns3_can_use_tx_sgl(struct hns3_enet_ring *ring, static void hns3_init_tx_spare_buffer(struct hns3_enet_ring *ring) { u32 alloc_size = ring->tqp->handle->kinfo.tx_spare_buf_size; + struct net_device *netdev = ring_to_netdev(ring); + struct hns3_nic_priv *priv = netdev_priv(netdev); struct hns3_tx_spare *tx_spare; struct page *page; dma_addr_t dma; @@ -1073,6 +1083,7 @@ static void hns3_init_tx_spare_buffer(struct hns3_enet_ring *ring) tx_spare->buf = page_address(page); tx_spare->len = PAGE_SIZE << order; ring->tx_spare = tx_spare; + ring->tx_copybreak = priv->tx_copybreak; return; dma_mapping_error: @@ -1297,7 +1308,7 @@ static int hns3_get_l4_protocol(struct sk_buff *skb, u8 *ol4_proto, static bool hns3_tunnel_csum_bug(struct sk_buff *skb) { struct hns3_nic_priv *priv = netdev_priv(skb->dev); - struct hnae3_ae_dev *ae_dev = pci_get_drvdata(priv->ae_handle->pdev); + struct hnae3_ae_dev *ae_dev = hns3_get_ae_dev(priv->ae_handle); union l4_hdr_info l4; /* device version above V3(include V3), the hardware can @@ -1497,7 +1508,7 @@ static int hns3_handle_vtags(struct hns3_enet_ring *tx_ring, * VLAN enabled, only one VLAN header is allowed in skb, otherwise it * will cause RAS error. */ - ae_dev = pci_get_drvdata(handle->pdev); + ae_dev = hns3_get_ae_dev(handle); if (unlikely(skb_vlan_tagged_multi(skb) && ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2 && handle->port_base_vlan_state == @@ -1683,8 +1694,8 @@ static int hns3_fill_desc(struct hns3_enet_ring *ring, dma_addr_t dma, #define HNS3_LIKELY_BD_NUM 1 struct hns3_desc *desc = &ring->desc[ring->next_to_use]; - unsigned int frag_buf_num; - int k, sizeoflast; + unsigned int frag_buf_num, k; + int sizeoflast; if (likely(size <= HNS3_MAX_BD_SIZE)) { desc->addr = cpu_to_le64(dma); @@ -1856,7 +1867,7 @@ static bool hns3_skb_need_linearized(struct sk_buff *skb, unsigned int *bd_size, unsigned int bd_num, u8 max_non_tso_bd_num) { unsigned int tot_len = 0; - int i; + unsigned int i; for (i = 0; i < max_non_tso_bd_num - 1U; i++) tot_len += bd_size[i]; @@ -1884,7 +1895,7 @@ static bool hns3_skb_need_linearized(struct sk_buff *skb, unsigned int *bd_size, void hns3_shinfo_pack(struct skb_shared_info *shinfo, __u32 *size) { - int i; + u32 i; for (i = 0; i < MAX_SKB_FRAGS; i++) size[i] = skb_frag_size(&shinfo->frags[i]); @@ -2068,8 +2079,6 @@ static void hns3_tx_push_bd(struct hns3_enet_ring *ring, int num) __iowrite64_copy(ring->tqp->mem_base, desc, (sizeof(struct hns3_desc) * HNS3_MAX_PUSH_BD_NUM) / HNS3_BYTES_PER_64BIT); - - io_stop_wc(); } static void hns3_tx_mem_doorbell(struct hns3_enet_ring *ring) @@ -2088,8 +2097,6 @@ static void hns3_tx_mem_doorbell(struct hns3_enet_ring *ring) u64_stats_update_begin(&ring->syncp); ring->stats.tx_mem_doorbell += ring->pending_buf; u64_stats_update_end(&ring->syncp); - - io_stop_wc(); } static void hns3_tx_doorbell(struct hns3_enet_ring *ring, int num, @@ -2103,7 +2110,7 @@ static void hns3_tx_doorbell(struct hns3_enet_ring *ring, int num, */ if (test_bit(HNS3_NIC_STATE_TX_PUSH_ENABLE, &priv->state) && num && !ring->pending_buf && num <= HNS3_MAX_PUSH_BD_NUM && doorbell) { - /* This smp_store_release() pairs with smp_load_aquire() in + /* This smp_store_release() pairs with smp_load_acquire() in * hns3_nic_reclaim_desc(). Ensure that the BD valid bit * is updated. */ @@ -2119,7 +2126,7 @@ static void hns3_tx_doorbell(struct hns3_enet_ring *ring, int num, return; } - /* This smp_store_release() pairs with smp_load_aquire() in + /* This smp_store_release() pairs with smp_load_acquire() in * hns3_nic_reclaim_desc(). Ensure that the BD valid bit is updated. */ smp_store_release(&ring->last_to_use, ring->next_to_use); @@ -2204,9 +2211,9 @@ static int hns3_handle_tx_sgl(struct hns3_enet_ring *ring, struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use]; u32 nfrag = skb_shinfo(skb)->nr_frags + 1; struct sg_table *sgt; - int i, bd_num = 0; + int bd_num = 0; dma_addr_t dma; - u32 cb_len; + u32 cb_len, i; int nents; if (skb_has_frag_list(skb)) @@ -2444,7 +2451,7 @@ static int hns3_nic_set_features(struct net_device *netdev, if ((netdev->features & NETIF_F_HW_TC) > (features & NETIF_F_HW_TC) && h->ae_algo->ops->cls_flower_active(h)) { netdev_err(netdev, - "there are offloaded TC filters active, cannot disable HW TC offload"); + "there are offloaded TC filters active, cannot disable HW TC offload\n"); return -EINVAL; } @@ -2456,7 +2463,6 @@ static int hns3_nic_set_features(struct net_device *netdev, return ret; } - netdev->features = features; return 0; } @@ -2542,7 +2548,7 @@ static void hns3_nic_get_stats64(struct net_device *netdev, struct hnae3_handle *handle = priv->ae_handle; struct rtnl_link_stats64 ring_total_stats; struct hns3_enet_ring *ring; - unsigned int idx; + int idx; if (test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) return; @@ -2761,14 +2767,14 @@ static int hns3_nic_change_mtu(struct net_device *netdev, int new_mtu) netdev_err(netdev, "failed to change MTU in hardware %d\n", ret); else - netdev->mtu = new_mtu; + WRITE_ONCE(netdev->mtu, new_mtu); return ret; } static int hns3_get_timeout_queue(struct net_device *ndev) { - int i; + unsigned int i; /* Find the stopped queue the same way the stack does */ for (i = 0; i < ndev->num_tx_queues; i++) { @@ -2849,7 +2855,7 @@ static bool hns3_get_tx_timeo_queue_info(struct net_device *ndev) struct hns3_nic_priv *priv = netdev_priv(ndev); struct hnae3_handle *h = hns3_get_handle(ndev); struct hns3_enet_ring *tx_ring; - int timeout_queue; + u32 timeout_queue; timeout_queue = hns3_get_timeout_queue(ndev); if (timeout_queue >= ndev->num_tx_queues) { @@ -3539,6 +3545,9 @@ static int hns3_alloc_ring_buffers(struct hns3_enet_ring *ring) ret = hns3_alloc_and_attach_buffer(ring, i); if (ret) goto out_buffer_fail; + + if (!(i % HNS3_RESCHED_BD_NUM)) + cond_resched(); } return 0; @@ -3816,7 +3825,7 @@ static int hns3_gro_complete(struct sk_buff *skb, u32 l234info) { __be16 type = skb->protocol; struct tcphdr *th; - int depth = 0; + u32 depth = 0; while (eth_type_vlan(type)) { struct vlan_hdr *vh; @@ -4449,7 +4458,7 @@ static void hns3_update_rx_int_coalesce(struct hns3_enet_tqp_vector *tqp_vector) dim_update_sample(tqp_vector->event_cnt, rx_group->total_packets, rx_group->total_bytes, &sample); - net_dim(&rx_group->dim, sample); + net_dim(&rx_group->dim, &sample); } static void hns3_update_tx_int_coalesce(struct hns3_enet_tqp_vector *tqp_vector) @@ -4462,7 +4471,7 @@ static void hns3_update_tx_int_coalesce(struct hns3_enet_tqp_vector *tqp_vector) dim_update_sample(tqp_vector->event_cnt, tx_group->total_packets, tx_group->total_bytes, &sample); - net_dim(&tx_group->dim, sample); + net_dim(&tx_group->dim, &sample); } static int hns3_nic_common_poll(struct napi_struct *napi, int budget) @@ -4742,7 +4751,7 @@ map_ring_fail: static void hns3_nic_init_coal_cfg(struct hns3_nic_priv *priv) { - struct hnae3_ae_dev *ae_dev = pci_get_drvdata(priv->ae_handle->pdev); + struct hnae3_ae_dev *ae_dev = hns3_get_ae_dev(priv->ae_handle); struct hns3_enet_coalesce *tx_coal = &priv->tx_coal; struct hns3_enet_coalesce *rx_coal = &priv->rx_coal; @@ -4869,6 +4878,30 @@ static void hns3_nic_dealloc_vector_data(struct hns3_nic_priv *priv) devm_kfree(&pdev->dev, priv->tqp_vector); } +static void hns3_update_tx_spare_buf_config(struct hns3_nic_priv *priv) +{ +#define HNS3_MIN_SPARE_BUF_SIZE (2 * 1024 * 1024) +#define HNS3_MAX_PACKET_SIZE (64 * 1024) + + struct iommu_domain *domain = iommu_get_domain_for_dev(priv->dev); + struct hnae3_ae_dev *ae_dev = hns3_get_ae_dev(priv->ae_handle); + struct hnae3_handle *handle = priv->ae_handle; + + if (ae_dev->dev_version < HNAE3_DEVICE_VERSION_V3) + return; + + if (!(domain && iommu_is_dma_domain(domain))) + return; + + priv->min_tx_copybreak = HNS3_MAX_PACKET_SIZE; + priv->min_tx_spare_buf_size = HNS3_MIN_SPARE_BUF_SIZE; + + if (priv->tx_copybreak < priv->min_tx_copybreak) + priv->tx_copybreak = priv->min_tx_copybreak; + if (handle->kinfo.tx_spare_buf_size < priv->min_tx_spare_buf_size) + handle->kinfo.tx_spare_buf_size = priv->min_tx_spare_buf_size; +} + static void hns3_ring_get_cfg(struct hnae3_queue *q, struct hns3_nic_priv *priv, unsigned int ring_type) { @@ -5102,6 +5135,7 @@ int hns3_init_all_ring(struct hns3_nic_priv *priv) int i, j; int ret; + hns3_update_tx_spare_buf_config(priv); for (i = 0; i < ring_num; i++) { ret = hns3_alloc_ring_memory(&priv->ring[i]); if (ret) { @@ -5111,6 +5145,7 @@ int hns3_init_all_ring(struct hns3_nic_priv *priv) } u64_stats_init(&priv->ring[i].syncp); + cond_resched(); } return 0; @@ -5220,7 +5255,7 @@ static void hns3_info_show(struct hns3_nic_priv *priv) static void hns3_set_cq_period_mode(struct hns3_nic_priv *priv, enum dim_cq_period_mode mode, bool is_tx) { - struct hnae3_ae_dev *ae_dev = pci_get_drvdata(priv->ae_handle->pdev); + struct hnae3_ae_dev *ae_dev = hns3_get_ae_dev(priv->ae_handle); struct hnae3_handle *handle = priv->ae_handle; int i; @@ -5258,7 +5293,7 @@ void hns3_cq_period_mode_init(struct hns3_nic_priv *priv, static void hns3_state_init(struct hnae3_handle *handle) { - struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); + struct hnae3_ae_dev *ae_dev = hns3_get_ae_dev(handle); struct net_device *netdev = handle->kinfo.netdev; struct hns3_nic_priv *priv = netdev_priv(netdev); @@ -5293,6 +5328,8 @@ static int hns3_client_init(struct hnae3_handle *handle) struct net_device *netdev; int ret; + ae_dev->handle = handle; + handle->ae_algo->ops->get_tqps_and_rss_info(handle, &alloc_tqps, &max_rss_size); netdev = alloc_etherdev_mq(sizeof(struct hns3_nic_priv), alloc_tqps); @@ -5305,6 +5342,8 @@ static int hns3_client_init(struct hnae3_handle *handle) priv->ae_handle = handle; priv->tx_timeout_count = 0; priv->max_non_tso_bd_num = ae_dev->dev_specs.max_non_tso_bd_num; + priv->min_tx_copybreak = 0; + priv->min_tx_spare_buf_size = 0; set_bit(HNS3_NIC_STATE_DOWN, &priv->state); handle->msg_enable = netif_msg_init(debug, DEFAULT_MSG_LEVEL); @@ -5724,6 +5763,9 @@ static int hns3_reset_notify_uninit_enet(struct hnae3_handle *handle) struct net_device *netdev = handle->kinfo.netdev; struct hns3_nic_priv *priv = netdev_priv(netdev); + if (!test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) + hns3_nic_net_stop(netdev); + if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) { netdev_warn(netdev, "already uninitialized\n"); return 0; @@ -5862,8 +5904,6 @@ int hns3_set_channels(struct net_device *netdev, void hns3_external_lb_prepare(struct net_device *ndev, bool if_running) { struct hns3_nic_priv *priv = netdev_priv(ndev); - struct hnae3_handle *h = priv->ae_handle; - int i; if (!if_running) return; @@ -5874,11 +5914,7 @@ void hns3_external_lb_prepare(struct net_device *ndev, bool if_running) netif_carrier_off(ndev); netif_tx_disable(ndev); - for (i = 0; i < priv->vector_num; i++) - hns3_vector_disable(&priv->tqp_vector[i]); - - for (i = 0; i < h->kinfo.num_tqps; i++) - hns3_tqp_disable(h->kinfo.tqp[i]); + hns3_disable_irqs_and_tqps(ndev); /* delay ring buffer clearing to hns3_reset_notify_uninit_enet * during reset process, because driver may not be able @@ -5894,7 +5930,6 @@ void hns3_external_lb_restore(struct net_device *ndev, bool if_running) { struct hns3_nic_priv *priv = netdev_priv(ndev); struct hnae3_handle *h = priv->ae_handle; - int i; if (!if_running) return; @@ -5910,11 +5945,7 @@ void hns3_external_lb_restore(struct net_device *ndev, bool if_running) clear_bit(HNS3_NIC_STATE_DOWN, &priv->state); - for (i = 0; i < priv->vector_num; i++) - hns3_vector_enable(&priv->tqp_vector[i]); - - for (i = 0; i < h->kinfo.num_tqps; i++) - hns3_tqp_enable(h->kinfo.tqp[i]); + hns3_enable_irqs_and_tqps(ndev); netif_tx_wake_all_queues(ndev); @@ -5936,7 +5967,7 @@ static const struct hns3_hw_error_info hns3_hw_err[] = { static void hns3_process_hw_error(struct hnae3_handle *handle, enum hnae3_hw_error_type type) { - int i; + u32 i; for (i = 0; i < ARRAY_SIZE(hns3_hw_err); i++) { if (hns3_hw_err[i].type == type) { @@ -5963,8 +5994,8 @@ static int __init hns3_init_module(void) { int ret; - pr_info("%s: %s - version\n", hns3_driver_name, hns3_driver_string); - pr_info("%s: %s\n", hns3_driver_name, hns3_copyright); + pr_debug("%s: %s - version\n", hns3_driver_name, hns3_driver_string); + pr_debug("%s: %s\n", hns3_driver_name, hns3_copyright); client.type = HNAE3_CLIENT_KNIC; snprintf(client.name, HNAE3_CLIENT_NAME_LENGTH, "%s", @@ -6000,9 +6031,11 @@ module_init(hns3_init_module); */ static void __exit hns3_exit_module(void) { + hnae3_acquire_unload_lock(); pci_unregister_driver(&hns3_driver); hnae3_unregister_client(&client); hns3_dbg_unregister_debugfs(); + hnae3_release_unload_lock(); } module_exit(hns3_exit_module); diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h index acd756b0c7c9..933e3527ed82 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h +++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h @@ -214,6 +214,8 @@ enum hns3_nic_state { #define HNS3_CQ_MODE_EQE 1U #define HNS3_CQ_MODE_CQE 0U +#define HNS3_RESCHED_BD_NUM 1024 + enum hns3_pkt_l2t_type { HNS3_L2_TYPE_UNICAST, HNS3_L2_TYPE_MULTICAST, @@ -594,6 +596,8 @@ struct hns3_nic_priv { struct hns3_enet_coalesce rx_coal; u32 tx_copybreak; u32 rx_copybreak; + u32 min_tx_copybreak; + u32 min_tx_spare_buf_size; }; union l3_hdr_info { @@ -619,7 +623,7 @@ struct hns3_reset_type_map { enum hnae3_reset_type rst_type; }; -static inline int ring_space(struct hns3_enet_ring *ring) +static inline u32 ring_space(struct hns3_enet_ring *ring) { /* This smp_load_acquire() pairs with smp_store_release() in * hns3_nic_reclaim_one_desc called by hns3_clean_tx_ring. @@ -690,7 +694,7 @@ static inline unsigned int hns3_page_order(struct hns3_enet_ring *ring) /* iterator for handling rings in ring group */ #define hns3_for_each_ring(pos, head) \ - for (pos = (head).ring; (pos); pos = (pos)->next) + for ((pos) = (head).ring; (pos); (pos) = (pos)->next) #define hns3_get_handle(ndev) \ (((struct hns3_nic_priv *)netdev_priv(ndev))->ae_handle) diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c b/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c index 999a0ee162a6..d5454e126c85 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c +++ b/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c @@ -3,6 +3,7 @@ #include <linux/etherdevice.h> #include <linux/string.h> +#include <linux/string_choices.h> #include <linux/phy.h> #include <linux/sfp.h> @@ -78,11 +79,14 @@ static const struct hns3_stats hns3_rxq_stats[] = { #define HNS3_NIC_LB_TEST_NO_MEM_ERR 1 #define HNS3_NIC_LB_TEST_TX_CNT_ERR 2 #define HNS3_NIC_LB_TEST_RX_CNT_ERR 3 +#define HNS3_NIC_LB_TEST_UNEXECUTED 4 + +static int hns3_get_sset_count(struct net_device *netdev, int stringset); static int hns3_lp_setup(struct net_device *ndev, enum hnae3_loop loop, bool en) { struct hnae3_handle *h = hns3_get_handle(ndev); - struct hnae3_ae_dev *ae_dev = pci_get_drvdata(h->pdev); + struct hnae3_ae_dev *ae_dev = hns3_get_ae_dev(h); int ret; if (!h->ae_algo->ops->set_loopback || @@ -167,7 +171,7 @@ static void hns3_lp_setup_skb(struct sk_buff *skb) * the purpose of mac or serdes selftest. */ handle = hns3_get_handle(ndev); - ae_dev = pci_get_drvdata(handle->pdev); + ae_dev = hns3_get_ae_dev(handle); if (ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) ethh->h_dest[5] += HNS3_NIC_LB_DST_MAC_ADDR; eth_zero_addr(ethh->h_source); @@ -418,18 +422,26 @@ static void hns3_do_external_lb(struct net_device *ndev, static void hns3_self_test(struct net_device *ndev, struct ethtool_test *eth_test, u64 *data) { + int cnt = hns3_get_sset_count(ndev, ETH_SS_TEST); struct hns3_nic_priv *priv = netdev_priv(ndev); struct hnae3_handle *h = priv->ae_handle; int st_param[HNAE3_LOOP_NONE][2]; bool if_running = netif_running(ndev); + int i; + + /* initialize the loopback test result, avoid marking an unexcuted + * loopback test as PASS. + */ + for (i = 0; i < cnt; i++) + data[i] = HNS3_NIC_LB_TEST_UNEXECUTED; if (hns3_nic_resetting(ndev)) { - netdev_err(ndev, "dev resetting!"); - return; + netdev_err(ndev, "dev resetting!\n"); + goto failure; } if (!(eth_test->flags & ETH_TEST_FL_OFFLINE)) - return; + goto failure; if (netif_msg_ifdown(h)) netdev_info(ndev, "self test start\n"); @@ -451,6 +463,10 @@ static void hns3_self_test(struct net_device *ndev, if (netif_msg_ifdown(h)) netdev_info(ndev, "self test end\n"); + return; + +failure: + eth_test->flags |= ETH_TEST_FL_FAILED; } static void hns3_update_limit_promisc_mode(struct net_device *netdev, @@ -473,7 +489,7 @@ static const struct hns3_pflag_desc hns3_priv_flags[HNAE3_PFLAG_MAX] = { static int hns3_get_sset_count(struct net_device *netdev, int stringset) { struct hnae3_handle *h = hns3_get_handle(netdev); - const struct hnae3_ae_ops *ops = h->ae_algo->ops; + const struct hnae3_ae_ops *ops = hns3_get_ops(h); if (!ops->get_sset_count) return -EOPNOTSUPP; @@ -494,73 +510,53 @@ static int hns3_get_sset_count(struct net_device *netdev, int stringset) } } -static void *hns3_update_strings(u8 *data, const struct hns3_stats *stats, - u32 stat_count, u32 num_tqps, const char *prefix) +static void hns3_update_strings(u8 **data, const struct hns3_stats *stats, + u32 stat_count, u32 num_tqps, + const char *prefix) { -#define MAX_PREFIX_SIZE (6 + 4) - u32 size_left; u32 i, j; - u32 n1; - for (i = 0; i < num_tqps; i++) { - for (j = 0; j < stat_count; j++) { - data[ETH_GSTRING_LEN - 1] = '\0'; - - /* first, prepend the prefix string */ - n1 = scnprintf(data, MAX_PREFIX_SIZE, "%s%u_", - prefix, i); - size_left = (ETH_GSTRING_LEN - 1) - n1; - - /* now, concatenate the stats string to it */ - strncat(data, stats[j].stats_string, size_left); - data += ETH_GSTRING_LEN; - } - } - - return data; + for (i = 0; i < num_tqps; i++) + for (j = 0; j < stat_count; j++) + ethtool_sprintf(data, "%s%u_%s", prefix, i, + stats[j].stats_string); } -static u8 *hns3_get_strings_tqps(struct hnae3_handle *handle, u8 *data) +static void hns3_get_strings_tqps(struct hnae3_handle *handle, u8 **data) { struct hnae3_knic_private_info *kinfo = &handle->kinfo; const char tx_prefix[] = "txq"; const char rx_prefix[] = "rxq"; /* get strings for Tx */ - data = hns3_update_strings(data, hns3_txq_stats, HNS3_TXQ_STATS_COUNT, - kinfo->num_tqps, tx_prefix); + hns3_update_strings(data, hns3_txq_stats, HNS3_TXQ_STATS_COUNT, + kinfo->num_tqps, tx_prefix); /* get strings for Rx */ - data = hns3_update_strings(data, hns3_rxq_stats, HNS3_RXQ_STATS_COUNT, - kinfo->num_tqps, rx_prefix); - - return data; + hns3_update_strings(data, hns3_rxq_stats, HNS3_RXQ_STATS_COUNT, + kinfo->num_tqps, rx_prefix); } static void hns3_get_strings(struct net_device *netdev, u32 stringset, u8 *data) { struct hnae3_handle *h = hns3_get_handle(netdev); - const struct hnae3_ae_ops *ops = h->ae_algo->ops; - char *buff = (char *)data; - int i; + const struct hnae3_ae_ops *ops = hns3_get_ops(h); + u32 i; if (!ops->get_strings) return; switch (stringset) { case ETH_SS_STATS: - buff = hns3_get_strings_tqps(h, buff); - ops->get_strings(h, stringset, (u8 *)buff); + hns3_get_strings_tqps(h, &data); + ops->get_strings(h, stringset, &data); break; case ETH_SS_TEST: - ops->get_strings(h, stringset, data); + ops->get_strings(h, stringset, &data); break; case ETH_SS_PRIV_FLAGS: - for (i = 0; i < HNS3_PRIV_FLAGS_LEN; i++) { - snprintf(buff, ETH_GSTRING_LEN, "%s", - hns3_priv_flags[i].name); - buff += ETH_GSTRING_LEN; - } + for (i = 0; i < HNS3_PRIV_FLAGS_LEN; i++) + ethtool_puts(&data, hns3_priv_flags[i].name); break; default: break; @@ -573,7 +569,7 @@ static u64 *hns3_get_stats_tqps(struct hnae3_handle *handle, u64 *data) struct hns3_nic_priv *nic_priv = handle->priv; struct hns3_enet_ring *ring; u8 *stat; - int i, j; + u32 i, j; /* get stats for Tx */ for (i = 0; i < kinfo->num_tqps; i++) { @@ -696,7 +692,7 @@ static void hns3_get_pauseparam(struct net_device *netdev, struct ethtool_pauseparam *param) { struct hnae3_handle *h = hns3_get_handle(netdev); - struct hnae3_ae_dev *ae_dev = pci_get_drvdata(h->pdev); + struct hnae3_ae_dev *ae_dev = hns3_get_ae_dev(h); if (!test_bit(HNAE3_DEV_SUPPORT_PAUSE_B, ae_dev->caps)) return; @@ -710,7 +706,7 @@ static int hns3_set_pauseparam(struct net_device *netdev, struct ethtool_pauseparam *param) { struct hnae3_handle *h = hns3_get_handle(netdev); - struct hnae3_ae_dev *ae_dev = pci_get_drvdata(h->pdev); + struct hnae3_ae_dev *ae_dev = hns3_get_ae_dev(h); if (!test_bit(HNAE3_DEV_SUPPORT_PAUSE_B, ae_dev->caps)) return -EOPNOTSUPP; @@ -729,7 +725,7 @@ static int hns3_set_pauseparam(struct net_device *netdev, static void hns3_get_ksettings(struct hnae3_handle *h, struct ethtool_link_ksettings *cmd) { - const struct hnae3_ae_ops *ops = h->ae_algo->ops; + const struct hnae3_ae_ops *ops = hns3_get_ops(h); /* 1.auto_neg & speed & duplex from cmd */ if (ops->get_ksettings_an_result) @@ -755,7 +751,7 @@ static int hns3_get_link_ksettings(struct net_device *netdev, struct ethtool_link_ksettings *cmd) { struct hnae3_handle *h = hns3_get_handle(netdev); - struct hnae3_ae_dev *ae_dev = pci_get_drvdata(h->pdev); + struct hnae3_ae_dev *ae_dev = hns3_get_ae_dev(h); const struct hnae3_ae_ops *ops; u8 module_type; u8 media_type; @@ -798,7 +794,7 @@ static int hns3_get_link_ksettings(struct net_device *netdev, break; default: - netdev_warn(netdev, "Unknown media type"); + netdev_warn(netdev, "Unknown media type\n"); return 0; } @@ -818,7 +814,7 @@ static int hns3_check_ksettings_param(const struct net_device *netdev, const struct ethtool_link_ksettings *cmd) { struct hnae3_handle *handle = hns3_get_handle(netdev); - const struct hnae3_ae_ops *ops = handle->ae_algo->ops; + const struct hnae3_ae_ops *ops = hns3_get_ops(handle); u8 module_type = HNAE3_MODULE_TYPE_UNKNOWN; u8 media_type = HNAE3_MEDIA_TYPE_UNKNOWN; u32 lane_num; @@ -846,7 +842,7 @@ static int hns3_check_ksettings_param(const struct net_device *netdev, if (cmd->base.duplex == DUPLEX_HALF && media_type != HNAE3_MEDIA_TYPE_COPPER) { netdev_err(netdev, - "only copper port supports half duplex!"); + "only copper port supports half duplex!\n"); return -EINVAL; } @@ -865,8 +861,8 @@ static int hns3_set_link_ksettings(struct net_device *netdev, const struct ethtool_link_ksettings *cmd) { struct hnae3_handle *handle = hns3_get_handle(netdev); - struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); - const struct hnae3_ae_ops *ops = handle->ae_algo->ops; + struct hnae3_ae_dev *ae_dev = hns3_get_ae_dev(handle); + const struct hnae3_ae_ops *ops = hns3_get_ops(handle); int ret; /* Chip don't support this mode. */ @@ -936,7 +932,7 @@ static u32 hns3_get_rss_key_size(struct net_device *netdev) static u32 hns3_get_rss_indir_size(struct net_device *netdev) { struct hnae3_handle *h = hns3_get_handle(netdev); - struct hnae3_ae_dev *ae_dev = pci_get_drvdata(h->pdev); + struct hnae3_ae_dev *ae_dev = hns3_get_ae_dev(h); return ae_dev->dev_specs.rss_ind_tbl_size; } @@ -958,7 +954,7 @@ static int hns3_set_rss(struct net_device *netdev, struct netlink_ext_ack *extack) { struct hnae3_handle *h = hns3_get_handle(netdev); - struct hnae3_ae_dev *ae_dev = pci_get_drvdata(h->pdev); + struct hnae3_ae_dev *ae_dev = hns3_get_ae_dev(h); if (!h->ae_algo->ops->set_rss) return -EOPNOTSUPP; @@ -982,6 +978,16 @@ static int hns3_set_rss(struct net_device *netdev, rxfh->hfunc); } +static int hns3_get_rxfh_fields(struct net_device *netdev, + struct ethtool_rxfh_fields *cmd) +{ + struct hnae3_handle *h = hns3_get_handle(netdev); + + if (h->ae_algo->ops->get_rss_tuple) + return h->ae_algo->ops->get_rss_tuple(h, cmd); + return -EOPNOTSUPP; +} + static int hns3_get_rxnfc(struct net_device *netdev, struct ethtool_rxnfc *cmd, u32 *rule_locs) @@ -992,10 +998,6 @@ static int hns3_get_rxnfc(struct net_device *netdev, case ETHTOOL_GRXRINGS: cmd->data = h->kinfo.num_tqps; return 0; - case ETHTOOL_GRXFH: - if (h->ae_algo->ops->get_rss_tuple) - return h->ae_algo->ops->get_rss_tuple(h, cmd); - return -EOPNOTSUPP; case ETHTOOL_GRXCLSRLCNT: if (h->ae_algo->ops->get_fd_rule_cnt) return h->ae_algo->ops->get_fd_rule_cnt(h, cmd); @@ -1028,8 +1030,8 @@ static int hns3_set_reset(struct net_device *netdev, u32 *flags) { enum hnae3_reset_type rst_type = HNAE3_NONE_RESET; struct hnae3_handle *h = hns3_get_handle(netdev); - struct hnae3_ae_dev *ae_dev = pci_get_drvdata(h->pdev); - const struct hnae3_ae_ops *ops = h->ae_algo->ops; + struct hnae3_ae_dev *ae_dev = hns3_get_ae_dev(h); + const struct hnae3_ae_ops *ops = hns3_get_ops(h); const struct hns3_reset_type_map *rst_type_map; enum ethtool_reset_flags rst_flags; u32 i, size; @@ -1193,7 +1195,7 @@ static int hns3_set_tx_push(struct net_device *netdev, u32 tx_push) { struct hns3_nic_priv *priv = netdev_priv(netdev); struct hnae3_handle *h = hns3_get_handle(netdev); - struct hnae3_ae_dev *ae_dev = pci_get_drvdata(h->pdev); + struct hnae3_ae_dev *ae_dev = hns3_get_ae_dev(h); u32 old_state = test_bit(HNS3_NIC_STATE_TX_PUSH_ENABLE, &priv->state); if (!test_bit(HNAE3_DEV_SUPPORT_TX_PUSH_B, ae_dev->caps) && tx_push) @@ -1203,7 +1205,7 @@ static int hns3_set_tx_push(struct net_device *netdev, u32 tx_push) return 0; netdev_dbg(netdev, "Changing tx push from %s to %s\n", - old_state ? "on" : "off", tx_push ? "on" : "off"); + str_on_off(old_state), str_on_off(tx_push)); if (tx_push) set_bit(HNS3_NIC_STATE_TX_PUSH_ENABLE, &priv->state); @@ -1279,15 +1281,22 @@ static int hns3_set_ringparam(struct net_device *ndev, return ret; } +static int hns3_set_rxfh_fields(struct net_device *netdev, + const struct ethtool_rxfh_fields *cmd, + struct netlink_ext_ack *extack) +{ + struct hnae3_handle *h = hns3_get_handle(netdev); + + if (h->ae_algo->ops->set_rss_tuple) + return h->ae_algo->ops->set_rss_tuple(h, cmd); + return -EOPNOTSUPP; +} + static int hns3_set_rxnfc(struct net_device *netdev, struct ethtool_rxnfc *cmd) { struct hnae3_handle *h = hns3_get_handle(netdev); switch (cmd->cmd) { - case ETHTOOL_SRXFH: - if (h->ae_algo->ops->set_rss_tuple) - return h->ae_algo->ops->set_rss_tuple(h, cmd); - return -EOPNOTSUPP; case ETHTOOL_SRXCLSRLINS: if (h->ae_algo->ops->add_fd_entry) return h->ae_algo->ops->add_fd_entry(h, cmd); @@ -1304,7 +1313,7 @@ static int hns3_set_rxnfc(struct net_device *netdev, struct ethtool_rxnfc *cmd) static int hns3_nway_reset(struct net_device *netdev) { struct hnae3_handle *handle = hns3_get_handle(netdev); - const struct hnae3_ae_ops *ops = handle->ae_algo->ops; + const struct hnae3_ae_ops *ops = hns3_get_ops(handle); struct phy_device *phy = netdev->phydev; int autoneg; @@ -1312,7 +1321,7 @@ static int hns3_nway_reset(struct net_device *netdev) return 0; if (hns3_nic_resetting(netdev)) { - netdev_err(netdev, "dev resetting!"); + netdev_err(netdev, "dev resetting!\n"); return -EBUSY; } @@ -1381,7 +1390,7 @@ static int hns3_check_gl_coalesce_para(struct net_device *netdev, struct ethtool_coalesce *cmd) { struct hnae3_handle *handle = hns3_get_handle(netdev); - struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); + struct hnae3_ae_dev *ae_dev = hns3_get_ae_dev(handle); u32 rx_gl, tx_gl; if (cmd->rx_coalesce_usecs > ae_dev->dev_specs.max_int_gl) { @@ -1453,7 +1462,7 @@ static int hns3_check_ql_coalesce_param(struct net_device *netdev, struct ethtool_coalesce *cmd) { struct hnae3_handle *handle = hns3_get_handle(netdev); - struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); + struct hnae3_ae_dev *ae_dev = hns3_get_ae_dev(handle); if ((cmd->tx_max_coalesced_frames || cmd->rx_max_coalesced_frames) && !ae_dev->dev_specs.int_ql_max) { @@ -1477,7 +1486,7 @@ hns3_check_cqe_coalesce_param(struct net_device *netdev, struct kernel_ethtool_coalesce *kernel_coal) { struct hnae3_handle *handle = hns3_get_handle(netdev); - struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); + struct hnae3_ae_dev *ae_dev = hns3_get_ae_dev(handle); if ((kernel_coal->use_cqe_mode_tx || kernel_coal->use_cqe_mode_rx) && !hnae3_ae_dev_cq_supported(ae_dev)) { @@ -1653,8 +1662,8 @@ static void hns3_get_fec_stats(struct net_device *netdev, struct ethtool_fec_stats *fec_stats) { struct hnae3_handle *handle = hns3_get_handle(netdev); - struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); - const struct hnae3_ae_ops *ops = handle->ae_algo->ops; + struct hnae3_ae_dev *ae_dev = hns3_get_ae_dev(handle); + const struct hnae3_ae_ops *ops = hns3_get_ops(handle); if (!hnae3_ae_dev_fec_stats_supported(ae_dev) || !ops->get_fec_stats) return; @@ -1704,8 +1713,8 @@ static int hns3_get_fecparam(struct net_device *netdev, struct ethtool_fecparam *fec) { struct hnae3_handle *handle = hns3_get_handle(netdev); - struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); - const struct hnae3_ae_ops *ops = handle->ae_algo->ops; + struct hnae3_ae_dev *ae_dev = hns3_get_ae_dev(handle); + const struct hnae3_ae_ops *ops = hns3_get_ops(handle); u8 fec_ability; u8 fec_mode; @@ -1729,8 +1738,8 @@ static int hns3_set_fecparam(struct net_device *netdev, struct ethtool_fecparam *fec) { struct hnae3_handle *handle = hns3_get_handle(netdev); - struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); - const struct hnae3_ae_ops *ops = handle->ae_algo->ops; + struct hnae3_ae_dev *ae_dev = hns3_get_ae_dev(handle); + const struct hnae3_ae_ops *ops = hns3_get_ops(handle); u32 fec_mode; if (!test_bit(HNAE3_DEV_SUPPORT_FEC_B, ae_dev->caps)) @@ -1751,8 +1760,8 @@ static int hns3_get_module_info(struct net_device *netdev, #define HNS3_SFF_8636_V1_3 0x03 struct hnae3_handle *handle = hns3_get_handle(netdev); - struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); - const struct hnae3_ae_ops *ops = handle->ae_algo->ops; + struct hnae3_ae_dev *ae_dev = hns3_get_ae_dev(handle); + const struct hnae3_ae_ops *ops = hns3_get_ops(handle); struct hns3_sfp_type sfp_type; int ret; @@ -1801,8 +1810,8 @@ static int hns3_get_module_eeprom(struct net_device *netdev, struct ethtool_eeprom *ee, u8 *data) { struct hnae3_handle *handle = hns3_get_handle(netdev); - struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); - const struct hnae3_ae_ops *ops = handle->ae_algo->ops; + struct hnae3_ae_dev *ae_dev = hns3_get_ae_dev(handle); + const struct hnae3_ae_ops *ops = hns3_get_ops(handle); if (ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2 || !ops->get_module_eeprom) @@ -1928,7 +1937,7 @@ static int hns3_set_tunable(struct net_device *netdev, int i, ret = 0; if (hns3_nic_resetting(netdev) || !priv->ring) { - netdev_err(netdev, "failed to set tunable value, dev resetting!"); + netdev_err(netdev, "failed to set tunable value, dev resetting!\n"); return -EBUSY; } @@ -1994,7 +2003,7 @@ static int hns3_set_tunable(struct net_device *netdev, ETHTOOL_RING_USE_TX_PUSH) static int hns3_get_ts_info(struct net_device *netdev, - struct ethtool_ts_info *info) + struct kernel_ethtool_ts_info *info) { struct hnae3_handle *handle = hns3_get_handle(netdev); @@ -2109,6 +2118,8 @@ static const struct ethtool_ops hns3vf_ethtool_ops = { .get_rxfh_indir_size = hns3_get_rss_indir_size, .get_rxfh = hns3_get_rss, .set_rxfh = hns3_set_rss, + .get_rxfh_fields = hns3_get_rxfh_fields, + .set_rxfh_fields = hns3_set_rxfh_fields, .get_link_ksettings = hns3_get_link_ksettings, .get_channels = hns3_get_channels, .set_channels = hns3_set_channels, @@ -2146,6 +2157,8 @@ static const struct ethtool_ops hns3_ethtool_ops = { .get_rxfh_indir_size = hns3_get_rss_indir_size, .get_rxfh = hns3_get_rss, .set_rxfh = hns3_set_rss, + .get_rxfh_fields = hns3_get_rxfh_fields, + .set_rxfh_fields = hns3_set_rxfh_fields, .get_link_ksettings = hns3_get_link_ksettings, .set_link_ksettings = hns3_set_link_ksettings, .nway_reset = hns3_nway_reset, diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_trace.h b/drivers/net/ethernet/hisilicon/hns3/hns3_trace.h index b8a1ecb4b8fb..3362b8d14d4f 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3_trace.h +++ b/drivers/net/ethernet/hisilicon/hns3/hns3_trace.h @@ -84,7 +84,7 @@ TRACE_EVENT(hns3_tx_desc, __entry->desc_dma = ring->desc_dma_addr, memcpy(__entry->desc, &ring->desc[cur_ntu], sizeof(struct hns3_desc)); - __assign_str(devname, ring->tqp->handle->kinfo.netdev->name); + __assign_str(devname); ), TP_printk( @@ -117,7 +117,7 @@ TRACE_EVENT(hns3_rx_desc, __entry->buf_dma = ring->desc_cb[ring->next_to_clean].dma; memcpy(__entry->desc, &ring->desc[ring->next_to_clean], sizeof(struct hns3_desc)); - __assign_str(devname, ring->tqp->handle->kinfo.netdev->name); + __assign_str(devname); ), TP_printk( diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c index 9ec471ced3d6..b76d25074e99 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c @@ -3,6 +3,7 @@ #include <linux/device.h> #include <linux/sched/clock.h> +#include <linux/string_choices.h> #include "hclge_debugfs.h" #include "hclge_err.h" @@ -11,13 +12,655 @@ #include "hclge_tm.h" #include "hnae3.h" -static const char * const state_str[] = { "off", "on" }; +#define hclge_seq_file_to_hdev(s) \ + (((struct hnae3_ae_dev *)hnae3_seq_file_to_ae_dev(s))->priv) + static const char * const hclge_mac_state_str[] = { "TO_ADD", "TO_DEL", "ACTIVE" }; static const char * const tc_map_mode_str[] = { "PRIO", "DSCP" }; +static const struct hclge_dbg_dfx_message hclge_dbg_bios_common_reg[] = { + {false, "Reserved"}, + {true, "BP_CPU_STATE"}, + {true, "DFX_MSIX_INFO_NIC_0"}, + {true, "DFX_MSIX_INFO_NIC_1"}, + {true, "DFX_MSIX_INFO_NIC_2"}, + {true, "DFX_MSIX_INFO_NIC_3"}, + + {true, "DFX_MSIX_INFO_ROC_0"}, + {true, "DFX_MSIX_INFO_ROC_1"}, + {true, "DFX_MSIX_INFO_ROC_2"}, + {true, "DFX_MSIX_INFO_ROC_3"}, + {false, "Reserved"}, + {false, "Reserved"}, +}; + +static const struct hclge_dbg_dfx_message hclge_dbg_ssu_reg_0[] = { + {false, "Reserved"}, + {true, "SSU_ETS_PORT_STATUS"}, + {true, "SSU_ETS_TCG_STATUS"}, + {false, "Reserved"}, + {false, "Reserved"}, + {true, "SSU_BP_STATUS_0"}, + + {true, "SSU_BP_STATUS_1"}, + {true, "SSU_BP_STATUS_2"}, + {true, "SSU_BP_STATUS_3"}, + {true, "SSU_BP_STATUS_4"}, + {true, "SSU_BP_STATUS_5"}, + {true, "SSU_MAC_TX_PFC_IND"}, + + {true, "MAC_SSU_RX_PFC_IND"}, + {true, "BTMP_AGEING_ST_B0"}, + {true, "BTMP_AGEING_ST_B1"}, + {true, "BTMP_AGEING_ST_B2"}, + {false, "Reserved"}, + {false, "Reserved"}, + + {true, "FULL_DROP_NUM"}, + {true, "PART_DROP_NUM"}, + {true, "PPP_KEY_DROP_NUM"}, + {true, "PPP_RLT_DROP_NUM"}, + {true, "LO_PRI_UNICAST_RLT_DROP_NUM"}, + {true, "HI_PRI_MULTICAST_RLT_DROP_NUM"}, + + {true, "LO_PRI_MULTICAST_RLT_DROP_NUM"}, + {true, "NCSI_PACKET_CURR_BUFFER_CNT"}, + {true, "BTMP_AGEING_RLS_CNT_BANK0"}, + {true, "BTMP_AGEING_RLS_CNT_BANK1"}, + {true, "BTMP_AGEING_RLS_CNT_BANK2"}, + {true, "SSU_MB_RD_RLT_DROP_CNT"}, + + {true, "SSU_PPP_MAC_KEY_NUM_L"}, + {true, "SSU_PPP_MAC_KEY_NUM_H"}, + {true, "SSU_PPP_HOST_KEY_NUM_L"}, + {true, "SSU_PPP_HOST_KEY_NUM_H"}, + {true, "PPP_SSU_MAC_RLT_NUM_L"}, + {true, "PPP_SSU_MAC_RLT_NUM_H"}, + + {true, "PPP_SSU_HOST_RLT_NUM_L"}, + {true, "PPP_SSU_HOST_RLT_NUM_H"}, + {true, "NCSI_RX_PACKET_IN_CNT_L"}, + {true, "NCSI_RX_PACKET_IN_CNT_H"}, + {true, "NCSI_TX_PACKET_OUT_CNT_L"}, + {true, "NCSI_TX_PACKET_OUT_CNT_H"}, + + {true, "SSU_KEY_DROP_NUM"}, + {true, "MB_UNCOPY_NUM"}, + {true, "RX_OQ_DROP_PKT_CNT"}, + {true, "TX_OQ_DROP_PKT_CNT"}, + {true, "BANK_UNBALANCE_DROP_CNT"}, + {true, "BANK_UNBALANCE_RX_DROP_CNT"}, + + {true, "NIC_L2_ERR_DROP_PKT_CNT"}, + {true, "ROC_L2_ERR_DROP_PKT_CNT"}, + {true, "NIC_L2_ERR_DROP_PKT_CNT_RX"}, + {true, "ROC_L2_ERR_DROP_PKT_CNT_RX"}, + {true, "RX_OQ_GLB_DROP_PKT_CNT"}, + {false, "Reserved"}, + + {true, "LO_PRI_UNICAST_CUR_CNT"}, + {true, "HI_PRI_MULTICAST_CUR_CNT"}, + {true, "LO_PRI_MULTICAST_CUR_CNT"}, + {false, "Reserved"}, + {false, "Reserved"}, + {false, "Reserved"}, +}; + +static const struct hclge_dbg_dfx_message hclge_dbg_ssu_reg_1[] = { + {true, "prt_id"}, + {true, "PACKET_TC_CURR_BUFFER_CNT_0"}, + {true, "PACKET_TC_CURR_BUFFER_CNT_1"}, + {true, "PACKET_TC_CURR_BUFFER_CNT_2"}, + {true, "PACKET_TC_CURR_BUFFER_CNT_3"}, + {true, "PACKET_TC_CURR_BUFFER_CNT_4"}, + + {true, "PACKET_TC_CURR_BUFFER_CNT_5"}, + {true, "PACKET_TC_CURR_BUFFER_CNT_6"}, + {true, "PACKET_TC_CURR_BUFFER_CNT_7"}, + {true, "PACKET_CURR_BUFFER_CNT"}, + {false, "Reserved"}, + {false, "Reserved"}, + + {true, "RX_PACKET_IN_CNT_L"}, + {true, "RX_PACKET_IN_CNT_H"}, + {true, "RX_PACKET_OUT_CNT_L"}, + {true, "RX_PACKET_OUT_CNT_H"}, + {true, "TX_PACKET_IN_CNT_L"}, + {true, "TX_PACKET_IN_CNT_H"}, + + {true, "TX_PACKET_OUT_CNT_L"}, + {true, "TX_PACKET_OUT_CNT_H"}, + {true, "ROC_RX_PACKET_IN_CNT_L"}, + {true, "ROC_RX_PACKET_IN_CNT_H"}, + {true, "ROC_TX_PACKET_OUT_CNT_L"}, + {true, "ROC_TX_PACKET_OUT_CNT_H"}, + + {true, "RX_PACKET_TC_IN_CNT_0_L"}, + {true, "RX_PACKET_TC_IN_CNT_0_H"}, + {true, "RX_PACKET_TC_IN_CNT_1_L"}, + {true, "RX_PACKET_TC_IN_CNT_1_H"}, + {true, "RX_PACKET_TC_IN_CNT_2_L"}, + {true, "RX_PACKET_TC_IN_CNT_2_H"}, + + {true, "RX_PACKET_TC_IN_CNT_3_L"}, + {true, "RX_PACKET_TC_IN_CNT_3_H"}, + {true, "RX_PACKET_TC_IN_CNT_4_L"}, + {true, "RX_PACKET_TC_IN_CNT_4_H"}, + {true, "RX_PACKET_TC_IN_CNT_5_L"}, + {true, "RX_PACKET_TC_IN_CNT_5_H"}, + + {true, "RX_PACKET_TC_IN_CNT_6_L"}, + {true, "RX_PACKET_TC_IN_CNT_6_H"}, + {true, "RX_PACKET_TC_IN_CNT_7_L"}, + {true, "RX_PACKET_TC_IN_CNT_7_H"}, + {true, "RX_PACKET_TC_OUT_CNT_0_L"}, + {true, "RX_PACKET_TC_OUT_CNT_0_H"}, + + {true, "RX_PACKET_TC_OUT_CNT_1_L"}, + {true, "RX_PACKET_TC_OUT_CNT_1_H"}, + {true, "RX_PACKET_TC_OUT_CNT_2_L"}, + {true, "RX_PACKET_TC_OUT_CNT_2_H"}, + {true, "RX_PACKET_TC_OUT_CNT_3_L"}, + {true, "RX_PACKET_TC_OUT_CNT_3_H"}, + + {true, "RX_PACKET_TC_OUT_CNT_4_L"}, + {true, "RX_PACKET_TC_OUT_CNT_4_H"}, + {true, "RX_PACKET_TC_OUT_CNT_5_L"}, + {true, "RX_PACKET_TC_OUT_CNT_5_H"}, + {true, "RX_PACKET_TC_OUT_CNT_6_L"}, + {true, "RX_PACKET_TC_OUT_CNT_6_H"}, + + {true, "RX_PACKET_TC_OUT_CNT_7_L"}, + {true, "RX_PACKET_TC_OUT_CNT_7_H"}, + {true, "TX_PACKET_TC_IN_CNT_0_L"}, + {true, "TX_PACKET_TC_IN_CNT_0_H"}, + {true, "TX_PACKET_TC_IN_CNT_1_L"}, + {true, "TX_PACKET_TC_IN_CNT_1_H"}, + + {true, "TX_PACKET_TC_IN_CNT_2_L"}, + {true, "TX_PACKET_TC_IN_CNT_2_H"}, + {true, "TX_PACKET_TC_IN_CNT_3_L"}, + {true, "TX_PACKET_TC_IN_CNT_3_H"}, + {true, "TX_PACKET_TC_IN_CNT_4_L"}, + {true, "TX_PACKET_TC_IN_CNT_4_H"}, + + {true, "TX_PACKET_TC_IN_CNT_5_L"}, + {true, "TX_PACKET_TC_IN_CNT_5_H"}, + {true, "TX_PACKET_TC_IN_CNT_6_L"}, + {true, "TX_PACKET_TC_IN_CNT_6_H"}, + {true, "TX_PACKET_TC_IN_CNT_7_L"}, + {true, "TX_PACKET_TC_IN_CNT_7_H"}, + + {true, "TX_PACKET_TC_OUT_CNT_0_L"}, + {true, "TX_PACKET_TC_OUT_CNT_0_H"}, + {true, "TX_PACKET_TC_OUT_CNT_1_L"}, + {true, "TX_PACKET_TC_OUT_CNT_1_H"}, + {true, "TX_PACKET_TC_OUT_CNT_2_L"}, + {true, "TX_PACKET_TC_OUT_CNT_2_H"}, + + {true, "TX_PACKET_TC_OUT_CNT_3_L"}, + {true, "TX_PACKET_TC_OUT_CNT_3_H"}, + {true, "TX_PACKET_TC_OUT_CNT_4_L"}, + {true, "TX_PACKET_TC_OUT_CNT_4_H"}, + {true, "TX_PACKET_TC_OUT_CNT_5_L"}, + {true, "TX_PACKET_TC_OUT_CNT_5_H"}, + + {true, "TX_PACKET_TC_OUT_CNT_6_L"}, + {true, "TX_PACKET_TC_OUT_CNT_6_H"}, + {true, "TX_PACKET_TC_OUT_CNT_7_L"}, + {true, "TX_PACKET_TC_OUT_CNT_7_H"}, + {false, "Reserved"}, + {false, "Reserved"}, +}; + +static const struct hclge_dbg_dfx_message hclge_dbg_ssu_reg_2[] = { + {true, "OQ_INDEX"}, + {true, "QUEUE_CNT"}, + {false, "Reserved"}, + {false, "Reserved"}, + {false, "Reserved"}, + {false, "Reserved"}, +}; + +static const struct hclge_dbg_dfx_message hclge_dbg_igu_egu_reg[] = { + {true, "prt_id"}, + {true, "IGU_RX_ERR_PKT"}, + {true, "IGU_RX_NO_SOF_PKT"}, + {true, "EGU_TX_1588_SHORT_PKT"}, + {true, "EGU_TX_1588_PKT"}, + {true, "EGU_TX_ERR_PKT"}, + + {true, "IGU_RX_OUT_L2_PKT"}, + {true, "IGU_RX_OUT_L3_PKT"}, + {true, "IGU_RX_OUT_L4_PKT"}, + {true, "IGU_RX_IN_L2_PKT"}, + {true, "IGU_RX_IN_L3_PKT"}, + {true, "IGU_RX_IN_L4_PKT"}, + + {true, "IGU_RX_EL3E_PKT"}, + {true, "IGU_RX_EL4E_PKT"}, + {true, "IGU_RX_L3E_PKT"}, + {true, "IGU_RX_L4E_PKT"}, + {true, "IGU_RX_ROCEE_PKT"}, + {true, "IGU_RX_OUT_UDP0_PKT"}, + + {true, "IGU_RX_IN_UDP0_PKT"}, + {true, "IGU_MC_CAR_DROP_PKT_L"}, + {true, "IGU_MC_CAR_DROP_PKT_H"}, + {true, "IGU_BC_CAR_DROP_PKT_L"}, + {true, "IGU_BC_CAR_DROP_PKT_H"}, + {false, "Reserved"}, + + {true, "IGU_RX_OVERSIZE_PKT_L"}, + {true, "IGU_RX_OVERSIZE_PKT_H"}, + {true, "IGU_RX_UNDERSIZE_PKT_L"}, + {true, "IGU_RX_UNDERSIZE_PKT_H"}, + {true, "IGU_RX_OUT_ALL_PKT_L"}, + {true, "IGU_RX_OUT_ALL_PKT_H"}, + + {true, "IGU_TX_OUT_ALL_PKT_L"}, + {true, "IGU_TX_OUT_ALL_PKT_H"}, + {true, "IGU_RX_UNI_PKT_L"}, + {true, "IGU_RX_UNI_PKT_H"}, + {true, "IGU_RX_MULTI_PKT_L"}, + {true, "IGU_RX_MULTI_PKT_H"}, + + {true, "IGU_RX_BROAD_PKT_L"}, + {true, "IGU_RX_BROAD_PKT_H"}, + {true, "EGU_TX_OUT_ALL_PKT_L"}, + {true, "EGU_TX_OUT_ALL_PKT_H"}, + {true, "EGU_TX_UNI_PKT_L"}, + {true, "EGU_TX_UNI_PKT_H"}, + + {true, "EGU_TX_MULTI_PKT_L"}, + {true, "EGU_TX_MULTI_PKT_H"}, + {true, "EGU_TX_BROAD_PKT_L"}, + {true, "EGU_TX_BROAD_PKT_H"}, + {true, "IGU_TX_KEY_NUM_L"}, + {true, "IGU_TX_KEY_NUM_H"}, + + {true, "IGU_RX_NON_TUN_PKT_L"}, + {true, "IGU_RX_NON_TUN_PKT_H"}, + {true, "IGU_RX_TUN_PKT_L"}, + {true, "IGU_RX_TUN_PKT_H"}, + {false, "Reserved"}, + {false, "Reserved"}, +}; + +static const struct hclge_dbg_dfx_message hclge_dbg_rpu_reg_0[] = { + {true, "tc_queue_num"}, + {true, "FSM_DFX_ST0"}, + {true, "FSM_DFX_ST1"}, + {true, "RPU_RX_PKT_DROP_CNT"}, + {true, "BUF_WAIT_TIMEOUT"}, + {true, "BUF_WAIT_TIMEOUT_QID"}, +}; + +static const struct hclge_dbg_dfx_message hclge_dbg_rpu_reg_1[] = { + {false, "Reserved"}, + {true, "FIFO_DFX_ST0"}, + {true, "FIFO_DFX_ST1"}, + {true, "FIFO_DFX_ST2"}, + {true, "FIFO_DFX_ST3"}, + {true, "FIFO_DFX_ST4"}, + + {true, "FIFO_DFX_ST5"}, + {false, "Reserved"}, + {false, "Reserved"}, + {false, "Reserved"}, + {false, "Reserved"}, + {false, "Reserved"}, +}; + +static const struct hclge_dbg_dfx_message hclge_dbg_ncsi_reg[] = { + {false, "Reserved"}, + {true, "NCSI_EGU_TX_FIFO_STS"}, + {true, "NCSI_PAUSE_STATUS"}, + {true, "NCSI_RX_CTRL_DMAC_ERR_CNT"}, + {true, "NCSI_RX_CTRL_SMAC_ERR_CNT"}, + {true, "NCSI_RX_CTRL_CKS_ERR_CNT"}, + + {true, "NCSI_RX_CTRL_PKT_CNT"}, + {true, "NCSI_RX_PT_DMAC_ERR_CNT"}, + {true, "NCSI_RX_PT_SMAC_ERR_CNT"}, + {true, "NCSI_RX_PT_PKT_CNT"}, + {true, "NCSI_RX_FCS_ERR_CNT"}, + {true, "NCSI_TX_CTRL_DMAC_ERR_CNT"}, + + {true, "NCSI_TX_CTRL_SMAC_ERR_CNT"}, + {true, "NCSI_TX_CTRL_PKT_CNT"}, + {true, "NCSI_TX_PT_DMAC_ERR_CNT"}, + {true, "NCSI_TX_PT_SMAC_ERR_CNT"}, + {true, "NCSI_TX_PT_PKT_CNT"}, + {true, "NCSI_TX_PT_PKT_TRUNC_CNT"}, + + {true, "NCSI_TX_PT_PKT_ERR_CNT"}, + {true, "NCSI_TX_CTRL_PKT_ERR_CNT"}, + {true, "NCSI_RX_CTRL_PKT_TRUNC_CNT"}, + {true, "NCSI_RX_CTRL_PKT_CFLIT_CNT"}, + {false, "Reserved"}, + {false, "Reserved"}, + + {true, "NCSI_MAC_RX_OCTETS_OK"}, + {true, "NCSI_MAC_RX_OCTETS_BAD"}, + {true, "NCSI_MAC_RX_UC_PKTS"}, + {true, "NCSI_MAC_RX_MC_PKTS"}, + {true, "NCSI_MAC_RX_BC_PKTS"}, + {true, "NCSI_MAC_RX_PKTS_64OCTETS"}, + + {true, "NCSI_MAC_RX_PKTS_65TO127OCTETS"}, + {true, "NCSI_MAC_RX_PKTS_128TO255OCTETS"}, + {true, "NCSI_MAC_RX_PKTS_255TO511OCTETS"}, + {true, "NCSI_MAC_RX_PKTS_512TO1023OCTETS"}, + {true, "NCSI_MAC_RX_PKTS_1024TO1518OCTETS"}, + {true, "NCSI_MAC_RX_PKTS_1519TOMAXOCTETS"}, + + {true, "NCSI_MAC_RX_FCS_ERRORS"}, + {true, "NCSI_MAC_RX_LONG_ERRORS"}, + {true, "NCSI_MAC_RX_JABBER_ERRORS"}, + {true, "NCSI_MAC_RX_RUNT_ERR_CNT"}, + {true, "NCSI_MAC_RX_SHORT_ERR_CNT"}, + {true, "NCSI_MAC_RX_FILT_PKT_CNT"}, + + {true, "NCSI_MAC_RX_OCTETS_TOTAL_FILT"}, + {true, "NCSI_MAC_TX_OCTETS_OK"}, + {true, "NCSI_MAC_TX_OCTETS_BAD"}, + {true, "NCSI_MAC_TX_UC_PKTS"}, + {true, "NCSI_MAC_TX_MC_PKTS"}, + {true, "NCSI_MAC_TX_BC_PKTS"}, + + {true, "NCSI_MAC_TX_PKTS_64OCTETS"}, + {true, "NCSI_MAC_TX_PKTS_65TO127OCTETS"}, + {true, "NCSI_MAC_TX_PKTS_128TO255OCTETS"}, + {true, "NCSI_MAC_TX_PKTS_256TO511OCTETS"}, + {true, "NCSI_MAC_TX_PKTS_512TO1023OCTETS"}, + {true, "NCSI_MAC_TX_PKTS_1024TO1518OCTETS"}, + + {true, "NCSI_MAC_TX_PKTS_1519TOMAXOCTETS"}, + {true, "NCSI_MAC_TX_UNDERRUN"}, + {true, "NCSI_MAC_TX_CRC_ERROR"}, + {true, "NCSI_MAC_TX_PAUSE_FRAMES"}, + {true, "NCSI_MAC_RX_PAD_PKTS"}, + {true, "NCSI_MAC_RX_PAUSE_FRAMES"}, +}; + +static const struct hclge_dbg_dfx_message hclge_dbg_rtc_reg[] = { + {false, "Reserved"}, + {true, "LGE_IGU_AFIFO_DFX_0"}, + {true, "LGE_IGU_AFIFO_DFX_1"}, + {true, "LGE_IGU_AFIFO_DFX_2"}, + {true, "LGE_IGU_AFIFO_DFX_3"}, + {true, "LGE_IGU_AFIFO_DFX_4"}, + + {true, "LGE_IGU_AFIFO_DFX_5"}, + {true, "LGE_IGU_AFIFO_DFX_6"}, + {true, "LGE_IGU_AFIFO_DFX_7"}, + {true, "LGE_EGU_AFIFO_DFX_0"}, + {true, "LGE_EGU_AFIFO_DFX_1"}, + {true, "LGE_EGU_AFIFO_DFX_2"}, + + {true, "LGE_EGU_AFIFO_DFX_3"}, + {true, "LGE_EGU_AFIFO_DFX_4"}, + {true, "LGE_EGU_AFIFO_DFX_5"}, + {true, "LGE_EGU_AFIFO_DFX_6"}, + {true, "LGE_EGU_AFIFO_DFX_7"}, + {true, "CGE_IGU_AFIFO_DFX_0"}, + + {true, "CGE_IGU_AFIFO_DFX_1"}, + {true, "CGE_EGU_AFIFO_DFX_0"}, + {true, "CGE_EGU_AFIFO_DFX_1"}, + {false, "Reserved"}, + {false, "Reserved"}, + {false, "Reserved"}, +}; + +static const struct hclge_dbg_dfx_message hclge_dbg_ppp_reg[] = { + {false, "Reserved"}, + {true, "DROP_FROM_PRT_PKT_CNT"}, + {true, "DROP_FROM_HOST_PKT_CNT"}, + {true, "DROP_TX_VLAN_PROC_CNT"}, + {true, "DROP_MNG_CNT"}, + {true, "DROP_FD_CNT"}, + + {true, "DROP_NO_DST_CNT"}, + {true, "DROP_MC_MBID_FULL_CNT"}, + {true, "DROP_SC_FILTERED"}, + {true, "PPP_MC_DROP_PKT_CNT"}, + {true, "DROP_PT_CNT"}, + {true, "DROP_MAC_ANTI_SPOOF_CNT"}, + + {true, "DROP_IG_VFV_CNT"}, + {true, "DROP_IG_PRTV_CNT"}, + {true, "DROP_CNM_PFC_PAUSE_CNT"}, + {true, "DROP_TORUS_TC_CNT"}, + {true, "DROP_TORUS_LPBK_CNT"}, + {true, "PPP_HFS_STS"}, + + {true, "PPP_MC_RSLT_STS"}, + {true, "PPP_P3U_STS"}, + {true, "PPP_RSLT_DESCR_STS"}, + {true, "PPP_UMV_STS_0"}, + {true, "PPP_UMV_STS_1"}, + {true, "PPP_VFV_STS"}, + + {true, "PPP_GRO_KEY_CNT"}, + {true, "PPP_GRO_INFO_CNT"}, + {true, "PPP_GRO_DROP_CNT"}, + {true, "PPP_GRO_OUT_CNT"}, + {true, "PPP_GRO_KEY_MATCH_DATA_CNT"}, + {true, "PPP_GRO_KEY_MATCH_TCAM_CNT"}, + + {true, "PPP_GRO_INFO_MATCH_CNT"}, + {true, "PPP_GRO_FREE_ENTRY_CNT"}, + {true, "PPP_GRO_INNER_DFX_SIGNAL"}, + {false, "Reserved"}, + {false, "Reserved"}, + {false, "Reserved"}, + + {true, "GET_RX_PKT_CNT_L"}, + {true, "GET_RX_PKT_CNT_H"}, + {true, "GET_TX_PKT_CNT_L"}, + {true, "GET_TX_PKT_CNT_H"}, + {true, "SEND_UC_PRT2HOST_PKT_CNT_L"}, + {true, "SEND_UC_PRT2HOST_PKT_CNT_H"}, + + {true, "SEND_UC_PRT2PRT_PKT_CNT_L"}, + {true, "SEND_UC_PRT2PRT_PKT_CNT_H"}, + {true, "SEND_UC_HOST2HOST_PKT_CNT_L"}, + {true, "SEND_UC_HOST2HOST_PKT_CNT_H"}, + {true, "SEND_UC_HOST2PRT_PKT_CNT_L"}, + {true, "SEND_UC_HOST2PRT_PKT_CNT_H"}, + + {true, "SEND_MC_FROM_PRT_CNT_L"}, + {true, "SEND_MC_FROM_PRT_CNT_H"}, + {true, "SEND_MC_FROM_HOST_CNT_L"}, + {true, "SEND_MC_FROM_HOST_CNT_H"}, + {true, "SSU_MC_RD_CNT_L"}, + {true, "SSU_MC_RD_CNT_H"}, + + {true, "SSU_MC_DROP_CNT_L"}, + {true, "SSU_MC_DROP_CNT_H"}, + {true, "SSU_MC_RD_PKT_CNT_L"}, + {true, "SSU_MC_RD_PKT_CNT_H"}, + {true, "PPP_MC_2HOST_PKT_CNT_L"}, + {true, "PPP_MC_2HOST_PKT_CNT_H"}, + + {true, "PPP_MC_2PRT_PKT_CNT_L"}, + {true, "PPP_MC_2PRT_PKT_CNT_H"}, + {true, "NTSNOS_PKT_CNT_L"}, + {true, "NTSNOS_PKT_CNT_H"}, + {true, "NTUP_PKT_CNT_L"}, + {true, "NTUP_PKT_CNT_H"}, + + {true, "NTLCL_PKT_CNT_L"}, + {true, "NTLCL_PKT_CNT_H"}, + {true, "NTTGT_PKT_CNT_L"}, + {true, "NTTGT_PKT_CNT_H"}, + {true, "RTNS_PKT_CNT_L"}, + {true, "RTNS_PKT_CNT_H"}, + + {true, "RTLPBK_PKT_CNT_L"}, + {true, "RTLPBK_PKT_CNT_H"}, + {true, "NR_PKT_CNT_L"}, + {true, "NR_PKT_CNT_H"}, + {true, "RR_PKT_CNT_L"}, + {true, "RR_PKT_CNT_H"}, + + {true, "MNG_TBL_HIT_CNT_L"}, + {true, "MNG_TBL_HIT_CNT_H"}, + {true, "FD_TBL_HIT_CNT_L"}, + {true, "FD_TBL_HIT_CNT_H"}, + {true, "FD_LKUP_CNT_L"}, + {true, "FD_LKUP_CNT_H"}, + + {true, "BC_HIT_CNT_L"}, + {true, "BC_HIT_CNT_H"}, + {true, "UM_TBL_UC_HIT_CNT_L"}, + {true, "UM_TBL_UC_HIT_CNT_H"}, + {true, "UM_TBL_MC_HIT_CNT_L"}, + {true, "UM_TBL_MC_HIT_CNT_H"}, + + {true, "UM_TBL_VMDQ1_HIT_CNT_L"}, + {true, "UM_TBL_VMDQ1_HIT_CNT_H"}, + {true, "MTA_TBL_HIT_CNT_L"}, + {true, "MTA_TBL_HIT_CNT_H"}, + {true, "FWD_BONDING_HIT_CNT_L"}, + {true, "FWD_BONDING_HIT_CNT_H"}, + + {true, "PROMIS_TBL_HIT_CNT_L"}, + {true, "PROMIS_TBL_HIT_CNT_H"}, + {true, "GET_TUNL_PKT_CNT_L"}, + {true, "GET_TUNL_PKT_CNT_H"}, + {true, "GET_BMC_PKT_CNT_L"}, + {true, "GET_BMC_PKT_CNT_H"}, + + {true, "SEND_UC_PRT2BMC_PKT_CNT_L"}, + {true, "SEND_UC_PRT2BMC_PKT_CNT_H"}, + {true, "SEND_UC_HOST2BMC_PKT_CNT_L"}, + {true, "SEND_UC_HOST2BMC_PKT_CNT_H"}, + {true, "SEND_UC_BMC2HOST_PKT_CNT_L"}, + {true, "SEND_UC_BMC2HOST_PKT_CNT_H"}, + + {true, "SEND_UC_BMC2PRT_PKT_CNT_L"}, + {true, "SEND_UC_BMC2PRT_PKT_CNT_H"}, + {true, "PPP_MC_2BMC_PKT_CNT_L"}, + {true, "PPP_MC_2BMC_PKT_CNT_H"}, + {true, "VLAN_MIRR_CNT_L"}, + {true, "VLAN_MIRR_CNT_H"}, + + {true, "IG_MIRR_CNT_L"}, + {true, "IG_MIRR_CNT_H"}, + {true, "EG_MIRR_CNT_L"}, + {true, "EG_MIRR_CNT_H"}, + {true, "RX_DEFAULT_HOST_HIT_CNT_L"}, + {true, "RX_DEFAULT_HOST_HIT_CNT_H"}, + + {true, "LAN_PAIR_CNT_L"}, + {true, "LAN_PAIR_CNT_H"}, + {true, "UM_TBL_MC_HIT_PKT_CNT_L"}, + {true, "UM_TBL_MC_HIT_PKT_CNT_H"}, + {true, "MTA_TBL_HIT_PKT_CNT_L"}, + {true, "MTA_TBL_HIT_PKT_CNT_H"}, + + {true, "PROMIS_TBL_HIT_PKT_CNT_L"}, + {true, "PROMIS_TBL_HIT_PKT_CNT_H"}, + {false, "Reserved"}, + {false, "Reserved"}, + {false, "Reserved"}, + {false, "Reserved"}, +}; + +static const struct hclge_dbg_dfx_message hclge_dbg_rcb_reg[] = { + {false, "Reserved"}, + {true, "FSM_DFX_ST0"}, + {true, "FSM_DFX_ST1"}, + {true, "FSM_DFX_ST2"}, + {true, "FIFO_DFX_ST0"}, + {true, "FIFO_DFX_ST1"}, + + {true, "FIFO_DFX_ST2"}, + {true, "FIFO_DFX_ST3"}, + {true, "FIFO_DFX_ST4"}, + {true, "FIFO_DFX_ST5"}, + {true, "FIFO_DFX_ST6"}, + {true, "FIFO_DFX_ST7"}, + + {true, "FIFO_DFX_ST8"}, + {true, "FIFO_DFX_ST9"}, + {true, "FIFO_DFX_ST10"}, + {true, "FIFO_DFX_ST11"}, + {true, "Q_CREDIT_VLD_0"}, + {true, "Q_CREDIT_VLD_1"}, + + {true, "Q_CREDIT_VLD_2"}, + {true, "Q_CREDIT_VLD_3"}, + {true, "Q_CREDIT_VLD_4"}, + {true, "Q_CREDIT_VLD_5"}, + {true, "Q_CREDIT_VLD_6"}, + {true, "Q_CREDIT_VLD_7"}, + + {true, "Q_CREDIT_VLD_8"}, + {true, "Q_CREDIT_VLD_9"}, + {true, "Q_CREDIT_VLD_10"}, + {true, "Q_CREDIT_VLD_11"}, + {true, "Q_CREDIT_VLD_12"}, + {true, "Q_CREDIT_VLD_13"}, + + {true, "Q_CREDIT_VLD_14"}, + {true, "Q_CREDIT_VLD_15"}, + {true, "Q_CREDIT_VLD_16"}, + {true, "Q_CREDIT_VLD_17"}, + {true, "Q_CREDIT_VLD_18"}, + {true, "Q_CREDIT_VLD_19"}, + + {true, "Q_CREDIT_VLD_20"}, + {true, "Q_CREDIT_VLD_21"}, + {true, "Q_CREDIT_VLD_22"}, + {true, "Q_CREDIT_VLD_23"}, + {true, "Q_CREDIT_VLD_24"}, + {true, "Q_CREDIT_VLD_25"}, + + {true, "Q_CREDIT_VLD_26"}, + {true, "Q_CREDIT_VLD_27"}, + {true, "Q_CREDIT_VLD_28"}, + {true, "Q_CREDIT_VLD_29"}, + {true, "Q_CREDIT_VLD_30"}, + {true, "Q_CREDIT_VLD_31"}, + + {true, "GRO_BD_SERR_CNT"}, + {true, "GRO_CONTEXT_SERR_CNT"}, + {true, "RX_STASH_CFG_SERR_CNT"}, + {true, "AXI_RD_FBD_SERR_CNT"}, + {true, "GRO_BD_MERR_CNT"}, + {true, "GRO_CONTEXT_MERR_CNT"}, + + {true, "RX_STASH_CFG_MERR_CNT"}, + {true, "AXI_RD_FBD_MERR_CNT"}, + {false, "Reserved"}, + {false, "Reserved"}, + {false, "Reserved"}, + {false, "Reserved"}, +}; + +static const struct hclge_dbg_dfx_message hclge_dbg_tqp_reg[] = { + {true, "q_num"}, + {true, "RCB_CFG_RX_RING_TAIL"}, + {true, "RCB_CFG_RX_RING_HEAD"}, + {true, "RCB_CFG_RX_RING_FBDNUM"}, + {true, "RCB_CFG_RX_RING_OFFSET"}, + {true, "RCB_CFG_RX_RING_FBDOFFSET"}, + + {true, "RCB_CFG_RX_RING_PKTNUM_RECORD"}, + {true, "RCB_CFG_TX_RING_TAIL"}, + {true, "RCB_CFG_TX_RING_HEAD"}, + {true, "RCB_CFG_TX_RING_FBDNUM"}, + {true, "RCB_CFG_TX_RING_OFFSET"}, + {true, "RCB_CFG_TX_RING_EBDNUM"}, +}; + static const struct hclge_dbg_reg_type_info hclge_dbg_reg_info[] = { { .cmd = HNAE3_DBG_CMD_REG_BIOS_COMMON, .dfx_msg = &hclge_dbg_bios_common_reg[0], @@ -81,48 +724,6 @@ static const struct hclge_dbg_reg_type_info hclge_dbg_reg_info[] = { .cmd = HCLGE_OPC_DFX_TQP_REG } }, }; -/* make sure: len(name) + interval >= maxlen(item data) + 2, - * for example, name = "pkt_num"(len: 7), the prototype of item data is u32, - * and print as "%u"(maxlen: 10), so the interval should be at least 5. - */ -static void hclge_dbg_fill_content(char *content, u16 len, - const struct hclge_dbg_item *items, - const char **result, u16 size) -{ -#define HCLGE_DBG_LINE_END_LEN 2 - char *pos = content; - u16 item_len; - u16 i; - - if (!len) { - return; - } else if (len <= HCLGE_DBG_LINE_END_LEN) { - *pos++ = '\0'; - return; - } - - memset(content, ' ', len); - len -= HCLGE_DBG_LINE_END_LEN; - - for (i = 0; i < size; i++) { - item_len = strlen(items[i].name) + items[i].interval; - if (len < item_len) - break; - - if (result) { - if (item_len < strlen(result[i])) - break; - memcpy(pos, result[i], strlen(result[i])); - } else { - memcpy(pos, items[i].name, strlen(items[i].name)); - } - pos += item_len; - len -= item_len; - } - *pos++ = '\n'; - *pos++ = '\0'; -} - static char *hclge_dbg_get_func_id_str(char *buf, u8 id) { if (id) @@ -161,10 +762,8 @@ static int hclge_dbg_get_dfx_bd_num(struct hclge_dev *hdev, int offset, return 0; } -static int hclge_dbg_cmd_send(struct hclge_dev *hdev, - struct hclge_desc *desc_src, - int index, int bd_num, - enum hclge_opcode_type cmd) +int hclge_dbg_cmd_send(struct hclge_dev *hdev, struct hclge_desc *desc_src, + int index, int bd_num, enum hclge_opcode_type cmd) { struct hclge_desc *desc = desc_src; int ret, i; @@ -188,14 +787,14 @@ static int hclge_dbg_cmd_send(struct hclge_dev *hdev, static int hclge_dbg_dump_reg_tqp(struct hclge_dev *hdev, const struct hclge_dbg_reg_type_info *reg_info, - char *buf, int len, int *pos) + struct seq_file *s) { const struct hclge_dbg_dfx_message *dfx_message = reg_info->dfx_msg; const struct hclge_dbg_reg_common_msg *reg_msg = ®_info->reg_msg; + u32 index, entry, i, cnt, min_num; struct hclge_desc *desc_src; - u32 index, entry, i, cnt; - int bd_num, min_num, ret; struct hclge_desc *desc; + int bd_num, ret; ret = hclge_dbg_get_dfx_bd_num(hdev, reg_msg->offset, &bd_num); if (ret) @@ -208,13 +807,12 @@ hclge_dbg_dump_reg_tqp(struct hclge_dev *hdev, min_num = min_t(int, bd_num * HCLGE_DESC_DATA_LEN, reg_msg->msg_num); for (i = 0, cnt = 0; i < min_num; i++, dfx_message++) - *pos += scnprintf(buf + *pos, len - *pos, "item%u = %s\n", - cnt++, dfx_message->message); + seq_printf(s, "item%u = %s\n", cnt++, dfx_message->message); for (i = 0; i < cnt; i++) - *pos += scnprintf(buf + *pos, len - *pos, "item%u\t", i); + seq_printf(s, "item%u\t", i); - *pos += scnprintf(buf + *pos, len - *pos, "\n"); + seq_puts(s, "\n"); for (index = 0; index < hdev->vport[0].alloc_tqps; index++) { dfx_message = reg_info->dfx_msg; @@ -229,10 +827,9 @@ hclge_dbg_dump_reg_tqp(struct hclge_dev *hdev, if (i > 0 && !entry) desc++; - *pos += scnprintf(buf + *pos, len - *pos, "%#x\t", - le32_to_cpu(desc->data[entry])); + seq_printf(s, "%#x\t", le32_to_cpu(desc->data[entry])); } - *pos += scnprintf(buf + *pos, len - *pos, "\n"); + seq_puts(s, "\n"); } kfree(desc_src); @@ -242,14 +839,14 @@ hclge_dbg_dump_reg_tqp(struct hclge_dev *hdev, static int hclge_dbg_dump_reg_common(struct hclge_dev *hdev, const struct hclge_dbg_reg_type_info *reg_info, - char *buf, int len, int *pos) + struct seq_file *s) { const struct hclge_dbg_reg_common_msg *reg_msg = ®_info->reg_msg; const struct hclge_dbg_dfx_message *dfx_message = reg_info->dfx_msg; struct hclge_desc *desc_src; - int bd_num, min_num, ret; + int bd_num, min_num, ret, i; struct hclge_desc *desc; - u32 entry, i; + u32 entry; ret = hclge_dbg_get_dfx_bd_num(hdev, reg_msg->offset, &bd_num); if (ret) @@ -276,9 +873,8 @@ hclge_dbg_dump_reg_common(struct hclge_dev *hdev, if (!dfx_message->flag) continue; - *pos += scnprintf(buf + *pos, len - *pos, "%s: %#x\n", - dfx_message->message, - le32_to_cpu(desc->data[entry])); + seq_printf(s, "%s: %#x\n", dfx_message->message, + le32_to_cpu(desc->data[entry])); } kfree(desc_src); @@ -302,8 +898,8 @@ static const struct hclge_dbg_status_dfx_info hclge_dbg_mac_en_status[] = { {HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B, "mac_tx_oversize_truncate_en"} }; -static int hclge_dbg_dump_mac_enable_status(struct hclge_dev *hdev, char *buf, - int len, int *pos) +static int hclge_dbg_dump_mac_enable_status(struct hclge_dev *hdev, + struct seq_file *s) { struct hclge_config_mac_mode_cmd *req; struct hclge_desc desc; @@ -324,16 +920,15 @@ static int hclge_dbg_dump_mac_enable_status(struct hclge_dev *hdev, char *buf, for (i = 0; i < ARRAY_SIZE(hclge_dbg_mac_en_status); i++) { offset = hclge_dbg_mac_en_status[i].offset; - *pos += scnprintf(buf + *pos, len - *pos, "%s: %#x\n", - hclge_dbg_mac_en_status[i].message, - hnae3_get_bit(loop_en, offset)); + seq_printf(s, "%s: %#x\n", hclge_dbg_mac_en_status[i].message, + hnae3_get_bit(loop_en, offset)); } return 0; } -static int hclge_dbg_dump_mac_frame_size(struct hclge_dev *hdev, char *buf, - int len, int *pos) +static int hclge_dbg_dump_mac_frame_size(struct hclge_dev *hdev, + struct seq_file *s) { struct hclge_config_max_frm_size_cmd *req; struct hclge_desc desc; @@ -350,16 +945,14 @@ static int hclge_dbg_dump_mac_frame_size(struct hclge_dev *hdev, char *buf, req = (struct hclge_config_max_frm_size_cmd *)desc.data; - *pos += scnprintf(buf + *pos, len - *pos, "max_frame_size: %u\n", - le16_to_cpu(req->max_frm_size)); - *pos += scnprintf(buf + *pos, len - *pos, "min_frame_size: %u\n", - req->min_frm_size); + seq_printf(s, "max_frame_size: %u\n", le16_to_cpu(req->max_frm_size)); + seq_printf(s, "min_frame_size: %u\n", req->min_frm_size); return 0; } -static int hclge_dbg_dump_mac_speed_duplex(struct hclge_dev *hdev, char *buf, - int len, int *pos) +static int hclge_dbg_dump_mac_speed_duplex(struct hclge_dev *hdev, + struct seq_file *s) { #define HCLGE_MAC_SPEED_SHIFT 0 #define HCLGE_MAC_SPEED_MASK GENMASK(5, 0) @@ -380,33 +973,31 @@ static int hclge_dbg_dump_mac_speed_duplex(struct hclge_dev *hdev, char *buf, req = (struct hclge_config_mac_speed_dup_cmd *)desc.data; - *pos += scnprintf(buf + *pos, len - *pos, "speed: %#lx\n", - hnae3_get_field(req->speed_dup, HCLGE_MAC_SPEED_MASK, - HCLGE_MAC_SPEED_SHIFT)); - *pos += scnprintf(buf + *pos, len - *pos, "duplex: %#x\n", - hnae3_get_bit(req->speed_dup, - HCLGE_MAC_DUPLEX_SHIFT)); + seq_printf(s, "speed: %#lx\n", + hnae3_get_field(req->speed_dup, HCLGE_MAC_SPEED_MASK, + HCLGE_MAC_SPEED_SHIFT)); + seq_printf(s, "duplex: %#x\n", + hnae3_get_bit(req->speed_dup, HCLGE_MAC_DUPLEX_SHIFT)); return 0; } -static int hclge_dbg_dump_mac(struct hclge_dev *hdev, char *buf, int len) +static int hclge_dbg_dump_mac(struct seq_file *s, void *data) { - int pos = 0; + struct hclge_dev *hdev = hclge_seq_file_to_hdev(s); int ret; - ret = hclge_dbg_dump_mac_enable_status(hdev, buf, len, &pos); + ret = hclge_dbg_dump_mac_enable_status(hdev, s); if (ret) return ret; - ret = hclge_dbg_dump_mac_frame_size(hdev, buf, len, &pos); + ret = hclge_dbg_dump_mac_frame_size(hdev, s); if (ret) return ret; - return hclge_dbg_dump_mac_speed_duplex(hdev, buf, len, &pos); + return hclge_dbg_dump_mac_speed_duplex(hdev, s); } -static int hclge_dbg_dump_dcb_qset(struct hclge_dev *hdev, char *buf, int len, - int *pos) +static int hclge_dbg_dump_dcb_qset(struct hclge_dev *hdev, struct seq_file *s) { struct hclge_dbg_bitmap_cmd req; struct hclge_desc desc; @@ -417,8 +1008,8 @@ static int hclge_dbg_dump_dcb_qset(struct hclge_dev *hdev, char *buf, int len, if (ret) return ret; - *pos += scnprintf(buf + *pos, len - *pos, - "qset_id roce_qset_mask nic_qset_mask qset_shaping_pass qset_bp_status\n"); + seq_puts(s, "qset_id roce_qset_mask nic_qset_mask "); + seq_puts(s, "qset_shaping_pass qset_bp_status\n"); for (qset_id = 0; qset_id < qset_num; qset_id++) { ret = hclge_dbg_cmd_send(hdev, &desc, qset_id, 1, HCLGE_OPC_QSET_DFX_STS); @@ -427,17 +1018,14 @@ static int hclge_dbg_dump_dcb_qset(struct hclge_dev *hdev, char *buf, int len, req.bitmap = (u8)le32_to_cpu(desc.data[1]); - *pos += scnprintf(buf + *pos, len - *pos, - "%04u %#x %#x %#x %#x\n", - qset_id, req.bit0, req.bit1, req.bit2, - req.bit3); + seq_printf(s, "%04u %#-16x%#-15x%#-19x%#-x\n", + qset_id, req.bit0, req.bit1, req.bit2, req.bit3); } return 0; } -static int hclge_dbg_dump_dcb_pri(struct hclge_dev *hdev, char *buf, int len, - int *pos) +static int hclge_dbg_dump_dcb_pri(struct hclge_dev *hdev, struct seq_file *s) { struct hclge_dbg_bitmap_cmd req; struct hclge_desc desc; @@ -448,8 +1036,7 @@ static int hclge_dbg_dump_dcb_pri(struct hclge_dev *hdev, char *buf, int len, if (ret) return ret; - *pos += scnprintf(buf + *pos, len - *pos, - "pri_id pri_mask pri_cshaping_pass pri_pshaping_pass\n"); + seq_puts(s, "pri_id pri_mask pri_cshaping_pass pri_pshaping_pass\n"); for (pri_id = 0; pri_id < pri_num; pri_id++) { ret = hclge_dbg_cmd_send(hdev, &desc, pri_id, 1, HCLGE_OPC_PRI_DFX_STS); @@ -458,24 +1045,21 @@ static int hclge_dbg_dump_dcb_pri(struct hclge_dev *hdev, char *buf, int len, req.bitmap = (u8)le32_to_cpu(desc.data[1]); - *pos += scnprintf(buf + *pos, len - *pos, - "%03u %#x %#x %#x\n", - pri_id, req.bit0, req.bit1, req.bit2); + seq_printf(s, "%03u %#-10x%#-19x%#-x\n", + pri_id, req.bit0, req.bit1, req.bit2); } return 0; } -static int hclge_dbg_dump_dcb_pg(struct hclge_dev *hdev, char *buf, int len, - int *pos) +static int hclge_dbg_dump_dcb_pg(struct hclge_dev *hdev, struct seq_file *s) { struct hclge_dbg_bitmap_cmd req; struct hclge_desc desc; u8 pg_id; int ret; - *pos += scnprintf(buf + *pos, len - *pos, - "pg_id pg_mask pg_cshaping_pass pg_pshaping_pass\n"); + seq_puts(s, "pg_id pg_mask pg_cshaping_pass pg_pshaping_pass\n"); for (pg_id = 0; pg_id < hdev->tm_info.num_pg; pg_id++) { ret = hclge_dbg_cmd_send(hdev, &desc, pg_id, 1, HCLGE_OPC_PG_DFX_STS); @@ -484,47 +1068,41 @@ static int hclge_dbg_dump_dcb_pg(struct hclge_dev *hdev, char *buf, int len, req.bitmap = (u8)le32_to_cpu(desc.data[1]); - *pos += scnprintf(buf + *pos, len - *pos, - "%03u %#x %#x %#x\n", - pg_id, req.bit0, req.bit1, req.bit2); + seq_printf(s, "%03u %#-9x%#-18x%#-x\n", + pg_id, req.bit0, req.bit1, req.bit2); } return 0; } -static int hclge_dbg_dump_dcb_queue(struct hclge_dev *hdev, char *buf, int len, - int *pos) +static int hclge_dbg_dump_dcb_queue(struct hclge_dev *hdev, struct seq_file *s) { struct hclge_desc desc; u16 nq_id; int ret; - *pos += scnprintf(buf + *pos, len - *pos, - "nq_id sch_nic_queue_cnt sch_roce_queue_cnt\n"); + seq_puts(s, "nq_id sch_nic_queue_cnt sch_roce_queue_cnt\n"); for (nq_id = 0; nq_id < hdev->num_tqps; nq_id++) { ret = hclge_dbg_cmd_send(hdev, &desc, nq_id, 1, HCLGE_OPC_SCH_NQ_CNT); if (ret) return ret; - *pos += scnprintf(buf + *pos, len - *pos, "%04u %#x", - nq_id, le32_to_cpu(desc.data[1])); + seq_printf(s, "%04u %#-19x", + nq_id, le32_to_cpu(desc.data[1])); ret = hclge_dbg_cmd_send(hdev, &desc, nq_id, 1, HCLGE_OPC_SCH_RQ_CNT); if (ret) return ret; - *pos += scnprintf(buf + *pos, len - *pos, - " %#x\n", - le32_to_cpu(desc.data[1])); + seq_printf(s, "%#-x\n", le32_to_cpu(desc.data[1])); } return 0; } -static int hclge_dbg_dump_dcb_port(struct hclge_dev *hdev, char *buf, int len, - int *pos) +static int hclge_dbg_dump_dcb_port(struct hclge_dev *hdev, struct seq_file *s) { struct hclge_dbg_bitmap_cmd req; struct hclge_desc desc; @@ -538,16 +1116,13 @@ static int hclge_dbg_dump_dcb_port(struct hclge_dev *hdev, char *buf, int len, req.bitmap = (u8)le32_to_cpu(desc.data[1]); - *pos += scnprintf(buf + *pos, len - *pos, "port_mask: %#x\n", - req.bit0); - *pos += scnprintf(buf + *pos, len - *pos, "port_shaping_pass: %#x\n", - req.bit1); + seq_printf(s, "port_mask: %#x\n", req.bit0); + seq_printf(s, "port_shaping_pass: %#x\n", req.bit1); return 0; } -static int hclge_dbg_dump_dcb_tm(struct hclge_dev *hdev, char *buf, int len, - int *pos) +static int hclge_dbg_dump_dcb_tm(struct hclge_dev *hdev, struct seq_file *s) { struct hclge_desc desc[2]; u8 port_id = 0; @@ -558,32 +1133,23 @@ static int hclge_dbg_dump_dcb_tm(struct hclge_dev *hdev, char *buf, int len, if (ret) return ret; - *pos += scnprintf(buf + *pos, len - *pos, "SCH_NIC_NUM: %#x\n", - le32_to_cpu(desc[0].data[1])); - *pos += scnprintf(buf + *pos, len - *pos, "SCH_ROCE_NUM: %#x\n", - le32_to_cpu(desc[0].data[2])); + seq_printf(s, "SCH_NIC_NUM: %#x\n", le32_to_cpu(desc[0].data[1])); + seq_printf(s, "SCH_ROCE_NUM: %#x\n", le32_to_cpu(desc[0].data[2])); ret = hclge_dbg_cmd_send(hdev, desc, port_id, 2, HCLGE_OPC_TM_INTERNAL_STS); if (ret) return ret; - *pos += scnprintf(buf + *pos, len - *pos, "pri_bp: %#x\n", - le32_to_cpu(desc[0].data[1])); - *pos += scnprintf(buf + *pos, len - *pos, "fifo_dfx_info: %#x\n", - le32_to_cpu(desc[0].data[2])); - *pos += scnprintf(buf + *pos, len - *pos, - "sch_roce_fifo_afull_gap: %#x\n", - le32_to_cpu(desc[0].data[3])); - *pos += scnprintf(buf + *pos, len - *pos, - "tx_private_waterline: %#x\n", - le32_to_cpu(desc[0].data[4])); - *pos += scnprintf(buf + *pos, len - *pos, "tm_bypass_en: %#x\n", - le32_to_cpu(desc[0].data[5])); - *pos += scnprintf(buf + *pos, len - *pos, "SSU_TM_BYPASS_EN: %#x\n", - le32_to_cpu(desc[1].data[0])); - *pos += scnprintf(buf + *pos, len - *pos, "SSU_RESERVE_CFG: %#x\n", - le32_to_cpu(desc[1].data[1])); + seq_printf(s, "pri_bp: %#x\n", le32_to_cpu(desc[0].data[1])); + seq_printf(s, "fifo_dfx_info: %#x\n", le32_to_cpu(desc[0].data[2])); + seq_printf(s, "sch_roce_fifo_afull_gap: %#x\n", + le32_to_cpu(desc[0].data[3])); + seq_printf(s, "tx_private_waterline: %#x\n", + le32_to_cpu(desc[0].data[4])); + seq_printf(s, "tm_bypass_en: %#x\n", le32_to_cpu(desc[0].data[5])); + seq_printf(s, "SSU_TM_BYPASS_EN: %#x\n", le32_to_cpu(desc[1].data[0])); + seq_printf(s, "SSU_RESERVE_CFG: %#x\n", le32_to_cpu(desc[1].data[1])); if (hdev->hw.mac.media_type == HNAE3_MEDIA_TYPE_COPPER) return 0; @@ -593,65 +1159,60 @@ static int hclge_dbg_dump_dcb_tm(struct hclge_dev *hdev, char *buf, int len, if (ret) return ret; - *pos += scnprintf(buf + *pos, len - *pos, "TC_MAP_SEL: %#x\n", - le32_to_cpu(desc[0].data[1])); - *pos += scnprintf(buf + *pos, len - *pos, "IGU_PFC_PRI_EN: %#x\n", - le32_to_cpu(desc[0].data[2])); - *pos += scnprintf(buf + *pos, len - *pos, "MAC_PFC_PRI_EN: %#x\n", - le32_to_cpu(desc[0].data[3])); - *pos += scnprintf(buf + *pos, len - *pos, "IGU_PRI_MAP_TC_CFG: %#x\n", - le32_to_cpu(desc[0].data[4])); - *pos += scnprintf(buf + *pos, len - *pos, - "IGU_TX_PRI_MAP_TC_CFG: %#x\n", - le32_to_cpu(desc[0].data[5])); + seq_printf(s, "TC_MAP_SEL: %#x\n", le32_to_cpu(desc[0].data[1])); + seq_printf(s, "IGU_PFC_PRI_EN: %#x\n", le32_to_cpu(desc[0].data[2])); + seq_printf(s, "MAC_PFC_PRI_EN: %#x\n", le32_to_cpu(desc[0].data[3])); + seq_printf(s, "IGU_PRI_MAP_TC_CFG: %#x\n", + le32_to_cpu(desc[0].data[4])); + seq_printf(s, "IGU_TX_PRI_MAP_TC_CFG: %#x\n", + le32_to_cpu(desc[0].data[5])); return 0; } -static int hclge_dbg_dump_dcb(struct hclge_dev *hdev, char *buf, int len) +static int hclge_dbg_dump_dcb(struct seq_file *s, void *data) { - int pos = 0; + struct hclge_dev *hdev = hclge_seq_file_to_hdev(s); int ret; - ret = hclge_dbg_dump_dcb_qset(hdev, buf, len, &pos); + ret = hclge_dbg_dump_dcb_qset(hdev, s); if (ret) return ret; - ret = hclge_dbg_dump_dcb_pri(hdev, buf, len, &pos); + ret = hclge_dbg_dump_dcb_pri(hdev, s); if (ret) return ret; - ret = hclge_dbg_dump_dcb_pg(hdev, buf, len, &pos); + ret = hclge_dbg_dump_dcb_pg(hdev, s); if (ret) return ret; - ret = hclge_dbg_dump_dcb_queue(hdev, buf, len, &pos); + ret = hclge_dbg_dump_dcb_queue(hdev, s); if (ret) return ret; - ret = hclge_dbg_dump_dcb_port(hdev, buf, len, &pos); + ret = hclge_dbg_dump_dcb_port(hdev, s); if (ret) return ret; - return hclge_dbg_dump_dcb_tm(hdev, buf, len, &pos); + return hclge_dbg_dump_dcb_tm(hdev, s); } -static int hclge_dbg_dump_reg_cmd(struct hclge_dev *hdev, - enum hnae3_dbg_cmd cmd, char *buf, int len) +static int hclge_dbg_dump_reg_cmd(enum hnae3_dbg_cmd cmd, struct seq_file *s) { + struct hclge_dev *hdev = hclge_seq_file_to_hdev(s); const struct hclge_dbg_reg_type_info *reg_info; - int pos = 0, ret = 0; - int i; + int ret = 0; + u32 i; for (i = 0; i < ARRAY_SIZE(hclge_dbg_reg_info); i++) { reg_info = &hclge_dbg_reg_info[i]; if (cmd == reg_info->cmd) { if (cmd == HNAE3_DBG_CMD_REG_TQP) - return hclge_dbg_dump_reg_tqp(hdev, reg_info, - buf, len, &pos); + return hclge_dbg_dump_reg_tqp(hdev, + reg_info, s); - ret = hclge_dbg_dump_reg_common(hdev, reg_info, buf, - len, &pos); + ret = hclge_dbg_dump_reg_common(hdev, reg_info, s); if (ret) break; } @@ -660,12 +1221,57 @@ static int hclge_dbg_dump_reg_cmd(struct hclge_dev *hdev, return ret; } -static int hclge_dbg_dump_tc(struct hclge_dev *hdev, char *buf, int len) +static int hclge_dbg_dump_bios_reg_cmd(struct seq_file *s, void *data) { + return hclge_dbg_dump_reg_cmd(HNAE3_DBG_CMD_REG_BIOS_COMMON, s); +} + +static int hclge_dbg_dump_ssu_reg_cmd(struct seq_file *s, void *data) +{ + return hclge_dbg_dump_reg_cmd(HNAE3_DBG_CMD_REG_SSU, s); +} + +static int hclge_dbg_dump_igu_egu_reg_cmd(struct seq_file *s, void *data) +{ + return hclge_dbg_dump_reg_cmd(HNAE3_DBG_CMD_REG_IGU_EGU, s); +} + +static int hclge_dbg_dump_rpu_reg_cmd(struct seq_file *s, void *data) +{ + return hclge_dbg_dump_reg_cmd(HNAE3_DBG_CMD_REG_RPU, s); +} + +static int hclge_dbg_dump_ncsi_reg_cmd(struct seq_file *s, void *data) +{ + return hclge_dbg_dump_reg_cmd(HNAE3_DBG_CMD_REG_NCSI, s); +} + +static int hclge_dbg_dump_rtc_reg_cmd(struct seq_file *s, void *data) +{ + return hclge_dbg_dump_reg_cmd(HNAE3_DBG_CMD_REG_RTC, s); +} + +static int hclge_dbg_dump_ppp_reg_cmd(struct seq_file *s, void *data) +{ + return hclge_dbg_dump_reg_cmd(HNAE3_DBG_CMD_REG_PPP, s); +} + +static int hclge_dbg_dump_rcb_reg_cmd(struct seq_file *s, void *data) +{ + return hclge_dbg_dump_reg_cmd(HNAE3_DBG_CMD_REG_RCB, s); +} + +static int hclge_dbg_dump_tqp_reg_cmd(struct seq_file *s, void *data) +{ + return hclge_dbg_dump_reg_cmd(HNAE3_DBG_CMD_REG_TQP, s); +} + +static int hclge_dbg_dump_tc(struct seq_file *s, void *data) +{ + struct hclge_dev *hdev = hclge_seq_file_to_hdev(s); struct hclge_ets_tc_weight_cmd *ets_weight; + const char *sch_mode_str; struct hclge_desc desc; - char *sch_mode_str; - int pos = 0; int ret; u8 i; @@ -685,72 +1291,37 @@ static int hclge_dbg_dump_tc(struct hclge_dev *hdev, char *buf, int len) ets_weight = (struct hclge_ets_tc_weight_cmd *)desc.data; - pos += scnprintf(buf + pos, len - pos, "enabled tc number: %u\n", - hdev->tm_info.num_tc); - pos += scnprintf(buf + pos, len - pos, "weight_offset: %u\n", - ets_weight->weight_offset); + seq_printf(s, "enabled tc number: %u\n", hdev->tm_info.num_tc); + seq_printf(s, "weight_offset: %u\n", ets_weight->weight_offset); - pos += scnprintf(buf + pos, len - pos, "TC MODE WEIGHT\n"); + seq_puts(s, "TC MODE WEIGHT\n"); for (i = 0; i < HNAE3_MAX_TC; i++) { sch_mode_str = ets_weight->tc_weight[i] ? "dwrr" : "sp"; - pos += scnprintf(buf + pos, len - pos, "%u %4s %3u\n", - i, sch_mode_str, ets_weight->tc_weight[i]); + seq_printf(s, "%u %4s %3u\n", i, sch_mode_str, + ets_weight->tc_weight[i]); } return 0; } -static const struct hclge_dbg_item tm_pg_items[] = { - { "ID", 2 }, - { "PRI_MAP", 2 }, - { "MODE", 2 }, - { "DWRR", 2 }, - { "C_IR_B", 2 }, - { "C_IR_U", 2 }, - { "C_IR_S", 2 }, - { "C_BS_B", 2 }, - { "C_BS_S", 2 }, - { "C_FLAG", 2 }, - { "C_RATE(Mbps)", 2 }, - { "P_IR_B", 2 }, - { "P_IR_U", 2 }, - { "P_IR_S", 2 }, - { "P_BS_B", 2 }, - { "P_BS_S", 2 }, - { "P_FLAG", 2 }, - { "P_RATE(Mbps)", 0 } -}; - -static void hclge_dbg_fill_shaper_content(struct hclge_tm_shaper_para *para, - char **result, u8 *index) +static void hclge_dbg_fill_shaper_content(struct seq_file *s, + struct hclge_tm_shaper_para *para) { - sprintf(result[(*index)++], "%3u", para->ir_b); - sprintf(result[(*index)++], "%3u", para->ir_u); - sprintf(result[(*index)++], "%3u", para->ir_s); - sprintf(result[(*index)++], "%3u", para->bs_b); - sprintf(result[(*index)++], "%3u", para->bs_s); - sprintf(result[(*index)++], "%3u", para->flag); - sprintf(result[(*index)++], "%6u", para->rate); + seq_printf(s, "%-8u%-8u%-8u%-8u%-8u%-8u%-14u", para->ir_b, para->ir_u, + para->ir_s, para->bs_b, para->bs_s, para->flag, para->rate); } -static int __hclge_dbg_dump_tm_pg(struct hclge_dev *hdev, char *data_str, - char *buf, int len) +static int hclge_dbg_dump_tm_pg(struct seq_file *s, void *data) { struct hclge_tm_shaper_para c_shaper_para, p_shaper_para; - char *result[ARRAY_SIZE(tm_pg_items)], *sch_mode_str; - u8 pg_id, sch_mode, weight, pri_bit_map, i, j; - char content[HCLGE_DBG_TM_INFO_LEN]; - int pos = 0; + struct hclge_dev *hdev = hclge_seq_file_to_hdev(s); + u8 pg_id, sch_mode, weight, pri_bit_map; + const char *sch_mode_str; int ret; - for (i = 0; i < ARRAY_SIZE(tm_pg_items); i++) { - result[i] = data_str; - data_str += HCLGE_DBG_DATA_STR_LEN; - } - - hclge_dbg_fill_content(content, sizeof(content), tm_pg_items, - NULL, ARRAY_SIZE(tm_pg_items)); - pos += scnprintf(buf + pos, len - pos, "%s", content); + seq_puts(s, "ID PRI_MAP MODE DWRR C_IR_B C_IR_U C_IR_S C_BS_B "); + seq_puts(s, "C_BS_S C_FLAG C_RATE(Mbps) P_IR_B P_IR_U P_IR_S "); + seq_puts(s, "P_BS_B P_BS_S P_FLAG P_RATE(Mbps)\n"); for (pg_id = 0; pg_id < hdev->tm_info.num_pg; pg_id++) { ret = hclge_tm_get_pg_to_pri_map(hdev, pg_id, &pri_bit_map); @@ -780,68 +1351,41 @@ static int __hclge_dbg_dump_tm_pg(struct hclge_dev *hdev, char *data_str, sch_mode_str = sch_mode & HCLGE_TM_TX_SCHD_DWRR_MSK ? "dwrr" : "sp"; - j = 0; - sprintf(result[j++], "%02u", pg_id); - sprintf(result[j++], "0x%02x", pri_bit_map); - sprintf(result[j++], "%4s", sch_mode_str); - sprintf(result[j++], "%3u", weight); - hclge_dbg_fill_shaper_content(&c_shaper_para, result, &j); - hclge_dbg_fill_shaper_content(&p_shaper_para, result, &j); - - hclge_dbg_fill_content(content, sizeof(content), tm_pg_items, - (const char **)result, - ARRAY_SIZE(tm_pg_items)); - pos += scnprintf(buf + pos, len - pos, "%s", content); + seq_printf(s, "%02u 0x%-7x%-6s%-6u", pg_id, pri_bit_map, + sch_mode_str, weight); + hclge_dbg_fill_shaper_content(s, &c_shaper_para); + hclge_dbg_fill_shaper_content(s, &p_shaper_para); + seq_puts(s, "\n"); } return 0; } -static int hclge_dbg_dump_tm_pg(struct hclge_dev *hdev, char *buf, int len) -{ - char *data_str; - int ret; - - data_str = kcalloc(ARRAY_SIZE(tm_pg_items), - HCLGE_DBG_DATA_STR_LEN, GFP_KERNEL); - if (!data_str) - return -ENOMEM; - - ret = __hclge_dbg_dump_tm_pg(hdev, data_str, buf, len); - - kfree(data_str); - - return ret; -} - -static int hclge_dbg_dump_tm_port(struct hclge_dev *hdev, char *buf, int len) +static int hclge_dbg_dump_tm_port(struct seq_file *s, void *data) { + struct hclge_dev *hdev = hclge_seq_file_to_hdev(s); struct hclge_tm_shaper_para shaper_para; - int pos = 0; int ret; ret = hclge_tm_get_port_shaper(hdev, &shaper_para); if (ret) return ret; - pos += scnprintf(buf + pos, len - pos, - "IR_B IR_U IR_S BS_B BS_S FLAG RATE(Mbps)\n"); - pos += scnprintf(buf + pos, len - pos, - "%3u %3u %3u %3u %3u %1u %6u\n", - shaper_para.ir_b, shaper_para.ir_u, shaper_para.ir_s, - shaper_para.bs_b, shaper_para.bs_s, shaper_para.flag, - shaper_para.rate); + seq_puts(s, "IR_B IR_U IR_S BS_B BS_S FLAG RATE(Mbps)\n"); + seq_printf(s, "%3u %3u %3u %3u %3u %1u %6u\n", + shaper_para.ir_b, shaper_para.ir_u, shaper_para.ir_s, + shaper_para.bs_b, shaper_para.bs_s, shaper_para.flag, + shaper_para.rate); return 0; } static int hclge_dbg_dump_tm_bp_qset_map(struct hclge_dev *hdev, u8 tc_id, - char *buf, int len) + struct seq_file *s) { u32 qset_mapping[HCLGE_BP_EXT_GRP_NUM]; struct hclge_bp_to_qs_map_cmd *map; struct hclge_desc desc; - int pos = 0; u8 group_id; u8 grp_num; u16 i = 0; @@ -867,27 +1411,27 @@ static int hclge_dbg_dump_tm_bp_qset_map(struct hclge_dev *hdev, u8 tc_id, qset_mapping[group_id] = le32_to_cpu(map->qs_bit_map); } - pos += scnprintf(buf + pos, len - pos, "INDEX | TM BP QSET MAPPING:\n"); + seq_puts(s, "INDEX | TM BP QSET MAPPING:\n"); for (group_id = 0; group_id < grp_num / 8; group_id++) { - pos += scnprintf(buf + pos, len - pos, - "%04d | %08x:%08x:%08x:%08x:%08x:%08x:%08x:%08x\n", - group_id * 256, qset_mapping[i + 7], - qset_mapping[i + 6], qset_mapping[i + 5], - qset_mapping[i + 4], qset_mapping[i + 3], - qset_mapping[i + 2], qset_mapping[i + 1], - qset_mapping[i]); + seq_printf(s, + "%04d | %08x:%08x:%08x:%08x:%08x:%08x:%08x:%08x\n", + group_id * 256, qset_mapping[i + 7], + qset_mapping[i + 6], qset_mapping[i + 5], + qset_mapping[i + 4], qset_mapping[i + 3], + qset_mapping[i + 2], qset_mapping[i + 1], + qset_mapping[i]); i += 8; } - return pos; + return 0; } -static int hclge_dbg_dump_tm_map(struct hclge_dev *hdev, char *buf, int len) +static int hclge_dbg_dump_tm_map(struct seq_file *s, void *data) { + struct hclge_dev *hdev = hclge_seq_file_to_hdev(s); u16 queue_id; u16 qset_id; u8 link_vld; - int pos = 0; u8 pri_id; u8 tc_id; int ret; @@ -906,32 +1450,28 @@ static int hclge_dbg_dump_tm_map(struct hclge_dev *hdev, char *buf, int len) if (ret) return ret; - pos += scnprintf(buf + pos, len - pos, - "QUEUE_ID QSET_ID PRI_ID TC_ID\n"); - pos += scnprintf(buf + pos, len - pos, - "%04u %4u %3u %2u\n", - queue_id, qset_id, pri_id, tc_id); + seq_puts(s, "QUEUE_ID QSET_ID PRI_ID TC_ID\n"); + seq_printf(s, "%04u %4u %3u %2u\n", + queue_id, qset_id, pri_id, tc_id); if (!hnae3_dev_dcb_supported(hdev)) continue; - ret = hclge_dbg_dump_tm_bp_qset_map(hdev, tc_id, buf + pos, - len - pos); + ret = hclge_dbg_dump_tm_bp_qset_map(hdev, tc_id, s); if (ret < 0) return ret; - pos += ret; - pos += scnprintf(buf + pos, len - pos, "\n"); + seq_puts(s, "\n"); } return 0; } -static int hclge_dbg_dump_tm_nodes(struct hclge_dev *hdev, char *buf, int len) +static int hclge_dbg_dump_tm_nodes(struct seq_file *s, void *data) { + struct hclge_dev *hdev = hclge_seq_file_to_hdev(s); struct hclge_tm_nodes_cmd *nodes; struct hclge_desc desc; - int pos = 0; int ret; hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_NODES, true); @@ -944,65 +1484,36 @@ static int hclge_dbg_dump_tm_nodes(struct hclge_dev *hdev, char *buf, int len) nodes = (struct hclge_tm_nodes_cmd *)desc.data; - pos += scnprintf(buf + pos, len - pos, " BASE_ID MAX_NUM\n"); - pos += scnprintf(buf + pos, len - pos, "PG %4u %4u\n", - nodes->pg_base_id, nodes->pg_num); - pos += scnprintf(buf + pos, len - pos, "PRI %4u %4u\n", - nodes->pri_base_id, nodes->pri_num); - pos += scnprintf(buf + pos, len - pos, "QSET %4u %4u\n", - le16_to_cpu(nodes->qset_base_id), - le16_to_cpu(nodes->qset_num)); - pos += scnprintf(buf + pos, len - pos, "QUEUE %4u %4u\n", - le16_to_cpu(nodes->queue_base_id), - le16_to_cpu(nodes->queue_num)); + seq_puts(s, " BASE_ID MAX_NUM\n"); + seq_printf(s, "PG %4u %4u\n", nodes->pg_base_id, + nodes->pg_num); + seq_printf(s, "PRI %4u %4u\n", nodes->pri_base_id, + nodes->pri_num); + seq_printf(s, "QSET %4u %4u\n", + le16_to_cpu(nodes->qset_base_id), + le16_to_cpu(nodes->qset_num)); + seq_printf(s, "QUEUE %4u %4u\n", + le16_to_cpu(nodes->queue_base_id), + le16_to_cpu(nodes->queue_num)); return 0; } -static const struct hclge_dbg_item tm_pri_items[] = { - { "ID", 4 }, - { "MODE", 2 }, - { "DWRR", 2 }, - { "C_IR_B", 2 }, - { "C_IR_U", 2 }, - { "C_IR_S", 2 }, - { "C_BS_B", 2 }, - { "C_BS_S", 2 }, - { "C_FLAG", 2 }, - { "C_RATE(Mbps)", 2 }, - { "P_IR_B", 2 }, - { "P_IR_U", 2 }, - { "P_IR_S", 2 }, - { "P_BS_B", 2 }, - { "P_BS_S", 2 }, - { "P_FLAG", 2 }, - { "P_RATE(Mbps)", 0 } -}; - -static int hclge_dbg_dump_tm_pri(struct hclge_dev *hdev, char *buf, int len) +static int hclge_dbg_dump_tm_pri(struct seq_file *s, void *data) { struct hclge_tm_shaper_para c_shaper_para, p_shaper_para; - char *result[ARRAY_SIZE(tm_pri_items)], *sch_mode_str; - char content[HCLGE_DBG_TM_INFO_LEN]; - u8 pri_num, sch_mode, weight, i, j; - char *data_str; - int pos, ret; + struct hclge_dev *hdev = hclge_seq_file_to_hdev(s); + u8 pri_num, sch_mode, weight, i; + const char *sch_mode_str; + int ret; ret = hclge_tm_get_pri_num(hdev, &pri_num); if (ret) return ret; - data_str = kcalloc(ARRAY_SIZE(tm_pri_items), HCLGE_DBG_DATA_STR_LEN, - GFP_KERNEL); - if (!data_str) - return -ENOMEM; - - for (i = 0; i < ARRAY_SIZE(tm_pri_items); i++) - result[i] = &data_str[i * HCLGE_DBG_DATA_STR_LEN]; - - hclge_dbg_fill_content(content, sizeof(content), tm_pri_items, - NULL, ARRAY_SIZE(tm_pri_items)); - pos = scnprintf(buf, len, "%s", content); + seq_puts(s, "ID MODE DWRR C_IR_B C_IR_U C_IR_S C_BS_B "); + seq_puts(s, "C_BS_S C_FLAG C_RATE(Mbps) P_IR_B P_IR_U P_IR_S "); + seq_puts(s, "P_BS_B P_BS_S P_FLAG P_RATE(Mbps)\n"); for (i = 0; i < pri_num; i++) { ret = hclge_tm_get_pri_sch_mode(hdev, i, &sch_mode); @@ -1028,59 +1539,31 @@ static int hclge_dbg_dump_tm_pri(struct hclge_dev *hdev, char *buf, int len) sch_mode_str = sch_mode & HCLGE_TM_TX_SCHD_DWRR_MSK ? "dwrr" : "sp"; - j = 0; - sprintf(result[j++], "%04u", i); - sprintf(result[j++], "%4s", sch_mode_str); - sprintf(result[j++], "%3u", weight); - hclge_dbg_fill_shaper_content(&c_shaper_para, result, &j); - hclge_dbg_fill_shaper_content(&p_shaper_para, result, &j); - hclge_dbg_fill_content(content, sizeof(content), tm_pri_items, - (const char **)result, - ARRAY_SIZE(tm_pri_items)); - pos += scnprintf(buf + pos, len - pos, "%s", content); + seq_printf(s, "%04u %-6s%-6u", i, sch_mode_str, weight); + hclge_dbg_fill_shaper_content(s, &c_shaper_para); + hclge_dbg_fill_shaper_content(s, &p_shaper_para); + seq_puts(s, "\n"); } out: - kfree(data_str); return ret; } -static const struct hclge_dbg_item tm_qset_items[] = { - { "ID", 4 }, - { "MAP_PRI", 2 }, - { "LINK_VLD", 2 }, - { "MODE", 2 }, - { "DWRR", 2 }, - { "IR_B", 2 }, - { "IR_U", 2 }, - { "IR_S", 2 }, - { "BS_B", 2 }, - { "BS_S", 2 }, - { "FLAG", 2 }, - { "RATE(Mbps)", 0 } -}; - -static int hclge_dbg_dump_tm_qset(struct hclge_dev *hdev, char *buf, int len) +static int hclge_dbg_dump_tm_qset(struct seq_file *s, void *data) { - char data_str[ARRAY_SIZE(tm_qset_items)][HCLGE_DBG_DATA_STR_LEN]; - char *result[ARRAY_SIZE(tm_qset_items)], *sch_mode_str; + struct hclge_dev *hdev = hclge_seq_file_to_hdev(s); u8 priority, link_vld, sch_mode, weight; struct hclge_tm_shaper_para shaper_para; - char content[HCLGE_DBG_TM_INFO_LEN]; + const char *sch_mode_str; u16 qset_num, i; - int ret, pos; - u8 j; + int ret; ret = hclge_tm_get_qset_num(hdev, &qset_num); if (ret) return ret; - for (i = 0; i < ARRAY_SIZE(tm_qset_items); i++) - result[i] = &data_str[i][0]; - - hclge_dbg_fill_content(content, sizeof(content), tm_qset_items, - NULL, ARRAY_SIZE(tm_qset_items)); - pos = scnprintf(buf, len, "%s", content); + seq_puts(s, "ID MAP_PRI LINK_VLD MODE DWRR IR_B IR_U IR_S "); + seq_puts(s, "BS_B BS_S FLAG RATE(Mbps)\n"); for (i = 0; i < qset_num; i++) { ret = hclge_tm_get_qset_map_pri(hdev, i, &priority, &link_vld); @@ -1102,29 +1585,22 @@ static int hclge_dbg_dump_tm_qset(struct hclge_dev *hdev, char *buf, int len) sch_mode_str = sch_mode & HCLGE_TM_TX_SCHD_DWRR_MSK ? "dwrr" : "sp"; - j = 0; - sprintf(result[j++], "%04u", i); - sprintf(result[j++], "%4u", priority); - sprintf(result[j++], "%4u", link_vld); - sprintf(result[j++], "%4s", sch_mode_str); - sprintf(result[j++], "%3u", weight); - hclge_dbg_fill_shaper_content(&shaper_para, result, &j); - - hclge_dbg_fill_content(content, sizeof(content), tm_qset_items, - (const char **)result, - ARRAY_SIZE(tm_qset_items)); - pos += scnprintf(buf + pos, len - pos, "%s", content); + seq_printf(s, "%04u %-9u%-10u%-6s%-6u", i, priority, link_vld, + sch_mode_str, weight); + seq_printf(s, "%-6u%-6u%-6u%-6u%-6u%-6u%-14u\n", + shaper_para.ir_b, shaper_para.ir_u, shaper_para.ir_s, + shaper_para.bs_b, shaper_para.bs_s, shaper_para.flag, + shaper_para.rate); } return 0; } -static int hclge_dbg_dump_qos_pause_cfg(struct hclge_dev *hdev, char *buf, - int len) +static int hclge_dbg_dump_qos_pause_cfg(struct seq_file *s, void *data) { + struct hclge_dev *hdev = hclge_seq_file_to_hdev(s); struct hclge_cfg_pause_param_cmd *pause_param; struct hclge_desc desc; - int pos = 0; int ret; hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_MAC_PARA, true); @@ -1137,23 +1613,21 @@ static int hclge_dbg_dump_qos_pause_cfg(struct hclge_dev *hdev, char *buf, pause_param = (struct hclge_cfg_pause_param_cmd *)desc.data; - pos += scnprintf(buf + pos, len - pos, "pause_trans_gap: 0x%x\n", - pause_param->pause_trans_gap); - pos += scnprintf(buf + pos, len - pos, "pause_trans_time: 0x%x\n", - le16_to_cpu(pause_param->pause_trans_time)); + seq_printf(s, "pause_trans_gap: 0x%x\n", pause_param->pause_trans_gap); + seq_printf(s, "pause_trans_time: 0x%x\n", + le16_to_cpu(pause_param->pause_trans_time)); return 0; } #define HCLGE_DBG_TC_MASK 0x0F -static int hclge_dbg_dump_qos_pri_map(struct hclge_dev *hdev, char *buf, - int len) +static int hclge_dbg_dump_qos_pri_map(struct seq_file *s, void *data) { #define HCLGE_DBG_TC_BIT_WIDTH 4 + struct hclge_dev *hdev = hclge_seq_file_to_hdev(s); struct hclge_qos_pri_map_cmd *pri_map; struct hclge_desc desc; - int pos = 0; u8 *pri_tc; u8 tc, i; int ret; @@ -1168,33 +1642,33 @@ static int hclge_dbg_dump_qos_pri_map(struct hclge_dev *hdev, char *buf, pri_map = (struct hclge_qos_pri_map_cmd *)desc.data; - pos += scnprintf(buf + pos, len - pos, "vlan_to_pri: 0x%x\n", - pri_map->vlan_pri); - pos += scnprintf(buf + pos, len - pos, "PRI TC\n"); + seq_printf(s, "vlan_to_pri: 0x%x\n", pri_map->vlan_pri); + seq_puts(s, "PRI TC\n"); pri_tc = (u8 *)pri_map; for (i = 0; i < HNAE3_MAX_TC; i++) { tc = pri_tc[i >> 1] >> ((i & 1) * HCLGE_DBG_TC_BIT_WIDTH); tc &= HCLGE_DBG_TC_MASK; - pos += scnprintf(buf + pos, len - pos, "%u %u\n", i, tc); + seq_printf(s, "%u %u\n", i, tc); } return 0; } -static int hclge_dbg_dump_qos_dscp_map(struct hclge_dev *hdev, char *buf, - int len) +static int hclge_dbg_dump_qos_dscp_map(struct seq_file *s, void *data) { - struct hnae3_knic_private_info *kinfo = &hdev->vport[0].nic.kinfo; + struct hclge_dev *hdev = hclge_seq_file_to_hdev(s); struct hclge_desc desc[HCLGE_DSCP_MAP_TC_BD_NUM]; + struct hnae3_knic_private_info *kinfo; u8 *req0 = (u8 *)desc[0].data; u8 *req1 = (u8 *)desc[1].data; u8 dscp_tc[HNAE3_MAX_DSCP]; - int pos, ret; + int ret; u8 i, j; - pos = scnprintf(buf, len, "tc map mode: %s\n", - tc_map_mode_str[kinfo->tc_map_mode]); + kinfo = &hdev->vport[0].nic.kinfo; + + seq_printf(s, "tc map mode: %s\n", tc_map_mode_str[kinfo->tc_map_mode]); if (kinfo->tc_map_mode != HNAE3_TC_MAP_MODE_DSCP) return 0; @@ -1209,7 +1683,7 @@ static int hclge_dbg_dump_qos_dscp_map(struct hclge_dev *hdev, char *buf, return ret; } - pos += scnprintf(buf + pos, len - pos, "\nDSCP PRIO TC\n"); + seq_puts(s, "\nDSCP PRIO TC\n"); /* The low 32 dscp setting use bd0, high 32 dscp setting use bd1 */ for (i = 0; i < HNAE3_MAX_DSCP / HCLGE_DSCP_MAP_TC_BD_NUM; i++) { @@ -1227,18 +1701,17 @@ static int hclge_dbg_dump_qos_dscp_map(struct hclge_dev *hdev, char *buf, if (kinfo->dscp_prio[i] == HNAE3_PRIO_ID_INVALID) continue; - pos += scnprintf(buf + pos, len - pos, " %2u %u %u\n", - i, kinfo->dscp_prio[i], dscp_tc[i]); + seq_printf(s, " %2u %u %u\n", i, kinfo->dscp_prio[i], + dscp_tc[i]); } return 0; } -static int hclge_dbg_dump_tx_buf_cfg(struct hclge_dev *hdev, char *buf, int len) +static int hclge_dbg_dump_tx_buf_cfg(struct hclge_dev *hdev, struct seq_file *s) { struct hclge_tx_buff_alloc_cmd *tx_buf_cmd; struct hclge_desc desc; - int pos = 0; int i, ret; hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TX_BUFF_ALLOC, true); @@ -1251,19 +1724,17 @@ static int hclge_dbg_dump_tx_buf_cfg(struct hclge_dev *hdev, char *buf, int len) tx_buf_cmd = (struct hclge_tx_buff_alloc_cmd *)desc.data; for (i = 0; i < HCLGE_MAX_TC_NUM; i++) - pos += scnprintf(buf + pos, len - pos, - "tx_packet_buf_tc_%d: 0x%x\n", i, - le16_to_cpu(tx_buf_cmd->tx_pkt_buff[i])); + seq_printf(s, "tx_packet_buf_tc_%d: 0x%x\n", i, + le16_to_cpu(tx_buf_cmd->tx_pkt_buff[i])); - return pos; + return 0; } -static int hclge_dbg_dump_rx_priv_buf_cfg(struct hclge_dev *hdev, char *buf, - int len) +static int hclge_dbg_dump_rx_priv_buf_cfg(struct hclge_dev *hdev, + struct seq_file *s) { struct hclge_rx_priv_buff_cmd *rx_buf_cmd; struct hclge_desc desc; - int pos = 0; int i, ret; hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_PRIV_BUFF_ALLOC, true); @@ -1274,26 +1745,24 @@ static int hclge_dbg_dump_rx_priv_buf_cfg(struct hclge_dev *hdev, char *buf, return ret; } - pos += scnprintf(buf + pos, len - pos, "\n"); + seq_puts(s, "\n"); rx_buf_cmd = (struct hclge_rx_priv_buff_cmd *)desc.data; for (i = 0; i < HCLGE_MAX_TC_NUM; i++) - pos += scnprintf(buf + pos, len - pos, - "rx_packet_buf_tc_%d: 0x%x\n", i, - le16_to_cpu(rx_buf_cmd->buf_num[i])); + seq_printf(s, "rx_packet_buf_tc_%d: 0x%x\n", i, + le16_to_cpu(rx_buf_cmd->buf_num[i])); - pos += scnprintf(buf + pos, len - pos, "rx_share_buf: 0x%x\n", - le16_to_cpu(rx_buf_cmd->shared_buf)); + seq_printf(s, "rx_share_buf: 0x%x\n", + le16_to_cpu(rx_buf_cmd->shared_buf)); - return pos; + return 0; } -static int hclge_dbg_dump_rx_common_wl_cfg(struct hclge_dev *hdev, char *buf, - int len) +static int hclge_dbg_dump_rx_common_wl_cfg(struct hclge_dev *hdev, + struct seq_file *s) { struct hclge_rx_com_wl *rx_com_wl; struct hclge_desc desc; - int pos = 0; int ret; hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_COM_WL_ALLOC, true); @@ -1305,21 +1774,19 @@ static int hclge_dbg_dump_rx_common_wl_cfg(struct hclge_dev *hdev, char *buf, } rx_com_wl = (struct hclge_rx_com_wl *)desc.data; - pos += scnprintf(buf + pos, len - pos, "\n"); - pos += scnprintf(buf + pos, len - pos, - "rx_com_wl: high: 0x%x, low: 0x%x\n", - le16_to_cpu(rx_com_wl->com_wl.high), - le16_to_cpu(rx_com_wl->com_wl.low)); + seq_puts(s, "\n"); + seq_printf(s, "rx_com_wl: high: 0x%x, low: 0x%x\n", + le16_to_cpu(rx_com_wl->com_wl.high), + le16_to_cpu(rx_com_wl->com_wl.low)); - return pos; + return 0; } -static int hclge_dbg_dump_rx_global_pkt_cnt(struct hclge_dev *hdev, char *buf, - int len) +static int hclge_dbg_dump_rx_global_pkt_cnt(struct hclge_dev *hdev, + struct seq_file *s) { struct hclge_rx_com_wl *rx_packet_cnt; struct hclge_desc desc; - int pos = 0; int ret; hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_GBL_PKT_CNT, true); @@ -1331,20 +1798,18 @@ static int hclge_dbg_dump_rx_global_pkt_cnt(struct hclge_dev *hdev, char *buf, } rx_packet_cnt = (struct hclge_rx_com_wl *)desc.data; - pos += scnprintf(buf + pos, len - pos, - "rx_global_packet_cnt: high: 0x%x, low: 0x%x\n", - le16_to_cpu(rx_packet_cnt->com_wl.high), - le16_to_cpu(rx_packet_cnt->com_wl.low)); + seq_printf(s, "rx_global_packet_cnt: high: 0x%x, low: 0x%x\n", + le16_to_cpu(rx_packet_cnt->com_wl.high), + le16_to_cpu(rx_packet_cnt->com_wl.low)); - return pos; + return 0; } -static int hclge_dbg_dump_rx_priv_wl_buf_cfg(struct hclge_dev *hdev, char *buf, - int len) +static int hclge_dbg_dump_rx_priv_wl_buf_cfg(struct hclge_dev *hdev, + struct seq_file *s) { struct hclge_rx_priv_wl_buf *rx_priv_wl; struct hclge_desc desc[2]; - int pos = 0; int i, ret; hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_RX_PRIV_WL_ALLOC, true); @@ -1359,28 +1824,25 @@ static int hclge_dbg_dump_rx_priv_wl_buf_cfg(struct hclge_dev *hdev, char *buf, rx_priv_wl = (struct hclge_rx_priv_wl_buf *)desc[0].data; for (i = 0; i < HCLGE_TC_NUM_ONE_DESC; i++) - pos += scnprintf(buf + pos, len - pos, - "rx_priv_wl_tc_%d: high: 0x%x, low: 0x%x\n", i, - le16_to_cpu(rx_priv_wl->tc_wl[i].high), - le16_to_cpu(rx_priv_wl->tc_wl[i].low)); + seq_printf(s, "rx_priv_wl_tc_%d: high: 0x%x, low: 0x%x\n", i, + le16_to_cpu(rx_priv_wl->tc_wl[i].high), + le16_to_cpu(rx_priv_wl->tc_wl[i].low)); rx_priv_wl = (struct hclge_rx_priv_wl_buf *)desc[1].data; for (i = 0; i < HCLGE_TC_NUM_ONE_DESC; i++) - pos += scnprintf(buf + pos, len - pos, - "rx_priv_wl_tc_%d: high: 0x%x, low: 0x%x\n", - i + HCLGE_TC_NUM_ONE_DESC, - le16_to_cpu(rx_priv_wl->tc_wl[i].high), - le16_to_cpu(rx_priv_wl->tc_wl[i].low)); + seq_printf(s, "rx_priv_wl_tc_%d: high: 0x%x, low: 0x%x\n", + i + HCLGE_TC_NUM_ONE_DESC, + le16_to_cpu(rx_priv_wl->tc_wl[i].high), + le16_to_cpu(rx_priv_wl->tc_wl[i].low)); - return pos; + return 0; } static int hclge_dbg_dump_rx_common_threshold_cfg(struct hclge_dev *hdev, - char *buf, int len) + struct seq_file *s) { struct hclge_rx_com_thrd *rx_com_thrd; struct hclge_desc desc[2]; - int pos = 0; int i, ret; hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_RX_COM_THRD_ALLOC, true); @@ -1393,86 +1855,75 @@ static int hclge_dbg_dump_rx_common_threshold_cfg(struct hclge_dev *hdev, return ret; } - pos += scnprintf(buf + pos, len - pos, "\n"); + seq_puts(s, "\n"); rx_com_thrd = (struct hclge_rx_com_thrd *)desc[0].data; for (i = 0; i < HCLGE_TC_NUM_ONE_DESC; i++) - pos += scnprintf(buf + pos, len - pos, - "rx_com_thrd_tc_%d: high: 0x%x, low: 0x%x\n", i, - le16_to_cpu(rx_com_thrd->com_thrd[i].high), - le16_to_cpu(rx_com_thrd->com_thrd[i].low)); + seq_printf(s, "rx_com_thrd_tc_%d: high: 0x%x, low: 0x%x\n", i, + le16_to_cpu(rx_com_thrd->com_thrd[i].high), + le16_to_cpu(rx_com_thrd->com_thrd[i].low)); rx_com_thrd = (struct hclge_rx_com_thrd *)desc[1].data; for (i = 0; i < HCLGE_TC_NUM_ONE_DESC; i++) - pos += scnprintf(buf + pos, len - pos, - "rx_com_thrd_tc_%d: high: 0x%x, low: 0x%x\n", - i + HCLGE_TC_NUM_ONE_DESC, - le16_to_cpu(rx_com_thrd->com_thrd[i].high), - le16_to_cpu(rx_com_thrd->com_thrd[i].low)); + seq_printf(s, "rx_com_thrd_tc_%d: high: 0x%x, low: 0x%x\n", + i + HCLGE_TC_NUM_ONE_DESC, + le16_to_cpu(rx_com_thrd->com_thrd[i].high), + le16_to_cpu(rx_com_thrd->com_thrd[i].low)); - return pos; + return 0; } -static int hclge_dbg_dump_qos_buf_cfg(struct hclge_dev *hdev, char *buf, - int len) +static int hclge_dbg_dump_qos_buf_cfg(struct seq_file *s, void *data) { - int pos = 0; + struct hclge_dev *hdev = hclge_seq_file_to_hdev(s); int ret; - ret = hclge_dbg_dump_tx_buf_cfg(hdev, buf + pos, len - pos); + ret = hclge_dbg_dump_tx_buf_cfg(hdev, s); if (ret < 0) return ret; - pos += ret; - ret = hclge_dbg_dump_rx_priv_buf_cfg(hdev, buf + pos, len - pos); + ret = hclge_dbg_dump_rx_priv_buf_cfg(hdev, s); if (ret < 0) return ret; - pos += ret; - ret = hclge_dbg_dump_rx_common_wl_cfg(hdev, buf + pos, len - pos); + ret = hclge_dbg_dump_rx_common_wl_cfg(hdev, s); if (ret < 0) return ret; - pos += ret; - ret = hclge_dbg_dump_rx_global_pkt_cnt(hdev, buf + pos, len - pos); + ret = hclge_dbg_dump_rx_global_pkt_cnt(hdev, s); if (ret < 0) return ret; - pos += ret; - pos += scnprintf(buf + pos, len - pos, "\n"); + seq_puts(s, "\n"); if (!hnae3_dev_dcb_supported(hdev)) return 0; - ret = hclge_dbg_dump_rx_priv_wl_buf_cfg(hdev, buf + pos, len - pos); + ret = hclge_dbg_dump_rx_priv_wl_buf_cfg(hdev, s); if (ret < 0) return ret; - pos += ret; - ret = hclge_dbg_dump_rx_common_threshold_cfg(hdev, buf + pos, - len - pos); + ret = hclge_dbg_dump_rx_common_threshold_cfg(hdev, s); if (ret < 0) return ret; return 0; } -static int hclge_dbg_dump_mng_table(struct hclge_dev *hdev, char *buf, int len) +static int hclge_dbg_dump_mng_table(struct seq_file *s, void *data) { + struct hclge_dev *hdev = hclge_seq_file_to_hdev(s); struct hclge_mac_ethertype_idx_rd_cmd *req0; struct hclge_desc desc; u32 msg_egress_port; - int pos = 0; int ret, i; - pos += scnprintf(buf + pos, len - pos, - "entry mac_addr mask ether "); - pos += scnprintf(buf + pos, len - pos, - "mask vlan mask i_map i_dir e_type "); - pos += scnprintf(buf + pos, len - pos, "pf_id vf_id q_id drop\n"); + seq_puts(s, "entry mac_addr mask ether "); + seq_puts(s, "mask vlan mask i_map i_dir e_type "); + seq_puts(s, "pf_id vf_id q_id drop\n"); for (i = 0; i < HCLGE_DBG_MNG_TBL_MAX; i++) { hclge_cmd_setup_basic_desc(&desc, HCLGE_MAC_ETHERTYPE_IDX_RD, true); - req0 = (struct hclge_mac_ethertype_idx_rd_cmd *)&desc.data; + req0 = (struct hclge_mac_ethertype_idx_rd_cmd *)desc.data; req0->index = cpu_to_le16(i); ret = hclge_cmd_send(&hdev->hw, &desc, 1); @@ -1485,46 +1936,40 @@ static int hclge_dbg_dump_mng_table(struct hclge_dev *hdev, char *buf, int len) if (!req0->resp_code) continue; - pos += scnprintf(buf + pos, len - pos, "%02u %pM ", - le16_to_cpu(req0->index), req0->mac_addr); + seq_printf(s, "%02u %pM ", + le16_to_cpu(req0->index), req0->mac_addr); - pos += scnprintf(buf + pos, len - pos, - "%x %04x %x %04x ", - !!(req0->flags & HCLGE_DBG_MNG_MAC_MASK_B), - le16_to_cpu(req0->ethter_type), - !!(req0->flags & HCLGE_DBG_MNG_ETHER_MASK_B), - le16_to_cpu(req0->vlan_tag) & - HCLGE_DBG_MNG_VLAN_TAG); + seq_printf(s, "%x %04x %x %04x ", + !!(req0->flags & HCLGE_DBG_MNG_MAC_MASK_B), + le16_to_cpu(req0->ethter_type), + !!(req0->flags & HCLGE_DBG_MNG_ETHER_MASK_B), + le16_to_cpu(req0->vlan_tag) & + HCLGE_DBG_MNG_VLAN_TAG); - pos += scnprintf(buf + pos, len - pos, - "%x %02x %02x ", - !!(req0->flags & HCLGE_DBG_MNG_VLAN_MASK_B), - req0->i_port_bitmap, req0->i_port_direction); + seq_printf(s, "%x %02x %02x ", + !!(req0->flags & HCLGE_DBG_MNG_VLAN_MASK_B), + req0->i_port_bitmap, req0->i_port_direction); msg_egress_port = le16_to_cpu(req0->egress_port); - pos += scnprintf(buf + pos, len - pos, - "%x %x %02x %04x %x\n", - !!(msg_egress_port & HCLGE_DBG_MNG_E_TYPE_B), - msg_egress_port & HCLGE_DBG_MNG_PF_ID, - (msg_egress_port >> 3) & HCLGE_DBG_MNG_VF_ID, - le16_to_cpu(req0->egress_queue), - !!(msg_egress_port & HCLGE_DBG_MNG_DROP_B)); + seq_printf(s, "%x %x %02x %04x %x\n", + !!(msg_egress_port & HCLGE_DBG_MNG_E_TYPE_B), + msg_egress_port & HCLGE_DBG_MNG_PF_ID, + (msg_egress_port >> 3) & HCLGE_DBG_MNG_VF_ID, + le16_to_cpu(req0->egress_queue), + !!(msg_egress_port & HCLGE_DBG_MNG_DROP_B)); } return 0; } -#define HCLGE_DBG_TCAM_BUF_SIZE 256 - static int hclge_dbg_fd_tcam_read(struct hclge_dev *hdev, bool sel_x, - char *tcam_buf, + struct seq_file *s, struct hclge_dbg_tcam_msg tcam_msg) { struct hclge_fd_tcam_config_1_cmd *req1; struct hclge_fd_tcam_config_2_cmd *req2; struct hclge_fd_tcam_config_3_cmd *req3; struct hclge_desc desc[3]; - int pos = 0; int ret, i; __le32 *req; @@ -1546,27 +1991,23 @@ static int hclge_dbg_fd_tcam_read(struct hclge_dev *hdev, bool sel_x, if (ret) return ret; - pos += scnprintf(tcam_buf + pos, HCLGE_DBG_TCAM_BUF_SIZE - pos, - "read result tcam key %s(%u):\n", sel_x ? "x" : "y", - tcam_msg.loc); + seq_printf(s, "read result tcam key %s(%u):\n", + sel_x ? "x" : "y", tcam_msg.loc); /* tcam_data0 ~ tcam_data1 */ req = (__le32 *)req1->tcam_data; for (i = 0; i < 2; i++) - pos += scnprintf(tcam_buf + pos, HCLGE_DBG_TCAM_BUF_SIZE - pos, - "%08x\n", le32_to_cpu(*req++)); + seq_printf(s, "%08x\n", le32_to_cpu(*req++)); /* tcam_data2 ~ tcam_data7 */ req = (__le32 *)req2->tcam_data; for (i = 0; i < 6; i++) - pos += scnprintf(tcam_buf + pos, HCLGE_DBG_TCAM_BUF_SIZE - pos, - "%08x\n", le32_to_cpu(*req++)); + seq_printf(s, "%08x\n", le32_to_cpu(*req++)); /* tcam_data8 ~ tcam_data12 */ req = (__le32 *)req3->tcam_data; for (i = 0; i < 5; i++) - pos += scnprintf(tcam_buf + pos, HCLGE_DBG_TCAM_BUF_SIZE - pos, - "%08x\n", le32_to_cpu(*req++)); + seq_printf(s, "%08x\n", le32_to_cpu(*req++)); return ret; } @@ -1590,14 +2031,13 @@ static int hclge_dbg_get_rules_location(struct hclge_dev *hdev, u16 *rule_locs) return cnt; } -static int hclge_dbg_dump_fd_tcam(struct hclge_dev *hdev, char *buf, int len) +static int hclge_dbg_dump_fd_tcam(struct seq_file *s, void *data) { - u32 rule_num = hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]; + struct hclge_dev *hdev = hclge_seq_file_to_hdev(s); struct hclge_dbg_tcam_msg tcam_msg; int i, ret, rule_cnt; u16 *rule_locs; - char *tcam_buf; - int pos = 0; + u32 rule_num; if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) { dev_err(&hdev->pdev->dev, @@ -1605,6 +2045,7 @@ static int hclge_dbg_dump_fd_tcam(struct hclge_dev *hdev, char *buf, int len) return -EOPNOTSUPP; } + rule_num = hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]; if (!hdev->hclge_fd_rule_num || !rule_num) return 0; @@ -1612,12 +2053,6 @@ static int hclge_dbg_dump_fd_tcam(struct hclge_dev *hdev, char *buf, int len) if (!rule_locs) return -ENOMEM; - tcam_buf = kzalloc(HCLGE_DBG_TCAM_BUF_SIZE, GFP_KERNEL); - if (!tcam_buf) { - kfree(rule_locs); - return -ENOMEM; - } - rule_cnt = hclge_dbg_get_rules_location(hdev, rule_locs); if (rule_cnt < 0) { ret = rule_cnt; @@ -1631,38 +2066,34 @@ static int hclge_dbg_dump_fd_tcam(struct hclge_dev *hdev, char *buf, int len) tcam_msg.stage = HCLGE_FD_STAGE_1; tcam_msg.loc = rule_locs[i]; - ret = hclge_dbg_fd_tcam_read(hdev, true, tcam_buf, tcam_msg); + ret = hclge_dbg_fd_tcam_read(hdev, true, s, tcam_msg); if (ret) { dev_err(&hdev->pdev->dev, "failed to get fd tcam key x, ret = %d\n", ret); goto out; } - pos += scnprintf(buf + pos, len - pos, "%s", tcam_buf); - - ret = hclge_dbg_fd_tcam_read(hdev, false, tcam_buf, tcam_msg); + ret = hclge_dbg_fd_tcam_read(hdev, false, s, tcam_msg); if (ret) { dev_err(&hdev->pdev->dev, "failed to get fd tcam key y, ret = %d\n", ret); goto out; } - pos += scnprintf(buf + pos, len - pos, "%s", tcam_buf); } out: - kfree(tcam_buf); kfree(rule_locs); return ret; } -static int hclge_dbg_dump_fd_counter(struct hclge_dev *hdev, char *buf, int len) +static int hclge_dbg_dump_fd_counter(struct seq_file *s, void *data) { + struct hclge_dev *hdev = hclge_seq_file_to_hdev(s); u8 func_num = pci_num_vf(hdev->pdev) + 1; /* pf and enabled vf num */ struct hclge_fd_ad_cnt_read_cmd *req; char str_id[HCLGE_DBG_ID_LEN]; struct hclge_desc desc; - int pos = 0; int ret; u64 cnt; u8 i; @@ -1670,8 +2101,7 @@ static int hclge_dbg_dump_fd_counter(struct hclge_dev *hdev, char *buf, int len) if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) return -EOPNOTSUPP; - pos += scnprintf(buf + pos, len - pos, - "func_id\thit_times\n"); + seq_puts(s, "func_id\thit_times\n"); for (i = 0; i < func_num; i++) { hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_CNT_OP, true); @@ -1685,8 +2115,7 @@ static int hclge_dbg_dump_fd_counter(struct hclge_dev *hdev, char *buf, int len) } cnt = le64_to_cpu(req->cnt); hclge_dbg_get_func_id_str(str_id, i); - pos += scnprintf(buf + pos, len - pos, - "%s\t%llu\n", str_id, cnt); + seq_printf(s, "%s\t%llu\n", str_id, cnt); } return 0; @@ -1737,74 +2166,95 @@ int hclge_dbg_dump_rst_info(struct hclge_dev *hdev, char *buf, int len) return 0; } -static int hclge_dbg_dump_serv_info(struct hclge_dev *hdev, char *buf, int len) +static int hclge_dbg_seq_dump_rst_info(struct seq_file *s, void *data) { + struct hclge_dev *hdev = hclge_seq_file_to_hdev(s); + u32 i, offset; + + seq_printf(s, "PF reset count: %u\n", hdev->rst_stats.pf_rst_cnt); + seq_printf(s, "FLR reset count: %u\n", hdev->rst_stats.flr_rst_cnt); + seq_printf(s, "GLOBAL reset count: %u\n", + hdev->rst_stats.global_rst_cnt); + seq_printf(s, "IMP reset count: %u\n", hdev->rst_stats.imp_rst_cnt); + seq_printf(s, "reset done count: %u\n", hdev->rst_stats.reset_done_cnt); + seq_printf(s, "HW reset done count: %u\n", + hdev->rst_stats.hw_reset_done_cnt); + seq_printf(s, "reset count: %u\n", hdev->rst_stats.reset_cnt); + seq_printf(s, "reset fail count: %u\n", hdev->rst_stats.reset_fail_cnt); + + for (i = 0; i < ARRAY_SIZE(hclge_dbg_rst_info); i++) { + offset = hclge_dbg_rst_info[i].offset; + seq_printf(s, "%s: 0x%x\n", + hclge_dbg_rst_info[i].message, + hclge_read_dev(&hdev->hw, offset)); + } + + seq_printf(s, "hdev state: 0x%lx\n", hdev->state); + + return 0; +} + +static int hclge_dbg_dump_serv_info(struct seq_file *s, void *data) +{ + struct hclge_dev *hdev = hclge_seq_file_to_hdev(s); unsigned long rem_nsec; - int pos = 0; u64 lc; lc = local_clock(); rem_nsec = do_div(lc, HCLGE_BILLION_NANO_SECONDS); - pos += scnprintf(buf + pos, len - pos, "local_clock: [%5lu.%06lu]\n", - (unsigned long)lc, rem_nsec / 1000); - pos += scnprintf(buf + pos, len - pos, "delta: %u(ms)\n", - jiffies_to_msecs(jiffies - hdev->last_serv_processed)); - pos += scnprintf(buf + pos, len - pos, - "last_service_task_processed: %lu(jiffies)\n", - hdev->last_serv_processed); - pos += scnprintf(buf + pos, len - pos, "last_service_task_cnt: %lu\n", - hdev->serv_processed_cnt); + seq_printf(s, "local_clock: [%5lu.%06lu]\n", + (unsigned long)lc, rem_nsec / 1000); + seq_printf(s, "delta: %u(ms)\n", + jiffies_to_msecs(jiffies - hdev->last_serv_processed)); + seq_printf(s, "last_service_task_processed: %lu(jiffies)\n", + hdev->last_serv_processed); + seq_printf(s, "last_service_task_cnt: %lu\n", hdev->serv_processed_cnt); return 0; } -static int hclge_dbg_dump_interrupt(struct hclge_dev *hdev, char *buf, int len) +static int hclge_dbg_dump_interrupt(struct seq_file *s, void *data) { - int pos = 0; + struct hclge_dev *hdev = hclge_seq_file_to_hdev(s); - pos += scnprintf(buf + pos, len - pos, "num_nic_msi: %u\n", - hdev->num_nic_msi); - pos += scnprintf(buf + pos, len - pos, "num_roce_msi: %u\n", - hdev->num_roce_msi); - pos += scnprintf(buf + pos, len - pos, "num_msi_used: %u\n", - hdev->num_msi_used); - pos += scnprintf(buf + pos, len - pos, "num_msi_left: %u\n", - hdev->num_msi_left); + seq_printf(s, "num_nic_msi: %u\n", hdev->num_nic_msi); + seq_printf(s, "num_roce_msi: %u\n", hdev->num_roce_msi); + seq_printf(s, "num_msi_used: %u\n", hdev->num_msi_used); + seq_printf(s, "num_msi_left: %u\n", hdev->num_msi_left); return 0; } -static void hclge_dbg_imp_info_data_print(struct hclge_desc *desc_src, - char *buf, int len, u32 bd_num) +static void hclge_dbg_imp_info_data_print(struct seq_file *s, + struct hclge_desc *desc_src, + u32 bd_num) { #define HCLGE_DBG_IMP_INFO_PRINT_OFFSET 0x2 struct hclge_desc *desc_index = desc_src; u32 offset = 0; - int pos = 0; u32 i, j; - pos += scnprintf(buf + pos, len - pos, "offset | data\n"); + seq_puts(s, "offset | data\n"); for (i = 0; i < bd_num; i++) { j = 0; while (j < HCLGE_DESC_DATA_LEN - 1) { - pos += scnprintf(buf + pos, len - pos, "0x%04x | ", - offset); - pos += scnprintf(buf + pos, len - pos, "0x%08x ", - le32_to_cpu(desc_index->data[j++])); - pos += scnprintf(buf + pos, len - pos, "0x%08x\n", - le32_to_cpu(desc_index->data[j++])); + seq_printf(s, "0x%04x | ", offset); + seq_printf(s, "0x%08x ", + le32_to_cpu(desc_index->data[j++])); + seq_printf(s, "0x%08x\n", + le32_to_cpu(desc_index->data[j++])); offset += sizeof(u32) * HCLGE_DBG_IMP_INFO_PRINT_OFFSET; } desc_index++; } } -static int -hclge_dbg_get_imp_stats_info(struct hclge_dev *hdev, char *buf, int len) +static int hclge_dbg_get_imp_stats_info(struct seq_file *s, void *data) { + struct hclge_dev *hdev = hclge_seq_file_to_hdev(s); struct hclge_get_imp_bd_cmd *req; struct hclge_desc *desc_src; struct hclge_desc desc; @@ -1841,7 +2291,7 @@ hclge_dbg_get_imp_stats_info(struct hclge_dev *hdev, char *buf, int len) return ret; } - hclge_dbg_imp_info_data_print(desc_src, buf, len, bd_num); + hclge_dbg_imp_info_data_print(s, desc_src, bd_num); kfree(desc_src); @@ -1852,7 +2302,7 @@ hclge_dbg_get_imp_stats_info(struct hclge_dev *hdev, char *buf, int len) #define HCLGE_MAX_NCL_CONFIG_LENGTH 16384 static void hclge_ncl_config_data_print(struct hclge_desc *desc, int *index, - char *buf, int len, int *pos) + struct seq_file *s) { #define HCLGE_CMD_DATA_NUM 6 @@ -1864,9 +2314,8 @@ static void hclge_ncl_config_data_print(struct hclge_desc *desc, int *index, if (i == 0 && j == 0) continue; - *pos += scnprintf(buf + *pos, len - *pos, - "0x%04x | 0x%08x\n", offset, - le32_to_cpu(desc[i].data[j])); + seq_printf(s, "0x%04x | 0x%08x\n", offset, + le32_to_cpu(desc[i].data[j])); offset += sizeof(u32); *index -= sizeof(u32); @@ -1877,19 +2326,18 @@ static void hclge_ncl_config_data_print(struct hclge_desc *desc, int *index, } } -static int -hclge_dbg_dump_ncl_config(struct hclge_dev *hdev, char *buf, int len) +static int hclge_dbg_dump_ncl_config(struct seq_file *s, void *data) { #define HCLGE_NCL_CONFIG_LENGTH_IN_EACH_CMD (20 + 24 * 4) struct hclge_desc desc[HCLGE_CMD_NCL_CONFIG_BD_NUM]; + struct hclge_dev *hdev = hclge_seq_file_to_hdev(s); int bd_num = HCLGE_CMD_NCL_CONFIG_BD_NUM; int index = HCLGE_MAX_NCL_CONFIG_LENGTH; - int pos = 0; u32 data0; int ret; - pos += scnprintf(buf + pos, len - pos, "offset | data\n"); + seq_puts(s, "offset | data\n"); while (index > 0) { data0 = HCLGE_MAX_NCL_CONFIG_LENGTH - index; @@ -1902,27 +2350,26 @@ hclge_dbg_dump_ncl_config(struct hclge_dev *hdev, char *buf, int len) if (ret) return ret; - hclge_ncl_config_data_print(desc, &index, buf, len, &pos); + hclge_ncl_config_data_print(desc, &index, s); } return 0; } -static int hclge_dbg_dump_loopback(struct hclge_dev *hdev, char *buf, int len) +static int hclge_dbg_dump_loopback(struct seq_file *s, void *data) { + struct hclge_dev *hdev = hclge_seq_file_to_hdev(s); struct phy_device *phydev = hdev->hw.mac.phydev; struct hclge_config_mac_mode_cmd *req_app; struct hclge_common_lb_cmd *req_common; struct hclge_desc desc; u8 loopback_en; - int pos = 0; int ret; req_app = (struct hclge_config_mac_mode_cmd *)desc.data; req_common = (struct hclge_common_lb_cmd *)desc.data; - pos += scnprintf(buf + pos, len - pos, "mac id: %u\n", - hdev->hw.mac.mac_id); + seq_printf(s, "mac id: %u\n", hdev->hw.mac.mac_id); hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, true); ret = hclge_cmd_send(&hdev->hw, &desc, 1); @@ -1934,8 +2381,7 @@ static int hclge_dbg_dump_loopback(struct hclge_dev *hdev, char *buf, int len) loopback_en = hnae3_get_bit(le32_to_cpu(req_app->txrx_pad_fcs_loop_en), HCLGE_MAC_APP_LP_B); - pos += scnprintf(buf + pos, len - pos, "app loopback: %s\n", - state_str[loopback_en]); + seq_printf(s, "app loopback: %s\n", str_on_off(loopback_en)); hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_COMMON_LOOPBACK, true); ret = hclge_cmd_send(&hdev->hw, &desc, 1); @@ -1946,24 +2392,22 @@ static int hclge_dbg_dump_loopback(struct hclge_dev *hdev, char *buf, int len) return ret; } - loopback_en = req_common->enable & HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B; - pos += scnprintf(buf + pos, len - pos, "serdes serial loopback: %s\n", - state_str[loopback_en]); + loopback_en = req_common->enable & + HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B; + seq_printf(s, "serdes serial loopback: %s\n", str_on_off(loopback_en)); loopback_en = req_common->enable & - HCLGE_CMD_SERDES_PARALLEL_INNER_LOOP_B ? 1 : 0; - pos += scnprintf(buf + pos, len - pos, "serdes parallel loopback: %s\n", - state_str[loopback_en]); + HCLGE_CMD_SERDES_PARALLEL_INNER_LOOP_B ? 1 : 0; + seq_printf(s, "serdes parallel loopback: %s\n", + str_on_off(loopback_en)); if (phydev) { loopback_en = phydev->loopback_enabled; - pos += scnprintf(buf + pos, len - pos, "phy loopback: %s\n", - state_str[loopback_en]); + seq_printf(s, "phy loopback: %s\n", str_on_off(loopback_en)); } else if (hnae3_dev_phy_imp_supported(hdev)) { loopback_en = req_common->enable & HCLGE_CMD_GE_PHY_INNER_LOOP_B; - pos += scnprintf(buf + pos, len - pos, "phy loopback: %s\n", - state_str[loopback_en]); + seq_printf(s, "phy loopback: %s\n", str_on_off(loopback_en)); } return 0; @@ -1972,107 +2416,75 @@ static int hclge_dbg_dump_loopback(struct hclge_dev *hdev, char *buf, int len) /* hclge_dbg_dump_mac_tnl_status: print message about mac tnl interrupt * @hdev: pointer to struct hclge_dev */ -static int -hclge_dbg_dump_mac_tnl_status(struct hclge_dev *hdev, char *buf, int len) +static int hclge_dbg_dump_mac_tnl_status(struct seq_file *s, void *data) { + struct hclge_dev *hdev = hclge_seq_file_to_hdev(s); struct hclge_mac_tnl_stats stats; unsigned long rem_nsec; - int pos = 0; - pos += scnprintf(buf + pos, len - pos, - "Recently generated mac tnl interruption:\n"); + seq_puts(s, "Recently generated mac tnl interruption:\n"); while (kfifo_get(&hdev->mac_tnl_log, &stats)) { rem_nsec = do_div(stats.time, HCLGE_BILLION_NANO_SECONDS); - pos += scnprintf(buf + pos, len - pos, - "[%07lu.%03lu] status = 0x%x\n", - (unsigned long)stats.time, rem_nsec / 1000, - stats.status); + seq_printf(s, "[%07lu.%03lu] status = 0x%x\n", + (unsigned long)stats.time, rem_nsec / 1000, + stats.status); } return 0; } - -static const struct hclge_dbg_item mac_list_items[] = { - { "FUNC_ID", 2 }, - { "MAC_ADDR", 12 }, - { "STATE", 2 }, -}; - -static void hclge_dbg_dump_mac_list(struct hclge_dev *hdev, char *buf, int len, - bool is_unicast) +static void hclge_dbg_dump_mac_list(struct seq_file *s, bool is_unicast) { - char data_str[ARRAY_SIZE(mac_list_items)][HCLGE_DBG_DATA_STR_LEN]; - char content[HCLGE_DBG_INFO_LEN], str_id[HCLGE_DBG_ID_LEN]; - char *result[ARRAY_SIZE(mac_list_items)]; + struct hclge_dev *hdev = hclge_seq_file_to_hdev(s); struct hclge_mac_node *mac_node, *tmp; struct hclge_vport *vport; struct list_head *list; u32 func_id; - int pos = 0; - int i; - for (i = 0; i < ARRAY_SIZE(mac_list_items); i++) - result[i] = &data_str[i][0]; - - pos += scnprintf(buf + pos, len - pos, "%s MAC_LIST:\n", - is_unicast ? "UC" : "MC"); - hclge_dbg_fill_content(content, sizeof(content), mac_list_items, - NULL, ARRAY_SIZE(mac_list_items)); - pos += scnprintf(buf + pos, len - pos, "%s", content); + seq_printf(s, "%s MAC_LIST:\n", is_unicast ? "UC" : "MC"); + seq_puts(s, "FUNC_ID MAC_ADDR STATE\n"); for (func_id = 0; func_id < hdev->num_alloc_vport; func_id++) { vport = &hdev->vport[func_id]; list = is_unicast ? &vport->uc_mac_list : &vport->mc_mac_list; spin_lock_bh(&vport->mac_list_lock); list_for_each_entry_safe(mac_node, tmp, list, node) { - i = 0; - result[i++] = hclge_dbg_get_func_id_str(str_id, - func_id); - sprintf(result[i++], "%pM", mac_node->mac_addr); - sprintf(result[i++], "%5s", - hclge_mac_state_str[mac_node->state]); - hclge_dbg_fill_content(content, sizeof(content), - mac_list_items, - (const char **)result, - ARRAY_SIZE(mac_list_items)); - pos += scnprintf(buf + pos, len - pos, "%s", content); + if (func_id) + seq_printf(s, "vf%-7u", func_id - 1U); + else + seq_puts(s, "pf "); + seq_printf(s, "%pM ", mac_node->mac_addr); + seq_printf(s, "%5s\n", + hclge_mac_state_str[mac_node->state]); } spin_unlock_bh(&vport->mac_list_lock); } } -static int hclge_dbg_dump_umv_info(struct hclge_dev *hdev, char *buf, int len) +static int hclge_dbg_dump_umv_info(struct seq_file *s, void *data) { + struct hclge_dev *hdev = hclge_seq_file_to_hdev(s); u8 func_num = pci_num_vf(hdev->pdev) + 1; struct hclge_vport *vport; - int pos = 0; u8 i; - pos += scnprintf(buf, len, "num_alloc_vport : %u\n", - hdev->num_alloc_vport); - pos += scnprintf(buf + pos, len - pos, "max_umv_size : %u\n", - hdev->max_umv_size); - pos += scnprintf(buf + pos, len - pos, "wanted_umv_size : %u\n", - hdev->wanted_umv_size); - pos += scnprintf(buf + pos, len - pos, "priv_umv_size : %u\n", - hdev->priv_umv_size); + seq_printf(s, "num_alloc_vport : %u\n", hdev->num_alloc_vport); + seq_printf(s, "max_umv_size : %u\n", hdev->max_umv_size); + seq_printf(s, "wanted_umv_size : %u\n", hdev->wanted_umv_size); + seq_printf(s, "priv_umv_size : %u\n", hdev->priv_umv_size); mutex_lock(&hdev->vport_lock); - pos += scnprintf(buf + pos, len - pos, "share_umv_size : %u\n", - hdev->share_umv_size); + seq_printf(s, "share_umv_size : %u\n", hdev->share_umv_size); for (i = 0; i < func_num; i++) { vport = &hdev->vport[i]; - pos += scnprintf(buf + pos, len - pos, - "vport(%u) used_umv_num : %u\n", - i, vport->used_umv_num); + seq_printf(s, "vport(%u) used_umv_num : %u\n", + i, vport->used_umv_num); } mutex_unlock(&hdev->vport_lock); - pos += scnprintf(buf + pos, len - pos, "used_mc_mac_num : %u\n", - hdev->used_mc_mac_num); + seq_printf(s, "used_mc_mac_num : %u\n", hdev->used_mc_mac_num); return 0; } @@ -2214,38 +2626,12 @@ static int hclge_get_port_vlan_filter_bypass_state(struct hclge_dev *hdev, return 0; } -static const struct hclge_dbg_item vlan_filter_items[] = { - { "FUNC_ID", 2 }, - { "I_VF_VLAN_FILTER", 2 }, - { "E_VF_VLAN_FILTER", 2 }, - { "PORT_VLAN_FILTER_BYPASS", 0 } -}; - -static const struct hclge_dbg_item vlan_offload_items[] = { - { "FUNC_ID", 2 }, - { "PVID", 4 }, - { "ACCEPT_TAG1", 2 }, - { "ACCEPT_TAG2", 2 }, - { "ACCEPT_UNTAG1", 2 }, - { "ACCEPT_UNTAG2", 2 }, - { "INSERT_TAG1", 2 }, - { "INSERT_TAG2", 2 }, - { "SHIFT_TAG", 2 }, - { "STRIP_TAG1", 2 }, - { "STRIP_TAG2", 2 }, - { "DROP_TAG1", 2 }, - { "DROP_TAG2", 2 }, - { "PRI_ONLY_TAG1", 2 }, - { "PRI_ONLY_TAG2", 0 } -}; - -static int hclge_dbg_dump_vlan_filter_config(struct hclge_dev *hdev, char *buf, - int len, int *pos) +static int hclge_dbg_dump_vlan_filter_config(struct hclge_dev *hdev, + struct seq_file *s) { - char content[HCLGE_DBG_VLAN_FLTR_INFO_LEN], str_id[HCLGE_DBG_ID_LEN]; - const char *result[ARRAY_SIZE(vlan_filter_items)]; - u8 i, j, vlan_fe, bypass, ingress, egress; u8 func_num = pci_num_vf(hdev->pdev) + 1; /* pf and enabled vf num */ + u8 i, vlan_fe, bypass, ingress, egress; + char str_id[HCLGE_DBG_ID_LEN]; int ret; ret = hclge_get_vlan_filter_state(hdev, HCLGE_FILTER_TYPE_PORT, 0, @@ -2255,14 +2641,11 @@ static int hclge_dbg_dump_vlan_filter_config(struct hclge_dev *hdev, char *buf, ingress = vlan_fe & HCLGE_FILTER_FE_NIC_INGRESS_B; egress = vlan_fe & HCLGE_FILTER_FE_NIC_EGRESS_B ? 1 : 0; - *pos += scnprintf(buf, len, "I_PORT_VLAN_FILTER: %s\n", - state_str[ingress]); - *pos += scnprintf(buf + *pos, len - *pos, "E_PORT_VLAN_FILTER: %s\n", - state_str[egress]); + seq_printf(s, "I_PORT_VLAN_FILTER: %s\n", str_on_off(ingress)); + seq_printf(s, "E_PORT_VLAN_FILTER: %s\n", str_on_off(egress)); - hclge_dbg_fill_content(content, sizeof(content), vlan_filter_items, - NULL, ARRAY_SIZE(vlan_filter_items)); - *pos += scnprintf(buf + *pos, len - *pos, "%s", content); + seq_puts(s, "FUNC_ID I_VF_VLAN_FILTER E_VF_VLAN_FILTER "); + seq_puts(s, "PORT_VLAN_FILTER_BYPASS\n"); for (i = 0; i < func_num; i++) { ret = hclge_get_vlan_filter_state(hdev, HCLGE_FILTER_TYPE_VF, i, @@ -2275,37 +2658,32 @@ static int hclge_dbg_dump_vlan_filter_config(struct hclge_dev *hdev, char *buf, ret = hclge_get_port_vlan_filter_bypass_state(hdev, i, &bypass); if (ret) return ret; - j = 0; - result[j++] = hclge_dbg_get_func_id_str(str_id, i); - result[j++] = state_str[ingress]; - result[j++] = state_str[egress]; - result[j++] = - test_bit(HNAE3_DEV_SUPPORT_PORT_VLAN_BYPASS_B, - hdev->ae_dev->caps) ? state_str[bypass] : "NA"; - hclge_dbg_fill_content(content, sizeof(content), - vlan_filter_items, result, - ARRAY_SIZE(vlan_filter_items)); - *pos += scnprintf(buf + *pos, len - *pos, "%s", content); + + seq_printf(s, "%-9s%-18s%-18s%s\n", + hclge_dbg_get_func_id_str(str_id, i), + str_on_off(ingress), str_on_off(egress), + test_bit(HNAE3_DEV_SUPPORT_PORT_VLAN_BYPASS_B, + hdev->ae_dev->caps) ? + str_on_off(bypass) : "NA"); } - *pos += scnprintf(buf + *pos, len - *pos, "\n"); + seq_puts(s, "\n"); return 0; } -static int hclge_dbg_dump_vlan_offload_config(struct hclge_dev *hdev, char *buf, - int len, int *pos) +static int hclge_dbg_dump_vlan_offload_config(struct hclge_dev *hdev, + struct seq_file *s) { - char str_id[HCLGE_DBG_ID_LEN], str_pvid[HCLGE_DBG_ID_LEN]; - const char *result[ARRAY_SIZE(vlan_offload_items)]; - char content[HCLGE_DBG_VLAN_OFFLOAD_INFO_LEN]; u8 func_num = pci_num_vf(hdev->pdev) + 1; /* pf and enabled vf num */ struct hclge_dbg_vlan_cfg vlan_cfg; + char str_id[HCLGE_DBG_ID_LEN]; int ret; - u8 i, j; + u8 i; - hclge_dbg_fill_content(content, sizeof(content), vlan_offload_items, - NULL, ARRAY_SIZE(vlan_offload_items)); - *pos += scnprintf(buf + *pos, len - *pos, "%s", content); + seq_puts(s, "FUNC_ID PVID ACCEPT_TAG1 ACCEPT_TAG2 ACCEPT_UNTAG1 "); + seq_puts(s, "ACCEPT_UNTAG2 INSERT_TAG1 INSERT_TAG2 SHIFT_TAG "); + seq_puts(s, "STRIP_TAG1 STRIP_TAG2 DROP_TAG1 DROP_TAG2 "); + seq_puts(s, "PRI_ONLY_TAG1 PRI_ONLY_TAG2\n"); for (i = 0; i < func_num; i++) { ret = hclge_get_vlan_tx_offload_cfg(hdev, i, &vlan_cfg); @@ -2316,107 +2694,92 @@ static int hclge_dbg_dump_vlan_offload_config(struct hclge_dev *hdev, char *buf, if (ret) return ret; - sprintf(str_pvid, "%u", vlan_cfg.pvid); - j = 0; - result[j++] = hclge_dbg_get_func_id_str(str_id, i); - result[j++] = str_pvid; - result[j++] = state_str[vlan_cfg.accept_tag1]; - result[j++] = state_str[vlan_cfg.accept_tag2]; - result[j++] = state_str[vlan_cfg.accept_untag1]; - result[j++] = state_str[vlan_cfg.accept_untag2]; - result[j++] = state_str[vlan_cfg.insert_tag1]; - result[j++] = state_str[vlan_cfg.insert_tag2]; - result[j++] = state_str[vlan_cfg.shift_tag]; - result[j++] = state_str[vlan_cfg.strip_tag1]; - result[j++] = state_str[vlan_cfg.strip_tag2]; - result[j++] = state_str[vlan_cfg.drop_tag1]; - result[j++] = state_str[vlan_cfg.drop_tag2]; - result[j++] = state_str[vlan_cfg.pri_only1]; - result[j++] = state_str[vlan_cfg.pri_only2]; - - hclge_dbg_fill_content(content, sizeof(content), - vlan_offload_items, result, - ARRAY_SIZE(vlan_offload_items)); - *pos += scnprintf(buf + *pos, len - *pos, "%s", content); + seq_printf(s, "%-9s", hclge_dbg_get_func_id_str(str_id, i)); + seq_printf(s, "%-6u", vlan_cfg.pvid); + seq_printf(s, "%-13s", str_on_off(vlan_cfg.accept_tag1)); + seq_printf(s, "%-12s", str_on_off(vlan_cfg.accept_tag2)); + seq_printf(s, "%-15s", str_on_off(vlan_cfg.accept_untag1)); + seq_printf(s, "%-15s", str_on_off(vlan_cfg.accept_untag2)); + seq_printf(s, "%-13s", str_on_off(vlan_cfg.insert_tag1)); + seq_printf(s, "%-13s", str_on_off(vlan_cfg.insert_tag2)); + seq_printf(s, "%-11s", str_on_off(vlan_cfg.shift_tag)); + seq_printf(s, "%-12s", str_on_off(vlan_cfg.strip_tag1)); + seq_printf(s, "%-12s", str_on_off(vlan_cfg.strip_tag2)); + seq_printf(s, "%-11s", str_on_off(vlan_cfg.drop_tag1)); + seq_printf(s, "%-11s", str_on_off(vlan_cfg.drop_tag2)); + seq_printf(s, "%-15s", str_on_off(vlan_cfg.pri_only1)); + seq_printf(s, "%s\n", str_on_off(vlan_cfg.pri_only2)); } return 0; } -static int hclge_dbg_dump_vlan_config(struct hclge_dev *hdev, char *buf, - int len) +static int hclge_dbg_dump_vlan_config(struct seq_file *s, void *data) { - int pos = 0; + struct hclge_dev *hdev = hclge_seq_file_to_hdev(s); int ret; - ret = hclge_dbg_dump_vlan_filter_config(hdev, buf, len, &pos); + ret = hclge_dbg_dump_vlan_filter_config(hdev, s); if (ret) return ret; - return hclge_dbg_dump_vlan_offload_config(hdev, buf, len, &pos); + return hclge_dbg_dump_vlan_offload_config(hdev, s); } -static int hclge_dbg_dump_ptp_info(struct hclge_dev *hdev, char *buf, int len) +static int hclge_dbg_dump_ptp_info(struct seq_file *s, void *data) { + struct hclge_dev *hdev = hclge_seq_file_to_hdev(s); struct hclge_ptp *ptp = hdev->ptp; u32 sw_cfg = ptp->ptp_cfg; unsigned int tx_start; unsigned int last_rx; - int pos = 0; u32 hw_cfg; int ret; - pos += scnprintf(buf + pos, len - pos, "phc %s's debug info:\n", - ptp->info.name); - pos += scnprintf(buf + pos, len - pos, "ptp enable: %s\n", - test_bit(HCLGE_PTP_FLAG_EN, &ptp->flags) ? - "yes" : "no"); - pos += scnprintf(buf + pos, len - pos, "ptp tx enable: %s\n", - test_bit(HCLGE_PTP_FLAG_TX_EN, &ptp->flags) ? - "yes" : "no"); - pos += scnprintf(buf + pos, len - pos, "ptp rx enable: %s\n", - test_bit(HCLGE_PTP_FLAG_RX_EN, &ptp->flags) ? - "yes" : "no"); + seq_printf(s, "phc %s's debug info:\n", ptp->info.name); + seq_printf(s, "ptp enable: %s\n", + str_yes_no(test_bit(HCLGE_PTP_FLAG_EN, &ptp->flags))); + seq_printf(s, "ptp tx enable: %s\n", + str_yes_no(test_bit(HCLGE_PTP_FLAG_TX_EN, &ptp->flags))); + seq_printf(s, "ptp rx enable: %s\n", + str_yes_no(test_bit(HCLGE_PTP_FLAG_RX_EN, &ptp->flags))); last_rx = jiffies_to_msecs(ptp->last_rx); - pos += scnprintf(buf + pos, len - pos, "last rx time: %lu.%lu\n", - last_rx / MSEC_PER_SEC, last_rx % MSEC_PER_SEC); - pos += scnprintf(buf + pos, len - pos, "rx count: %lu\n", ptp->rx_cnt); + seq_printf(s, "last rx time: %lu.%lu\n", + last_rx / MSEC_PER_SEC, last_rx % MSEC_PER_SEC); + seq_printf(s, "rx count: %lu\n", ptp->rx_cnt); tx_start = jiffies_to_msecs(ptp->tx_start); - pos += scnprintf(buf + pos, len - pos, "last tx start time: %lu.%lu\n", - tx_start / MSEC_PER_SEC, tx_start % MSEC_PER_SEC); - pos += scnprintf(buf + pos, len - pos, "tx count: %lu\n", ptp->tx_cnt); - pos += scnprintf(buf + pos, len - pos, "tx skipped count: %lu\n", - ptp->tx_skipped); - pos += scnprintf(buf + pos, len - pos, "tx timeout count: %lu\n", - ptp->tx_timeout); - pos += scnprintf(buf + pos, len - pos, "last tx seqid: %u\n", - ptp->last_tx_seqid); + seq_printf(s, "last tx start time: %lu.%lu\n", + tx_start / MSEC_PER_SEC, tx_start % MSEC_PER_SEC); + seq_printf(s, "tx count: %lu\n", ptp->tx_cnt); + seq_printf(s, "tx skipped count: %lu\n", ptp->tx_skipped); + seq_printf(s, "tx timeout count: %lu\n", ptp->tx_timeout); + seq_printf(s, "last tx seqid: %u\n", ptp->last_tx_seqid); + ret = hclge_ptp_cfg_qry(hdev, &hw_cfg); if (ret) return ret; - pos += scnprintf(buf + pos, len - pos, "sw_cfg: %#x, hw_cfg: %#x\n", - sw_cfg, hw_cfg); + seq_printf(s, "sw_cfg: %#x, hw_cfg: %#x\n", sw_cfg, hw_cfg); - pos += scnprintf(buf + pos, len - pos, "tx type: %d, rx filter: %d\n", - ptp->ts_cfg.tx_type, ptp->ts_cfg.rx_filter); + seq_printf(s, "tx type: %d, rx filter: %d\n", + ptp->ts_cfg.tx_type, ptp->ts_cfg.rx_filter); return 0; } -static int hclge_dbg_dump_mac_uc(struct hclge_dev *hdev, char *buf, int len) +static int hclge_dbg_dump_mac_uc(struct seq_file *s, void *data) { - hclge_dbg_dump_mac_list(hdev, buf, len, true); + hclge_dbg_dump_mac_list(s, true); return 0; } -static int hclge_dbg_dump_mac_mc(struct hclge_dev *hdev, char *buf, int len) +static int hclge_dbg_dump_mac_mc(struct seq_file *s, void *data) { - hclge_dbg_dump_mac_list(hdev, buf, len, false); + hclge_dbg_dump_mac_list(s, false); return 0; } @@ -2424,156 +2787,156 @@ static int hclge_dbg_dump_mac_mc(struct hclge_dev *hdev, char *buf, int len) static const struct hclge_dbg_func hclge_dbg_cmd_func[] = { { .cmd = HNAE3_DBG_CMD_TM_NODES, - .dbg_dump = hclge_dbg_dump_tm_nodes, + .dbg_read_func = hclge_dbg_dump_tm_nodes, }, { .cmd = HNAE3_DBG_CMD_TM_PRI, - .dbg_dump = hclge_dbg_dump_tm_pri, + .dbg_read_func = hclge_dbg_dump_tm_pri, }, { .cmd = HNAE3_DBG_CMD_TM_QSET, - .dbg_dump = hclge_dbg_dump_tm_qset, + .dbg_read_func = hclge_dbg_dump_tm_qset, }, { .cmd = HNAE3_DBG_CMD_TM_MAP, - .dbg_dump = hclge_dbg_dump_tm_map, + .dbg_read_func = hclge_dbg_dump_tm_map, }, { .cmd = HNAE3_DBG_CMD_TM_PG, - .dbg_dump = hclge_dbg_dump_tm_pg, + .dbg_read_func = hclge_dbg_dump_tm_pg, }, { .cmd = HNAE3_DBG_CMD_TM_PORT, - .dbg_dump = hclge_dbg_dump_tm_port, + .dbg_read_func = hclge_dbg_dump_tm_port, }, { .cmd = HNAE3_DBG_CMD_TC_SCH_INFO, - .dbg_dump = hclge_dbg_dump_tc, + .dbg_read_func = hclge_dbg_dump_tc, }, { .cmd = HNAE3_DBG_CMD_QOS_PAUSE_CFG, - .dbg_dump = hclge_dbg_dump_qos_pause_cfg, + .dbg_read_func = hclge_dbg_dump_qos_pause_cfg, }, { .cmd = HNAE3_DBG_CMD_QOS_PRI_MAP, - .dbg_dump = hclge_dbg_dump_qos_pri_map, + .dbg_read_func = hclge_dbg_dump_qos_pri_map, }, { .cmd = HNAE3_DBG_CMD_QOS_DSCP_MAP, - .dbg_dump = hclge_dbg_dump_qos_dscp_map, + .dbg_read_func = hclge_dbg_dump_qos_dscp_map, }, { .cmd = HNAE3_DBG_CMD_QOS_BUF_CFG, - .dbg_dump = hclge_dbg_dump_qos_buf_cfg, + .dbg_read_func = hclge_dbg_dump_qos_buf_cfg, }, { .cmd = HNAE3_DBG_CMD_MAC_UC, - .dbg_dump = hclge_dbg_dump_mac_uc, + .dbg_read_func = hclge_dbg_dump_mac_uc, }, { .cmd = HNAE3_DBG_CMD_MAC_MC, - .dbg_dump = hclge_dbg_dump_mac_mc, + .dbg_read_func = hclge_dbg_dump_mac_mc, }, { .cmd = HNAE3_DBG_CMD_MNG_TBL, - .dbg_dump = hclge_dbg_dump_mng_table, + .dbg_read_func = hclge_dbg_dump_mng_table, }, { .cmd = HNAE3_DBG_CMD_LOOPBACK, - .dbg_dump = hclge_dbg_dump_loopback, + .dbg_read_func = hclge_dbg_dump_loopback, }, { .cmd = HNAE3_DBG_CMD_PTP_INFO, - .dbg_dump = hclge_dbg_dump_ptp_info, + .dbg_read_func = hclge_dbg_dump_ptp_info, }, { .cmd = HNAE3_DBG_CMD_INTERRUPT_INFO, - .dbg_dump = hclge_dbg_dump_interrupt, + .dbg_read_func = hclge_dbg_dump_interrupt, }, { .cmd = HNAE3_DBG_CMD_RESET_INFO, - .dbg_dump = hclge_dbg_dump_rst_info, + .dbg_read_func = hclge_dbg_seq_dump_rst_info, }, { .cmd = HNAE3_DBG_CMD_IMP_INFO, - .dbg_dump = hclge_dbg_get_imp_stats_info, + .dbg_read_func = hclge_dbg_get_imp_stats_info, }, { .cmd = HNAE3_DBG_CMD_NCL_CONFIG, - .dbg_dump = hclge_dbg_dump_ncl_config, + .dbg_read_func = hclge_dbg_dump_ncl_config, }, { .cmd = HNAE3_DBG_CMD_REG_BIOS_COMMON, - .dbg_dump_reg = hclge_dbg_dump_reg_cmd, + .dbg_read_func = hclge_dbg_dump_bios_reg_cmd, }, { .cmd = HNAE3_DBG_CMD_REG_SSU, - .dbg_dump_reg = hclge_dbg_dump_reg_cmd, + .dbg_read_func = hclge_dbg_dump_ssu_reg_cmd, }, { .cmd = HNAE3_DBG_CMD_REG_IGU_EGU, - .dbg_dump_reg = hclge_dbg_dump_reg_cmd, + .dbg_read_func = hclge_dbg_dump_igu_egu_reg_cmd, }, { .cmd = HNAE3_DBG_CMD_REG_RPU, - .dbg_dump_reg = hclge_dbg_dump_reg_cmd, + .dbg_read_func = hclge_dbg_dump_rpu_reg_cmd, }, { .cmd = HNAE3_DBG_CMD_REG_NCSI, - .dbg_dump_reg = hclge_dbg_dump_reg_cmd, + .dbg_read_func = hclge_dbg_dump_ncsi_reg_cmd, }, { .cmd = HNAE3_DBG_CMD_REG_RTC, - .dbg_dump_reg = hclge_dbg_dump_reg_cmd, + .dbg_read_func = hclge_dbg_dump_rtc_reg_cmd, }, { .cmd = HNAE3_DBG_CMD_REG_PPP, - .dbg_dump_reg = hclge_dbg_dump_reg_cmd, + .dbg_read_func = hclge_dbg_dump_ppp_reg_cmd, }, { .cmd = HNAE3_DBG_CMD_REG_RCB, - .dbg_dump_reg = hclge_dbg_dump_reg_cmd, + .dbg_read_func = hclge_dbg_dump_rcb_reg_cmd, }, { .cmd = HNAE3_DBG_CMD_REG_TQP, - .dbg_dump_reg = hclge_dbg_dump_reg_cmd, + .dbg_read_func = hclge_dbg_dump_tqp_reg_cmd, }, { .cmd = HNAE3_DBG_CMD_REG_MAC, - .dbg_dump = hclge_dbg_dump_mac, + .dbg_read_func = hclge_dbg_dump_mac, }, { .cmd = HNAE3_DBG_CMD_REG_DCB, - .dbg_dump = hclge_dbg_dump_dcb, + .dbg_read_func = hclge_dbg_dump_dcb, }, { .cmd = HNAE3_DBG_CMD_FD_TCAM, - .dbg_dump = hclge_dbg_dump_fd_tcam, + .dbg_read_func = hclge_dbg_dump_fd_tcam, }, { .cmd = HNAE3_DBG_CMD_MAC_TNL_STATUS, - .dbg_dump = hclge_dbg_dump_mac_tnl_status, + .dbg_read_func = hclge_dbg_dump_mac_tnl_status, }, { .cmd = HNAE3_DBG_CMD_SERV_INFO, - .dbg_dump = hclge_dbg_dump_serv_info, + .dbg_read_func = hclge_dbg_dump_serv_info, }, { .cmd = HNAE3_DBG_CMD_VLAN_CONFIG, - .dbg_dump = hclge_dbg_dump_vlan_config, + .dbg_read_func = hclge_dbg_dump_vlan_config, }, { .cmd = HNAE3_DBG_CMD_FD_COUNTER, - .dbg_dump = hclge_dbg_dump_fd_counter, + .dbg_read_func = hclge_dbg_dump_fd_counter, }, { .cmd = HNAE3_DBG_CMD_UMV_INFO, - .dbg_dump = hclge_dbg_dump_umv_info, + .dbg_read_func = hclge_dbg_dump_umv_info, }, }; -int hclge_dbg_read_cmd(struct hnae3_handle *handle, enum hnae3_dbg_cmd cmd, - char *buf, int len) +int hclge_dbg_get_read_func(struct hnae3_handle *handle, enum hnae3_dbg_cmd cmd, + read_func *func) { struct hclge_vport *vport = hclge_get_vport(handle); const struct hclge_dbg_func *cmd_func; @@ -2583,11 +2946,8 @@ int hclge_dbg_read_cmd(struct hnae3_handle *handle, enum hnae3_dbg_cmd cmd, for (i = 0; i < ARRAY_SIZE(hclge_dbg_cmd_func); i++) { if (cmd == hclge_dbg_cmd_func[i].cmd) { cmd_func = &hclge_dbg_cmd_func[i]; - if (cmd_func->dbg_dump) - return cmd_func->dbg_dump(hdev, buf, len); - else - return cmd_func->dbg_dump_reg(hdev, cmd, buf, - len); + *func = cmd_func->dbg_read_func; + return 0; } } diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.h index 724052928b88..317f79efd54c 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.h +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.h @@ -92,6 +92,7 @@ struct hclge_dbg_func { int (*dbg_dump)(struct hclge_dev *hdev, char *buf, int len); int (*dbg_dump_reg)(struct hclge_dev *hdev, enum hnae3_dbg_cmd cmd, char *buf, int len); + read_func dbg_read_func; }; struct hclge_dbg_status_dfx_info { @@ -99,646 +100,6 @@ struct hclge_dbg_status_dfx_info { char message[HCLGE_DBG_MAX_DFX_MSG_LEN]; }; -static const struct hclge_dbg_dfx_message hclge_dbg_bios_common_reg[] = { - {false, "Reserved"}, - {true, "BP_CPU_STATE"}, - {true, "DFX_MSIX_INFO_NIC_0"}, - {true, "DFX_MSIX_INFO_NIC_1"}, - {true, "DFX_MSIX_INFO_NIC_2"}, - {true, "DFX_MSIX_INFO_NIC_3"}, - - {true, "DFX_MSIX_INFO_ROC_0"}, - {true, "DFX_MSIX_INFO_ROC_1"}, - {true, "DFX_MSIX_INFO_ROC_2"}, - {true, "DFX_MSIX_INFO_ROC_3"}, - {false, "Reserved"}, - {false, "Reserved"}, -}; - -static const struct hclge_dbg_dfx_message hclge_dbg_ssu_reg_0[] = { - {false, "Reserved"}, - {true, "SSU_ETS_PORT_STATUS"}, - {true, "SSU_ETS_TCG_STATUS"}, - {false, "Reserved"}, - {false, "Reserved"}, - {true, "SSU_BP_STATUS_0"}, - - {true, "SSU_BP_STATUS_1"}, - {true, "SSU_BP_STATUS_2"}, - {true, "SSU_BP_STATUS_3"}, - {true, "SSU_BP_STATUS_4"}, - {true, "SSU_BP_STATUS_5"}, - {true, "SSU_MAC_TX_PFC_IND"}, - - {true, "MAC_SSU_RX_PFC_IND"}, - {true, "BTMP_AGEING_ST_B0"}, - {true, "BTMP_AGEING_ST_B1"}, - {true, "BTMP_AGEING_ST_B2"}, - {false, "Reserved"}, - {false, "Reserved"}, - - {true, "FULL_DROP_NUM"}, - {true, "PART_DROP_NUM"}, - {true, "PPP_KEY_DROP_NUM"}, - {true, "PPP_RLT_DROP_NUM"}, - {true, "LO_PRI_UNICAST_RLT_DROP_NUM"}, - {true, "HI_PRI_MULTICAST_RLT_DROP_NUM"}, - - {true, "LO_PRI_MULTICAST_RLT_DROP_NUM"}, - {true, "NCSI_PACKET_CURR_BUFFER_CNT"}, - {true, "BTMP_AGEING_RLS_CNT_BANK0"}, - {true, "BTMP_AGEING_RLS_CNT_BANK1"}, - {true, "BTMP_AGEING_RLS_CNT_BANK2"}, - {true, "SSU_MB_RD_RLT_DROP_CNT"}, - - {true, "SSU_PPP_MAC_KEY_NUM_L"}, - {true, "SSU_PPP_MAC_KEY_NUM_H"}, - {true, "SSU_PPP_HOST_KEY_NUM_L"}, - {true, "SSU_PPP_HOST_KEY_NUM_H"}, - {true, "PPP_SSU_MAC_RLT_NUM_L"}, - {true, "PPP_SSU_MAC_RLT_NUM_H"}, - - {true, "PPP_SSU_HOST_RLT_NUM_L"}, - {true, "PPP_SSU_HOST_RLT_NUM_H"}, - {true, "NCSI_RX_PACKET_IN_CNT_L"}, - {true, "NCSI_RX_PACKET_IN_CNT_H"}, - {true, "NCSI_TX_PACKET_OUT_CNT_L"}, - {true, "NCSI_TX_PACKET_OUT_CNT_H"}, - - {true, "SSU_KEY_DROP_NUM"}, - {true, "MB_UNCOPY_NUM"}, - {true, "RX_OQ_DROP_PKT_CNT"}, - {true, "TX_OQ_DROP_PKT_CNT"}, - {true, "BANK_UNBALANCE_DROP_CNT"}, - {true, "BANK_UNBALANCE_RX_DROP_CNT"}, - - {true, "NIC_L2_ERR_DROP_PKT_CNT"}, - {true, "ROC_L2_ERR_DROP_PKT_CNT"}, - {true, "NIC_L2_ERR_DROP_PKT_CNT_RX"}, - {true, "ROC_L2_ERR_DROP_PKT_CNT_RX"}, - {true, "RX_OQ_GLB_DROP_PKT_CNT"}, - {false, "Reserved"}, - - {true, "LO_PRI_UNICAST_CUR_CNT"}, - {true, "HI_PRI_MULTICAST_CUR_CNT"}, - {true, "LO_PRI_MULTICAST_CUR_CNT"}, - {false, "Reserved"}, - {false, "Reserved"}, - {false, "Reserved"}, -}; - -static const struct hclge_dbg_dfx_message hclge_dbg_ssu_reg_1[] = { - {true, "prt_id"}, - {true, "PACKET_TC_CURR_BUFFER_CNT_0"}, - {true, "PACKET_TC_CURR_BUFFER_CNT_1"}, - {true, "PACKET_TC_CURR_BUFFER_CNT_2"}, - {true, "PACKET_TC_CURR_BUFFER_CNT_3"}, - {true, "PACKET_TC_CURR_BUFFER_CNT_4"}, - - {true, "PACKET_TC_CURR_BUFFER_CNT_5"}, - {true, "PACKET_TC_CURR_BUFFER_CNT_6"}, - {true, "PACKET_TC_CURR_BUFFER_CNT_7"}, - {true, "PACKET_CURR_BUFFER_CNT"}, - {false, "Reserved"}, - {false, "Reserved"}, - - {true, "RX_PACKET_IN_CNT_L"}, - {true, "RX_PACKET_IN_CNT_H"}, - {true, "RX_PACKET_OUT_CNT_L"}, - {true, "RX_PACKET_OUT_CNT_H"}, - {true, "TX_PACKET_IN_CNT_L"}, - {true, "TX_PACKET_IN_CNT_H"}, - - {true, "TX_PACKET_OUT_CNT_L"}, - {true, "TX_PACKET_OUT_CNT_H"}, - {true, "ROC_RX_PACKET_IN_CNT_L"}, - {true, "ROC_RX_PACKET_IN_CNT_H"}, - {true, "ROC_TX_PACKET_OUT_CNT_L"}, - {true, "ROC_TX_PACKET_OUT_CNT_H"}, - - {true, "RX_PACKET_TC_IN_CNT_0_L"}, - {true, "RX_PACKET_TC_IN_CNT_0_H"}, - {true, "RX_PACKET_TC_IN_CNT_1_L"}, - {true, "RX_PACKET_TC_IN_CNT_1_H"}, - {true, "RX_PACKET_TC_IN_CNT_2_L"}, - {true, "RX_PACKET_TC_IN_CNT_2_H"}, - - {true, "RX_PACKET_TC_IN_CNT_3_L"}, - {true, "RX_PACKET_TC_IN_CNT_3_H"}, - {true, "RX_PACKET_TC_IN_CNT_4_L"}, - {true, "RX_PACKET_TC_IN_CNT_4_H"}, - {true, "RX_PACKET_TC_IN_CNT_5_L"}, - {true, "RX_PACKET_TC_IN_CNT_5_H"}, - - {true, "RX_PACKET_TC_IN_CNT_6_L"}, - {true, "RX_PACKET_TC_IN_CNT_6_H"}, - {true, "RX_PACKET_TC_IN_CNT_7_L"}, - {true, "RX_PACKET_TC_IN_CNT_7_H"}, - {true, "RX_PACKET_TC_OUT_CNT_0_L"}, - {true, "RX_PACKET_TC_OUT_CNT_0_H"}, - - {true, "RX_PACKET_TC_OUT_CNT_1_L"}, - {true, "RX_PACKET_TC_OUT_CNT_1_H"}, - {true, "RX_PACKET_TC_OUT_CNT_2_L"}, - {true, "RX_PACKET_TC_OUT_CNT_2_H"}, - {true, "RX_PACKET_TC_OUT_CNT_3_L"}, - {true, "RX_PACKET_TC_OUT_CNT_3_H"}, - - {true, "RX_PACKET_TC_OUT_CNT_4_L"}, - {true, "RX_PACKET_TC_OUT_CNT_4_H"}, - {true, "RX_PACKET_TC_OUT_CNT_5_L"}, - {true, "RX_PACKET_TC_OUT_CNT_5_H"}, - {true, "RX_PACKET_TC_OUT_CNT_6_L"}, - {true, "RX_PACKET_TC_OUT_CNT_6_H"}, - - {true, "RX_PACKET_TC_OUT_CNT_7_L"}, - {true, "RX_PACKET_TC_OUT_CNT_7_H"}, - {true, "TX_PACKET_TC_IN_CNT_0_L"}, - {true, "TX_PACKET_TC_IN_CNT_0_H"}, - {true, "TX_PACKET_TC_IN_CNT_1_L"}, - {true, "TX_PACKET_TC_IN_CNT_1_H"}, - - {true, "TX_PACKET_TC_IN_CNT_2_L"}, - {true, "TX_PACKET_TC_IN_CNT_2_H"}, - {true, "TX_PACKET_TC_IN_CNT_3_L"}, - {true, "TX_PACKET_TC_IN_CNT_3_H"}, - {true, "TX_PACKET_TC_IN_CNT_4_L"}, - {true, "TX_PACKET_TC_IN_CNT_4_H"}, - - {true, "TX_PACKET_TC_IN_CNT_5_L"}, - {true, "TX_PACKET_TC_IN_CNT_5_H"}, - {true, "TX_PACKET_TC_IN_CNT_6_L"}, - {true, "TX_PACKET_TC_IN_CNT_6_H"}, - {true, "TX_PACKET_TC_IN_CNT_7_L"}, - {true, "TX_PACKET_TC_IN_CNT_7_H"}, - - {true, "TX_PACKET_TC_OUT_CNT_0_L"}, - {true, "TX_PACKET_TC_OUT_CNT_0_H"}, - {true, "TX_PACKET_TC_OUT_CNT_1_L"}, - {true, "TX_PACKET_TC_OUT_CNT_1_H"}, - {true, "TX_PACKET_TC_OUT_CNT_2_L"}, - {true, "TX_PACKET_TC_OUT_CNT_2_H"}, - - {true, "TX_PACKET_TC_OUT_CNT_3_L"}, - {true, "TX_PACKET_TC_OUT_CNT_3_H"}, - {true, "TX_PACKET_TC_OUT_CNT_4_L"}, - {true, "TX_PACKET_TC_OUT_CNT_4_H"}, - {true, "TX_PACKET_TC_OUT_CNT_5_L"}, - {true, "TX_PACKET_TC_OUT_CNT_5_H"}, - - {true, "TX_PACKET_TC_OUT_CNT_6_L"}, - {true, "TX_PACKET_TC_OUT_CNT_6_H"}, - {true, "TX_PACKET_TC_OUT_CNT_7_L"}, - {true, "TX_PACKET_TC_OUT_CNT_7_H"}, - {false, "Reserved"}, - {false, "Reserved"}, -}; - -static const struct hclge_dbg_dfx_message hclge_dbg_ssu_reg_2[] = { - {true, "OQ_INDEX"}, - {true, "QUEUE_CNT"}, - {false, "Reserved"}, - {false, "Reserved"}, - {false, "Reserved"}, - {false, "Reserved"}, -}; - -static const struct hclge_dbg_dfx_message hclge_dbg_igu_egu_reg[] = { - {true, "prt_id"}, - {true, "IGU_RX_ERR_PKT"}, - {true, "IGU_RX_NO_SOF_PKT"}, - {true, "EGU_TX_1588_SHORT_PKT"}, - {true, "EGU_TX_1588_PKT"}, - {true, "EGU_TX_ERR_PKT"}, - - {true, "IGU_RX_OUT_L2_PKT"}, - {true, "IGU_RX_OUT_L3_PKT"}, - {true, "IGU_RX_OUT_L4_PKT"}, - {true, "IGU_RX_IN_L2_PKT"}, - {true, "IGU_RX_IN_L3_PKT"}, - {true, "IGU_RX_IN_L4_PKT"}, - - {true, "IGU_RX_EL3E_PKT"}, - {true, "IGU_RX_EL4E_PKT"}, - {true, "IGU_RX_L3E_PKT"}, - {true, "IGU_RX_L4E_PKT"}, - {true, "IGU_RX_ROCEE_PKT"}, - {true, "IGU_RX_OUT_UDP0_PKT"}, - - {true, "IGU_RX_IN_UDP0_PKT"}, - {true, "IGU_MC_CAR_DROP_PKT_L"}, - {true, "IGU_MC_CAR_DROP_PKT_H"}, - {true, "IGU_BC_CAR_DROP_PKT_L"}, - {true, "IGU_BC_CAR_DROP_PKT_H"}, - {false, "Reserved"}, - - {true, "IGU_RX_OVERSIZE_PKT_L"}, - {true, "IGU_RX_OVERSIZE_PKT_H"}, - {true, "IGU_RX_UNDERSIZE_PKT_L"}, - {true, "IGU_RX_UNDERSIZE_PKT_H"}, - {true, "IGU_RX_OUT_ALL_PKT_L"}, - {true, "IGU_RX_OUT_ALL_PKT_H"}, - - {true, "IGU_TX_OUT_ALL_PKT_L"}, - {true, "IGU_TX_OUT_ALL_PKT_H"}, - {true, "IGU_RX_UNI_PKT_L"}, - {true, "IGU_RX_UNI_PKT_H"}, - {true, "IGU_RX_MULTI_PKT_L"}, - {true, "IGU_RX_MULTI_PKT_H"}, - - {true, "IGU_RX_BROAD_PKT_L"}, - {true, "IGU_RX_BROAD_PKT_H"}, - {true, "EGU_TX_OUT_ALL_PKT_L"}, - {true, "EGU_TX_OUT_ALL_PKT_H"}, - {true, "EGU_TX_UNI_PKT_L"}, - {true, "EGU_TX_UNI_PKT_H"}, - - {true, "EGU_TX_MULTI_PKT_L"}, - {true, "EGU_TX_MULTI_PKT_H"}, - {true, "EGU_TX_BROAD_PKT_L"}, - {true, "EGU_TX_BROAD_PKT_H"}, - {true, "IGU_TX_KEY_NUM_L"}, - {true, "IGU_TX_KEY_NUM_H"}, - - {true, "IGU_RX_NON_TUN_PKT_L"}, - {true, "IGU_RX_NON_TUN_PKT_H"}, - {true, "IGU_RX_TUN_PKT_L"}, - {true, "IGU_RX_TUN_PKT_H"}, - {false, "Reserved"}, - {false, "Reserved"}, -}; - -static const struct hclge_dbg_dfx_message hclge_dbg_rpu_reg_0[] = { - {true, "tc_queue_num"}, - {true, "FSM_DFX_ST0"}, - {true, "FSM_DFX_ST1"}, - {true, "RPU_RX_PKT_DROP_CNT"}, - {true, "BUF_WAIT_TIMEOUT"}, - {true, "BUF_WAIT_TIMEOUT_QID"}, -}; - -static const struct hclge_dbg_dfx_message hclge_dbg_rpu_reg_1[] = { - {false, "Reserved"}, - {true, "FIFO_DFX_ST0"}, - {true, "FIFO_DFX_ST1"}, - {true, "FIFO_DFX_ST2"}, - {true, "FIFO_DFX_ST3"}, - {true, "FIFO_DFX_ST4"}, - - {true, "FIFO_DFX_ST5"}, - {false, "Reserved"}, - {false, "Reserved"}, - {false, "Reserved"}, - {false, "Reserved"}, - {false, "Reserved"}, -}; - -static const struct hclge_dbg_dfx_message hclge_dbg_ncsi_reg[] = { - {false, "Reserved"}, - {true, "NCSI_EGU_TX_FIFO_STS"}, - {true, "NCSI_PAUSE_STATUS"}, - {true, "NCSI_RX_CTRL_DMAC_ERR_CNT"}, - {true, "NCSI_RX_CTRL_SMAC_ERR_CNT"}, - {true, "NCSI_RX_CTRL_CKS_ERR_CNT"}, - - {true, "NCSI_RX_CTRL_PKT_CNT"}, - {true, "NCSI_RX_PT_DMAC_ERR_CNT"}, - {true, "NCSI_RX_PT_SMAC_ERR_CNT"}, - {true, "NCSI_RX_PT_PKT_CNT"}, - {true, "NCSI_RX_FCS_ERR_CNT"}, - {true, "NCSI_TX_CTRL_DMAC_ERR_CNT"}, - - {true, "NCSI_TX_CTRL_SMAC_ERR_CNT"}, - {true, "NCSI_TX_CTRL_PKT_CNT"}, - {true, "NCSI_TX_PT_DMAC_ERR_CNT"}, - {true, "NCSI_TX_PT_SMAC_ERR_CNT"}, - {true, "NCSI_TX_PT_PKT_CNT"}, - {true, "NCSI_TX_PT_PKT_TRUNC_CNT"}, - - {true, "NCSI_TX_PT_PKT_ERR_CNT"}, - {true, "NCSI_TX_CTRL_PKT_ERR_CNT"}, - {true, "NCSI_RX_CTRL_PKT_TRUNC_CNT"}, - {true, "NCSI_RX_CTRL_PKT_CFLIT_CNT"}, - {false, "Reserved"}, - {false, "Reserved"}, - - {true, "NCSI_MAC_RX_OCTETS_OK"}, - {true, "NCSI_MAC_RX_OCTETS_BAD"}, - {true, "NCSI_MAC_RX_UC_PKTS"}, - {true, "NCSI_MAC_RX_MC_PKTS"}, - {true, "NCSI_MAC_RX_BC_PKTS"}, - {true, "NCSI_MAC_RX_PKTS_64OCTETS"}, - - {true, "NCSI_MAC_RX_PKTS_65TO127OCTETS"}, - {true, "NCSI_MAC_RX_PKTS_128TO255OCTETS"}, - {true, "NCSI_MAC_RX_PKTS_255TO511OCTETS"}, - {true, "NCSI_MAC_RX_PKTS_512TO1023OCTETS"}, - {true, "NCSI_MAC_RX_PKTS_1024TO1518OCTETS"}, - {true, "NCSI_MAC_RX_PKTS_1519TOMAXOCTETS"}, - - {true, "NCSI_MAC_RX_FCS_ERRORS"}, - {true, "NCSI_MAC_RX_LONG_ERRORS"}, - {true, "NCSI_MAC_RX_JABBER_ERRORS"}, - {true, "NCSI_MAC_RX_RUNT_ERR_CNT"}, - {true, "NCSI_MAC_RX_SHORT_ERR_CNT"}, - {true, "NCSI_MAC_RX_FILT_PKT_CNT"}, - - {true, "NCSI_MAC_RX_OCTETS_TOTAL_FILT"}, - {true, "NCSI_MAC_TX_OCTETS_OK"}, - {true, "NCSI_MAC_TX_OCTETS_BAD"}, - {true, "NCSI_MAC_TX_UC_PKTS"}, - {true, "NCSI_MAC_TX_MC_PKTS"}, - {true, "NCSI_MAC_TX_BC_PKTS"}, - - {true, "NCSI_MAC_TX_PKTS_64OCTETS"}, - {true, "NCSI_MAC_TX_PKTS_65TO127OCTETS"}, - {true, "NCSI_MAC_TX_PKTS_128TO255OCTETS"}, - {true, "NCSI_MAC_TX_PKTS_256TO511OCTETS"}, - {true, "NCSI_MAC_TX_PKTS_512TO1023OCTETS"}, - {true, "NCSI_MAC_TX_PKTS_1024TO1518OCTETS"}, - - {true, "NCSI_MAC_TX_PKTS_1519TOMAXOCTETS"}, - {true, "NCSI_MAC_TX_UNDERRUN"}, - {true, "NCSI_MAC_TX_CRC_ERROR"}, - {true, "NCSI_MAC_TX_PAUSE_FRAMES"}, - {true, "NCSI_MAC_RX_PAD_PKTS"}, - {true, "NCSI_MAC_RX_PAUSE_FRAMES"}, -}; - -static const struct hclge_dbg_dfx_message hclge_dbg_rtc_reg[] = { - {false, "Reserved"}, - {true, "LGE_IGU_AFIFO_DFX_0"}, - {true, "LGE_IGU_AFIFO_DFX_1"}, - {true, "LGE_IGU_AFIFO_DFX_2"}, - {true, "LGE_IGU_AFIFO_DFX_3"}, - {true, "LGE_IGU_AFIFO_DFX_4"}, - - {true, "LGE_IGU_AFIFO_DFX_5"}, - {true, "LGE_IGU_AFIFO_DFX_6"}, - {true, "LGE_IGU_AFIFO_DFX_7"}, - {true, "LGE_EGU_AFIFO_DFX_0"}, - {true, "LGE_EGU_AFIFO_DFX_1"}, - {true, "LGE_EGU_AFIFO_DFX_2"}, - - {true, "LGE_EGU_AFIFO_DFX_3"}, - {true, "LGE_EGU_AFIFO_DFX_4"}, - {true, "LGE_EGU_AFIFO_DFX_5"}, - {true, "LGE_EGU_AFIFO_DFX_6"}, - {true, "LGE_EGU_AFIFO_DFX_7"}, - {true, "CGE_IGU_AFIFO_DFX_0"}, - - {true, "CGE_IGU_AFIFO_DFX_1"}, - {true, "CGE_EGU_AFIFO_DFX_0"}, - {true, "CGE_EGU_AFIFO_DFX_1"}, - {false, "Reserved"}, - {false, "Reserved"}, - {false, "Reserved"}, -}; - -static const struct hclge_dbg_dfx_message hclge_dbg_ppp_reg[] = { - {false, "Reserved"}, - {true, "DROP_FROM_PRT_PKT_CNT"}, - {true, "DROP_FROM_HOST_PKT_CNT"}, - {true, "DROP_TX_VLAN_PROC_CNT"}, - {true, "DROP_MNG_CNT"}, - {true, "DROP_FD_CNT"}, - - {true, "DROP_NO_DST_CNT"}, - {true, "DROP_MC_MBID_FULL_CNT"}, - {true, "DROP_SC_FILTERED"}, - {true, "PPP_MC_DROP_PKT_CNT"}, - {true, "DROP_PT_CNT"}, - {true, "DROP_MAC_ANTI_SPOOF_CNT"}, - - {true, "DROP_IG_VFV_CNT"}, - {true, "DROP_IG_PRTV_CNT"}, - {true, "DROP_CNM_PFC_PAUSE_CNT"}, - {true, "DROP_TORUS_TC_CNT"}, - {true, "DROP_TORUS_LPBK_CNT"}, - {true, "PPP_HFS_STS"}, - - {true, "PPP_MC_RSLT_STS"}, - {true, "PPP_P3U_STS"}, - {true, "PPP_RSLT_DESCR_STS"}, - {true, "PPP_UMV_STS_0"}, - {true, "PPP_UMV_STS_1"}, - {true, "PPP_VFV_STS"}, - - {true, "PPP_GRO_KEY_CNT"}, - {true, "PPP_GRO_INFO_CNT"}, - {true, "PPP_GRO_DROP_CNT"}, - {true, "PPP_GRO_OUT_CNT"}, - {true, "PPP_GRO_KEY_MATCH_DATA_CNT"}, - {true, "PPP_GRO_KEY_MATCH_TCAM_CNT"}, - - {true, "PPP_GRO_INFO_MATCH_CNT"}, - {true, "PPP_GRO_FREE_ENTRY_CNT"}, - {true, "PPP_GRO_INNER_DFX_SIGNAL"}, - {false, "Reserved"}, - {false, "Reserved"}, - {false, "Reserved"}, - - {true, "GET_RX_PKT_CNT_L"}, - {true, "GET_RX_PKT_CNT_H"}, - {true, "GET_TX_PKT_CNT_L"}, - {true, "GET_TX_PKT_CNT_H"}, - {true, "SEND_UC_PRT2HOST_PKT_CNT_L"}, - {true, "SEND_UC_PRT2HOST_PKT_CNT_H"}, - - {true, "SEND_UC_PRT2PRT_PKT_CNT_L"}, - {true, "SEND_UC_PRT2PRT_PKT_CNT_H"}, - {true, "SEND_UC_HOST2HOST_PKT_CNT_L"}, - {true, "SEND_UC_HOST2HOST_PKT_CNT_H"}, - {true, "SEND_UC_HOST2PRT_PKT_CNT_L"}, - {true, "SEND_UC_HOST2PRT_PKT_CNT_H"}, - - {true, "SEND_MC_FROM_PRT_CNT_L"}, - {true, "SEND_MC_FROM_PRT_CNT_H"}, - {true, "SEND_MC_FROM_HOST_CNT_L"}, - {true, "SEND_MC_FROM_HOST_CNT_H"}, - {true, "SSU_MC_RD_CNT_L"}, - {true, "SSU_MC_RD_CNT_H"}, - - {true, "SSU_MC_DROP_CNT_L"}, - {true, "SSU_MC_DROP_CNT_H"}, - {true, "SSU_MC_RD_PKT_CNT_L"}, - {true, "SSU_MC_RD_PKT_CNT_H"}, - {true, "PPP_MC_2HOST_PKT_CNT_L"}, - {true, "PPP_MC_2HOST_PKT_CNT_H"}, - - {true, "PPP_MC_2PRT_PKT_CNT_L"}, - {true, "PPP_MC_2PRT_PKT_CNT_H"}, - {true, "NTSNOS_PKT_CNT_L"}, - {true, "NTSNOS_PKT_CNT_H"}, - {true, "NTUP_PKT_CNT_L"}, - {true, "NTUP_PKT_CNT_H"}, - - {true, "NTLCL_PKT_CNT_L"}, - {true, "NTLCL_PKT_CNT_H"}, - {true, "NTTGT_PKT_CNT_L"}, - {true, "NTTGT_PKT_CNT_H"}, - {true, "RTNS_PKT_CNT_L"}, - {true, "RTNS_PKT_CNT_H"}, - - {true, "RTLPBK_PKT_CNT_L"}, - {true, "RTLPBK_PKT_CNT_H"}, - {true, "NR_PKT_CNT_L"}, - {true, "NR_PKT_CNT_H"}, - {true, "RR_PKT_CNT_L"}, - {true, "RR_PKT_CNT_H"}, - - {true, "MNG_TBL_HIT_CNT_L"}, - {true, "MNG_TBL_HIT_CNT_H"}, - {true, "FD_TBL_HIT_CNT_L"}, - {true, "FD_TBL_HIT_CNT_H"}, - {true, "FD_LKUP_CNT_L"}, - {true, "FD_LKUP_CNT_H"}, - - {true, "BC_HIT_CNT_L"}, - {true, "BC_HIT_CNT_H"}, - {true, "UM_TBL_UC_HIT_CNT_L"}, - {true, "UM_TBL_UC_HIT_CNT_H"}, - {true, "UM_TBL_MC_HIT_CNT_L"}, - {true, "UM_TBL_MC_HIT_CNT_H"}, - - {true, "UM_TBL_VMDQ1_HIT_CNT_L"}, - {true, "UM_TBL_VMDQ1_HIT_CNT_H"}, - {true, "MTA_TBL_HIT_CNT_L"}, - {true, "MTA_TBL_HIT_CNT_H"}, - {true, "FWD_BONDING_HIT_CNT_L"}, - {true, "FWD_BONDING_HIT_CNT_H"}, - - {true, "PROMIS_TBL_HIT_CNT_L"}, - {true, "PROMIS_TBL_HIT_CNT_H"}, - {true, "GET_TUNL_PKT_CNT_L"}, - {true, "GET_TUNL_PKT_CNT_H"}, - {true, "GET_BMC_PKT_CNT_L"}, - {true, "GET_BMC_PKT_CNT_H"}, - - {true, "SEND_UC_PRT2BMC_PKT_CNT_L"}, - {true, "SEND_UC_PRT2BMC_PKT_CNT_H"}, - {true, "SEND_UC_HOST2BMC_PKT_CNT_L"}, - {true, "SEND_UC_HOST2BMC_PKT_CNT_H"}, - {true, "SEND_UC_BMC2HOST_PKT_CNT_L"}, - {true, "SEND_UC_BMC2HOST_PKT_CNT_H"}, - - {true, "SEND_UC_BMC2PRT_PKT_CNT_L"}, - {true, "SEND_UC_BMC2PRT_PKT_CNT_H"}, - {true, "PPP_MC_2BMC_PKT_CNT_L"}, - {true, "PPP_MC_2BMC_PKT_CNT_H"}, - {true, "VLAN_MIRR_CNT_L"}, - {true, "VLAN_MIRR_CNT_H"}, - - {true, "IG_MIRR_CNT_L"}, - {true, "IG_MIRR_CNT_H"}, - {true, "EG_MIRR_CNT_L"}, - {true, "EG_MIRR_CNT_H"}, - {true, "RX_DEFAULT_HOST_HIT_CNT_L"}, - {true, "RX_DEFAULT_HOST_HIT_CNT_H"}, - - {true, "LAN_PAIR_CNT_L"}, - {true, "LAN_PAIR_CNT_H"}, - {true, "UM_TBL_MC_HIT_PKT_CNT_L"}, - {true, "UM_TBL_MC_HIT_PKT_CNT_H"}, - {true, "MTA_TBL_HIT_PKT_CNT_L"}, - {true, "MTA_TBL_HIT_PKT_CNT_H"}, - - {true, "PROMIS_TBL_HIT_PKT_CNT_L"}, - {true, "PROMIS_TBL_HIT_PKT_CNT_H"}, - {false, "Reserved"}, - {false, "Reserved"}, - {false, "Reserved"}, - {false, "Reserved"}, -}; - -static const struct hclge_dbg_dfx_message hclge_dbg_rcb_reg[] = { - {false, "Reserved"}, - {true, "FSM_DFX_ST0"}, - {true, "FSM_DFX_ST1"}, - {true, "FSM_DFX_ST2"}, - {true, "FIFO_DFX_ST0"}, - {true, "FIFO_DFX_ST1"}, - - {true, "FIFO_DFX_ST2"}, - {true, "FIFO_DFX_ST3"}, - {true, "FIFO_DFX_ST4"}, - {true, "FIFO_DFX_ST5"}, - {true, "FIFO_DFX_ST6"}, - {true, "FIFO_DFX_ST7"}, - - {true, "FIFO_DFX_ST8"}, - {true, "FIFO_DFX_ST9"}, - {true, "FIFO_DFX_ST10"}, - {true, "FIFO_DFX_ST11"}, - {true, "Q_CREDIT_VLD_0"}, - {true, "Q_CREDIT_VLD_1"}, - - {true, "Q_CREDIT_VLD_2"}, - {true, "Q_CREDIT_VLD_3"}, - {true, "Q_CREDIT_VLD_4"}, - {true, "Q_CREDIT_VLD_5"}, - {true, "Q_CREDIT_VLD_6"}, - {true, "Q_CREDIT_VLD_7"}, - - {true, "Q_CREDIT_VLD_8"}, - {true, "Q_CREDIT_VLD_9"}, - {true, "Q_CREDIT_VLD_10"}, - {true, "Q_CREDIT_VLD_11"}, - {true, "Q_CREDIT_VLD_12"}, - {true, "Q_CREDIT_VLD_13"}, - - {true, "Q_CREDIT_VLD_14"}, - {true, "Q_CREDIT_VLD_15"}, - {true, "Q_CREDIT_VLD_16"}, - {true, "Q_CREDIT_VLD_17"}, - {true, "Q_CREDIT_VLD_18"}, - {true, "Q_CREDIT_VLD_19"}, - - {true, "Q_CREDIT_VLD_20"}, - {true, "Q_CREDIT_VLD_21"}, - {true, "Q_CREDIT_VLD_22"}, - {true, "Q_CREDIT_VLD_23"}, - {true, "Q_CREDIT_VLD_24"}, - {true, "Q_CREDIT_VLD_25"}, - - {true, "Q_CREDIT_VLD_26"}, - {true, "Q_CREDIT_VLD_27"}, - {true, "Q_CREDIT_VLD_28"}, - {true, "Q_CREDIT_VLD_29"}, - {true, "Q_CREDIT_VLD_30"}, - {true, "Q_CREDIT_VLD_31"}, - - {true, "GRO_BD_SERR_CNT"}, - {true, "GRO_CONTEXT_SERR_CNT"}, - {true, "RX_STASH_CFG_SERR_CNT"}, - {true, "AXI_RD_FBD_SERR_CNT"}, - {true, "GRO_BD_MERR_CNT"}, - {true, "GRO_CONTEXT_MERR_CNT"}, - - {true, "RX_STASH_CFG_MERR_CNT"}, - {true, "AXI_RD_FBD_MERR_CNT"}, - {false, "Reserved"}, - {false, "Reserved"}, - {false, "Reserved"}, - {false, "Reserved"}, -}; - -static const struct hclge_dbg_dfx_message hclge_dbg_tqp_reg[] = { - {true, "q_num"}, - {true, "RCB_CFG_RX_RING_TAIL"}, - {true, "RCB_CFG_RX_RING_HEAD"}, - {true, "RCB_CFG_RX_RING_FBDNUM"}, - {true, "RCB_CFG_RX_RING_OFFSET"}, - {true, "RCB_CFG_RX_RING_FBDOFFSET"}, - - {true, "RCB_CFG_RX_RING_PKTNUM_RECORD"}, - {true, "RCB_CFG_TX_RING_TAIL"}, - {true, "RCB_CFG_TX_RING_HEAD"}, - {true, "RCB_CFG_TX_RING_FBDNUM"}, - {true, "RCB_CFG_TX_RING_OFFSET"}, - {true, "RCB_CFG_TX_RING_EBDNUM"}, -}; - #define HCLGE_DBG_INFO_LEN 256 #define HCLGE_DBG_VLAN_FLTR_INFO_LEN 256 #define HCLGE_DBG_VLAN_OFFLOAD_INFO_LEN 512 @@ -771,4 +132,7 @@ struct hclge_dbg_vlan_cfg { u8 pri_only2; }; +int hclge_dbg_cmd_send(struct hclge_dev *hdev, struct hclge_desc *desc_src, + int index, int bd_num, enum hclge_opcode_type cmd); + #endif diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_devlink.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_devlink.c index 9a939c0b217f..a1571c108678 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_devlink.c +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_devlink.c @@ -5,6 +5,34 @@ #include "hclge_devlink.h" +static int hclge_devlink_scc_info_get(struct devlink *devlink, + struct devlink_info_req *req) +{ + struct hclge_devlink_priv *priv = devlink_priv(devlink); + char scc_version[HCLGE_DEVLINK_FW_SCC_LEN]; + struct hclge_dev *hdev = priv->hdev; + u32 scc_version_tmp; + int ret; + + ret = hclge_query_scc_version(hdev, &scc_version_tmp); + if (ret) { + dev_err(&hdev->pdev->dev, + "failed to get scc version, ret = %d\n", ret); + return ret; + } + + snprintf(scc_version, sizeof(scc_version), "%lu.%lu.%lu.%lu", + hnae3_get_field(scc_version_tmp, HNAE3_SCC_VERSION_BYTE3_MASK, + HNAE3_FW_VERSION_BYTE3_SHIFT), + hnae3_get_field(scc_version_tmp, HNAE3_SCC_VERSION_BYTE2_MASK, + HNAE3_FW_VERSION_BYTE2_SHIFT), + hnae3_get_field(scc_version_tmp, HNAE3_SCC_VERSION_BYTE1_MASK, + HNAE3_FW_VERSION_BYTE1_SHIFT), + hnae3_get_field(scc_version_tmp, HNAE3_SCC_VERSION_BYTE0_MASK, + HNAE3_FW_VERSION_BYTE0_SHIFT)); + return devlink_info_version_running_put(req, "fw.scc", scc_version); +} + static int hclge_devlink_info_get(struct devlink *devlink, struct devlink_info_req *req, struct netlink_ext_ack *extack) @@ -13,6 +41,7 @@ static int hclge_devlink_info_get(struct devlink *devlink, struct hclge_devlink_priv *priv = devlink_priv(devlink); char version_str[HCLGE_DEVLINK_FW_STRING_LEN]; struct hclge_dev *hdev = priv->hdev; + int ret; snprintf(version_str, sizeof(version_str), "%lu.%lu.%lu.%lu", hnae3_get_field(hdev->fw_version, HNAE3_FW_VERSION_BYTE3_MASK, @@ -24,9 +53,18 @@ static int hclge_devlink_info_get(struct devlink *devlink, hnae3_get_field(hdev->fw_version, HNAE3_FW_VERSION_BYTE0_MASK, HNAE3_FW_VERSION_BYTE0_SHIFT)); - return devlink_info_version_running_put(req, - DEVLINK_INFO_VERSION_GENERIC_FW, - version_str); + ret = devlink_info_version_running_put(req, + DEVLINK_INFO_VERSION_GENERIC_FW, + version_str); + if (ret) { + dev_err(&hdev->pdev->dev, "failed to set running version of fw\n"); + return ret; + } + + if (hdev->pdev->revision > HNAE3_DEVICE_VERSION_V2) + ret = hclge_devlink_scc_info_get(devlink, req); + + return ret; } static int hclge_devlink_reload_down(struct devlink *devlink, bool netns_change, diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_devlink.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_devlink.h index 918be04507a5..148effa5ea89 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_devlink.h +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_devlink.h @@ -6,6 +6,8 @@ #include "hclge_main.h" +#define HCLGE_DEVLINK_FW_SCC_LEN 32 + struct hclge_devlink_priv { struct hclge_dev *hdev; }; diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c index d63e114f93d0..cc7f46c0b35f 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c @@ -1198,6 +1198,425 @@ static const struct hclge_hw_error hclge_rocee_qmm_ovf_err_int[] = { } }; +static const struct hclge_mod_reg_info hclge_ssu_reg_0_info[] = { + { + .reg_name = "SSU_BP_STATUS_0~5", + .reg_offset_group = { 5, 6, 7, 8, 9, 10}, + .group_size = 6 + }, { + .reg_name = "LO_PRI_UNICAST_CUR_CNT", + .reg_offset_group = {54}, + .group_size = 1 + }, { + .reg_name = "HI/LO_PRI_MULTICAST_CUR_CNT", + .reg_offset_group = {55, 56}, + .group_size = 2 + }, { + .reg_name = "SSU_MB_RD_RLT_DROP_CNT", + .reg_offset_group = {29}, + .group_size = 1 + }, { + .reg_name = "SSU_PPP_MAC_KEY_NUM", + .reg_offset_group = {31, 30}, + .group_size = 2 + }, { + .reg_name = "SSU_PPP_HOST_KEY_NUM", + .reg_offset_group = {33, 32}, + .group_size = 2 + }, { + .reg_name = "PPP_SSU_MAC/HOST_RLT_NUM", + .reg_offset_group = {35, 34, 37, 36}, + .group_size = 4 + }, { + .reg_name = "FULL/PART_DROP_NUM", + .reg_offset_group = {18, 19}, + .group_size = 2 + }, { + .reg_name = "PPP_KEY/RLT_DROP_NUM", + .reg_offset_group = {20, 21}, + .group_size = 2 + }, { + .reg_name = "NIC/ROC_L2_ERR_DROP_PKT_CNT", + .reg_offset_group = {48, 49}, + .group_size = 2 + }, { + .reg_name = "NIC/ROC_L2_ERR_DROP_PKT_CNT_RX", + .reg_offset_group = {50, 51}, + .group_size = 2 + }, +}; + +static const struct hclge_mod_reg_info hclge_ssu_reg_1_info[] = { + { + .reg_name = "RX_PACKET_IN/OUT_CNT", + .reg_offset_group = {13, 12, 15, 14}, + .group_size = 4 + }, { + .reg_name = "TX_PACKET_IN/OUT_CNT", + .reg_offset_group = {17, 16, 19, 18}, + .group_size = 4 + }, { + .reg_name = "RX_PACKET_TC0_IN/OUT_CNT", + .reg_offset_group = {25, 24, 41, 40}, + .group_size = 4 + }, { + .reg_name = "RX_PACKET_TC1_IN/OUT_CNT", + .reg_offset_group = {27, 26, 43, 42}, + .group_size = 4 + }, { + .reg_name = "RX_PACKET_TC2_IN/OUT_CNT", + .reg_offset_group = {29, 28, 45, 44}, + .group_size = 4 + }, { + .reg_name = "RX_PACKET_TC3_IN/OUT_CNT", + .reg_offset_group = {31, 30, 47, 46}, + .group_size = 4 + }, { + .reg_name = "RX_PACKET_TC4_IN/OUT_CNT", + .reg_offset_group = {33, 32, 49, 48}, + .group_size = 4 + }, { + .reg_name = "RX_PACKET_TC5_IN/OUT_CNT", + .reg_offset_group = {35, 34, 51, 50}, + .group_size = 4 + }, { + .reg_name = "RX_PACKET_TC6_IN/OUT_CNT", + .reg_offset_group = {37, 36, 53, 52}, + .group_size = 4 + }, { + .reg_name = "RX_PACKET_TC7_IN/OUT_CNT", + .reg_offset_group = {39, 38, 55, 54}, + .group_size = 4 + }, { + .reg_name = "TX_PACKET_TC0_IN/OUT_CNT", + .reg_offset_group = {57, 56, 73, 72}, + .group_size = 4 + }, { + .reg_name = "TX_PACKET_TC1_IN/OUT_CNT", + .reg_offset_group = {59, 58, 75, 74}, + .group_size = 4 + }, { + .reg_name = "TX_PACKET_TC2_IN/OUT_CNT", + .reg_offset_group = {61, 60, 77, 76}, + .group_size = 4 + }, { + .reg_name = "TX_PACKET_TC3_IN/OUT_CNT", + .reg_offset_group = {63, 62, 79, 78}, + .group_size = 4 + }, { + .reg_name = "TX_PACKET_TC4_IN/OUT_CNT", + .reg_offset_group = {65, 64, 81, 80}, + .group_size = 4 + }, { + .reg_name = "TX_PACKET_TC5_IN/OUT_CNT", + .reg_offset_group = {67, 66, 83, 82}, + .group_size = 4 + }, { + .reg_name = "TX_PACKET_TC6_IN/OUT_CNT", + .reg_offset_group = {69, 68, 85, 84}, + .group_size = 4 + }, { + .reg_name = "TX_PACKET_TC7_IN/OUT_CNT", + .reg_offset_group = {71, 70, 87, 86}, + .group_size = 4 + }, { + .reg_name = "PACKET_TC0~3_CURR_BUFFER_CNT", + .reg_offset_group = {1, 2, 3, 4}, + .group_size = 4 + }, { + .reg_name = "PACKET_TC4~7_CURR_BUFFER_CNT", + .reg_offset_group = {5, 6, 7, 8}, + .group_size = 4 + }, { + .reg_name = "ROC_RX_PACKET_IN_CNT", + .reg_offset_group = {21, 20}, + .group_size = 2 + }, { + .reg_name = "ROC_TX_PACKET_OUT_CNT", + .reg_offset_group = {23, 22}, + .group_size = 2 + } +}; + +static const struct hclge_mod_reg_info hclge_rpu_reg_0_info[] = { + { + .reg_name = "RPU_FSM_DFX_ST0/ST1_TNL", + .has_suffix = true, + .reg_offset_group = {1, 2}, + .group_size = 2 + }, { + .reg_name = "RPU_RX_PKT_DROP_CNT_TNL", + .has_suffix = true, + .reg_offset_group = {3}, + .group_size = 1 + } +}; + +static const struct hclge_mod_reg_info hclge_rpu_reg_1_info[] = { + { + .reg_name = "FIFO_DFX_ST0_1_2_4", + .reg_offset_group = {1, 2, 3, 5}, + .group_size = 4 + } +}; + +static const struct hclge_mod_reg_info hclge_igu_egu_reg_info[] = { + { + .reg_name = "IGU_RX_ERR_PKT", + .reg_offset_group = {1}, + .group_size = 1 + }, { + .reg_name = "IGU_RX_OUT_ALL_PKT", + .reg_offset_group = {29, 28}, + .group_size = 2 + }, { + .reg_name = "EGU_TX_OUT_ALL_PKT", + .reg_offset_group = {39, 38}, + .group_size = 2 + }, { + .reg_name = "EGU_TX_ERR_PKT", + .reg_offset_group = {5}, + .group_size = 1 + } +}; + +static const struct hclge_mod_reg_info hclge_gen_reg_info_tnl[] = { + { + .reg_name = "SSU2RPU_TNL_WR_PKT_CNT_TNL", + .has_suffix = true, + .reg_offset_group = {1}, + .group_size = 1 + }, { + .reg_name = "RPU2HST_TNL_WR_PKT_CNT_TNL", + .has_suffix = true, + .reg_offset_group = {12}, + .group_size = 1 + } +}; + +static const struct hclge_mod_reg_info hclge_gen_reg_info[] = { + { + .reg_name = "SSU_OVERSIZE_DROP_CNT", + .reg_offset_group = {12}, + .group_size = 1 + }, { + .reg_name = "ROCE_RX_BYPASS_5NS_DROP_NUM", + .reg_offset_group = {13}, + .group_size = 1 + }, { + .reg_name = "RX_PKT_IN/OUT_ERR_CNT", + .reg_offset_group = {15, 14, 19, 18}, + .group_size = 4 + }, { + .reg_name = "TX_PKT_IN/OUT_ERR_CNT", + .reg_offset_group = {17, 16, 21, 20}, + .group_size = 4 + }, { + .reg_name = "ETS_TC_READY", + .reg_offset_group = {22}, + .group_size = 1 + }, { + .reg_name = "MIB_TX/RX_BAD_PKTS", + .reg_offset_group = {19, 18, 29, 28}, + .group_size = 4 + }, { + .reg_name = "MIB_TX/RX_GOOD_PKTS", + .reg_offset_group = {21, 20, 31, 30}, + .group_size = 4 + }, { + .reg_name = "MIB_TX/RX_TOTAL_PKTS", + .reg_offset_group = {23, 22, 33, 32}, + .group_size = 4 + }, { + .reg_name = "MIB_TX/RX_PAUSE_PKTS", + .reg_offset_group = {25, 24, 35, 34}, + .group_size = 4 + }, { + .reg_name = "MIB_TX_ERR_ALL_PKTS", + .reg_offset_group = {27, 26}, + .group_size = 2 + }, { + .reg_name = "MIB_RX_FCS_ERR_PKTS", + .reg_offset_group = {37, 36}, + .group_size = 2 + }, { + .reg_name = "IGU_EGU_AUTO_GATE_EN", + .reg_offset_group = {42}, + .group_size = 1 + }, { + .reg_name = "IGU_EGU_INT_SRC", + .reg_offset_group = {43}, + .group_size = 1 + }, { + .reg_name = "EGU_READY_NUM_CFG", + .reg_offset_group = {44}, + .group_size = 1 + }, { + .reg_name = "IGU_EGU_TNL_DFX", + .reg_offset_group = {45}, + .group_size = 1 + }, { + .reg_name = "TX_TNL_NOTE_PKT", + .reg_offset_group = {46}, + .group_size = 1 + } +}; + +static const struct hclge_mod_reg_common_msg hclge_ssu_reg_common_msg[] = { + { + .cmd = HCLGE_OPC_DFX_SSU_REG_0, + .result_regs = hclge_ssu_reg_0_info, + .bd_num = HCLGE_BD_NUM_SSU_REG_0, + .result_regs_size = ARRAY_SIZE(hclge_ssu_reg_0_info) + }, { + .cmd = HCLGE_OPC_DFX_SSU_REG_1, + .result_regs = hclge_ssu_reg_1_info, + .bd_num = HCLGE_BD_NUM_SSU_REG_1, + .result_regs_size = ARRAY_SIZE(hclge_ssu_reg_1_info) + }, { + .cmd = HCLGE_OPC_DFX_RPU_REG_0, + .result_regs = hclge_rpu_reg_0_info, + .bd_num = HCLGE_BD_NUM_RPU_REG_0, + .result_regs_size = ARRAY_SIZE(hclge_rpu_reg_0_info), + .need_para = true + }, { + .cmd = HCLGE_OPC_DFX_RPU_REG_1, + .result_regs = hclge_rpu_reg_1_info, + .bd_num = HCLGE_BD_NUM_RPU_REG_1, + .result_regs_size = ARRAY_SIZE(hclge_rpu_reg_1_info) + }, { + .cmd = HCLGE_OPC_DFX_IGU_EGU_REG, + .result_regs = hclge_igu_egu_reg_info, + .bd_num = HCLGE_BD_NUM_IGU_EGU_REG, + .result_regs_size = ARRAY_SIZE(hclge_igu_egu_reg_info) + }, { + .cmd = HCLGE_OPC_DFX_GEN_REG, + .result_regs = hclge_gen_reg_info_tnl, + .bd_num = HCLGE_BD_NUM_GEN_REG, + .result_regs_size = ARRAY_SIZE(hclge_gen_reg_info_tnl), + .need_para = true + }, { + .cmd = HCLGE_OPC_DFX_GEN_REG, + .result_regs = hclge_gen_reg_info, + .bd_num = HCLGE_BD_NUM_GEN_REG, + .result_regs_size = ARRAY_SIZE(hclge_gen_reg_info) + } +}; + +static int +hclge_print_mod_reg_info(struct device *dev, struct hclge_desc *desc, + const struct hclge_mod_reg_info *reg_info, int size) +{ + int i, j, pos, actual_len; + u8 offset, bd_idx, index; + char *buf; + + buf = kzalloc(HCLGE_MOD_REG_INFO_LEN_MAX, GFP_KERNEL); + if (!buf) + return -ENOMEM; + + for (i = 0; i < size; i++) { + actual_len = strlen(reg_info[i].reg_name) + + HCLGE_MOD_REG_EXTRA_LEN + + HCLGE_MOD_REG_VALUE_LEN * reg_info[i].group_size; + if (actual_len > HCLGE_MOD_REG_INFO_LEN_MAX) { + dev_info(dev, "length of reg(%s) is invalid, len=%d\n", + reg_info[i].reg_name, actual_len); + continue; + } + + pos = scnprintf(buf, HCLGE_MOD_REG_INFO_LEN_MAX, "%s", + reg_info[i].reg_name); + if (reg_info[i].has_suffix) + pos += scnprintf(buf + pos, + HCLGE_MOD_REG_INFO_LEN_MAX - pos, "%u", + le32_to_cpu(desc->data[0])); + pos += scnprintf(buf + pos, + HCLGE_MOD_REG_INFO_LEN_MAX - pos, + ":"); + for (j = 0; j < reg_info[i].group_size; j++) { + offset = reg_info[i].reg_offset_group[j]; + index = offset % HCLGE_DESC_DATA_LEN; + bd_idx = offset / HCLGE_DESC_DATA_LEN; + pos += scnprintf(buf + pos, + HCLGE_MOD_REG_INFO_LEN_MAX - pos, + " %08x", + le32_to_cpu(desc[bd_idx].data[index])); + } + dev_info(dev, "%s\n", buf); + } + + kfree(buf); + return 0; +} + +static bool hclge_err_mod_check_support_cmd(enum hclge_opcode_type opcode, + struct hclge_dev *hdev) +{ + if (opcode == HCLGE_OPC_DFX_GEN_REG && + !hnae3_ae_dev_gen_reg_dfx_supported(hdev)) + return false; + return true; +} + +/* For each common msg, send cmdq to IMP and print result reg info. + * If there is a parameter, loop it and request. + */ +static void +hclge_query_reg_info(struct hclge_dev *hdev, + struct hclge_mod_reg_common_msg *msg, u32 loop_time, + u32 *loop_para) +{ + int desc_len, i, ret; + + desc_len = msg->bd_num * sizeof(struct hclge_desc); + msg->desc = kzalloc(desc_len, GFP_KERNEL); + if (!msg->desc) { + dev_err(&hdev->pdev->dev, "failed to query reg info, ret=%d", + -ENOMEM); + return; + } + + for (i = 0; i < loop_time; i++) { + ret = hclge_dbg_cmd_send(hdev, msg->desc, *loop_para, + msg->bd_num, msg->cmd); + loop_para++; + if (ret) + continue; + ret = hclge_print_mod_reg_info(&hdev->pdev->dev, msg->desc, + msg->result_regs, + msg->result_regs_size); + if (ret) + dev_err(&hdev->pdev->dev, "failed to print mod reg info, ret=%d\n", + ret); + } + + kfree(msg->desc); +} + +static void hclge_query_reg_info_of_ssu(struct hclge_dev *hdev) +{ + u32 loop_para[HCLGE_MOD_MSG_PARA_ARRAY_MAX_SIZE] = {0}; + struct hclge_mod_reg_common_msg msg; + u8 i, j, num, loop_time; + + num = ARRAY_SIZE(hclge_ssu_reg_common_msg); + for (i = 0; i < num; i++) { + msg = hclge_ssu_reg_common_msg[i]; + if (!hclge_err_mod_check_support_cmd(msg.cmd, hdev)) + continue; + loop_time = 1; + loop_para[0] = 0; + if (msg.need_para) { + loop_time = min(hdev->ae_dev->dev_specs.tnl_num, + HCLGE_MOD_MSG_PARA_ARRAY_MAX_SIZE); + for (j = 0; j < loop_time; j++) + loop_para[j] = j + 1; + } + hclge_query_reg_info(hdev, &msg, loop_time, loop_para); + } +} + static const struct hclge_hw_module_id hclge_hw_module_id_st[] = { { .module_id = MODULE_NONE, @@ -1210,7 +1629,8 @@ static const struct hclge_hw_module_id hclge_hw_module_id_st[] = { .msg = "MODULE_GE" }, { .module_id = MODULE_IGU_EGU, - .msg = "MODULE_IGU_EGU" + .msg = "MODULE_IGU_EGU", + .query_reg_info = hclge_query_reg_info_of_ssu }, { .module_id = MODULE_LGE, .msg = "MODULE_LGE" @@ -1231,7 +1651,8 @@ static const struct hclge_hw_module_id hclge_hw_module_id_st[] = { .msg = "MODULE_RTC" }, { .module_id = MODULE_SSU, - .msg = "MODULE_SSU" + .msg = "MODULE_SSU", + .query_reg_info = hclge_query_reg_info_of_ssu }, { .module_id = MODULE_TM, .msg = "MODULE_TM" @@ -2762,7 +3183,7 @@ void hclge_handle_occurred_error(struct hclge_dev *hdev) } static bool -hclge_handle_error_type_reg_log(struct device *dev, +hclge_handle_error_type_reg_log(struct hclge_dev *hdev, struct hclge_mod_err_info *mod_info, struct hclge_type_reg_err_info *type_reg_info) { @@ -2770,6 +3191,7 @@ hclge_handle_error_type_reg_log(struct device *dev, #define HCLGE_ERR_TYPE_IS_RAS_OFFSET 7 u8 mod_id, total_module, type_id, total_type, i, is_ras; + struct device *dev = &hdev->pdev->dev; u8 index_module = MODULE_NONE; u8 index_type = NONE_ERROR; bool cause_by_vf = false; @@ -2810,6 +3232,9 @@ hclge_handle_error_type_reg_log(struct device *dev, for (i = 0; i < type_reg_info->reg_num; i++) dev_err(dev, "0x%08x\n", type_reg_info->hclge_reg[i]); + if (hclge_hw_module_id_st[index_module].query_reg_info) + hclge_hw_module_id_st[index_module].query_reg_info(hdev); + return cause_by_vf; } @@ -2850,7 +3275,7 @@ static void hclge_handle_error_module_log(struct hnae3_ae_dev *ae_dev, type_reg_info = (struct hclge_type_reg_err_info *) &buf[offset++]; - if (hclge_handle_error_type_reg_log(dev, mod_info, + if (hclge_handle_error_type_reg_log(hdev, mod_info, type_reg_info)) cause_by_vf = true; diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h index 68b738affa66..45a783a50643 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h @@ -5,6 +5,7 @@ #define __HCLGE_ERR_H #include "hclge_main.h" +#include "hclge_debugfs.h" #include "hnae3.h" #define HCLGE_MPF_RAS_INT_MIN_BD_NUM 10 @@ -115,6 +116,18 @@ #define HCLGE_REG_NUM_MAX 256 #define HCLGE_DESC_NO_DATA_LEN 8 +#define HCLGE_BD_NUM_SSU_REG_0 10 +#define HCLGE_BD_NUM_SSU_REG_1 15 +#define HCLGE_BD_NUM_RPU_REG_0 1 +#define HCLGE_BD_NUM_RPU_REG_1 2 +#define HCLGE_BD_NUM_IGU_EGU_REG 9 +#define HCLGE_BD_NUM_GEN_REG 8 +#define HCLGE_MOD_REG_INFO_LEN_MAX 256 +#define HCLGE_MOD_REG_EXTRA_LEN 11 +#define HCLGE_MOD_REG_VALUE_LEN 9 +#define HCLGE_MOD_REG_GROUP_MAX_SIZE 6 +#define HCLGE_MOD_MSG_PARA_ARRAY_MAX_SIZE 8 + enum hclge_err_int_type { HCLGE_ERR_INT_MSIX = 0, HCLGE_ERR_INT_RAS_CE = 1, @@ -191,6 +204,7 @@ struct hclge_hw_error { struct hclge_hw_module_id { enum hclge_mod_name_list module_id; const char *msg; + void (*query_reg_info)(struct hclge_dev *hdev); }; struct hclge_hw_type_id { @@ -218,6 +232,28 @@ struct hclge_type_reg_err_info { u32 hclge_reg[HCLGE_REG_NUM_MAX]; }; +struct hclge_mod_reg_info { + const char *reg_name; + bool has_suffix; /* add suffix for register name */ + /* the positions of reg values in hclge_desc.data */ + u8 reg_offset_group[HCLGE_MOD_REG_GROUP_MAX_SIZE]; + u8 group_size; +}; + +/* This structure defines cmdq used to query the hardware module debug + * regisgers. + */ +struct hclge_mod_reg_common_msg { + enum hclge_opcode_type cmd; + struct hclge_desc *desc; + u8 bd_num; /* the bd number of hclge_desc used */ + bool need_para; /* whether this cmdq needs to add para */ + + /* the regs need to print */ + const struct hclge_mod_reg_info *result_regs; + u16 result_regs_size; +}; + int hclge_config_mac_tnl_int(struct hclge_dev *hdev, bool en); int hclge_config_nic_hw_error(struct hclge_dev *hdev, bool state); int hclge_config_rocee_ras_interrupt(struct hclge_dev *hdev, bool en); diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c index b4afb66efe5c..f209a05e2033 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c @@ -6,6 +6,7 @@ #include <linux/etherdevice.h> #include <linux/init.h> #include <linux/interrupt.h> +#include <linux/irq.h> #include <linux/kernel.h> #include <linux/module.h> #include <linux/netdevice.h> @@ -13,8 +14,9 @@ #include <linux/platform_device.h> #include <linux/if_vlan.h> #include <linux/crash_dump.h> -#include <net/ipv6.h> + #include <net/rtnetlink.h> + #include "hclge_cmd.h" #include "hclge_dcb.h" #include "hclge_main.h" @@ -27,6 +29,8 @@ #include "hclge_devlink.h" #include "hclge_comm_cmd.h" +#include "hclge_trace.h" + #define HCLGE_NAME "hclge" #define HCLGE_BUF_SIZE_UNIT 256U @@ -391,6 +395,48 @@ int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num) return hclge_comm_cmd_send(&hw->hw, desc, num); } +static void hclge_trace_cmd_send(struct hclge_comm_hw *hw, struct hclge_desc *desc, + int num, bool is_special) +{ + int i; + + trace_hclge_pf_cmd_send(hw, desc, 0, num); + + if (!is_special) { + for (i = 1; i < num; i++) + trace_hclge_pf_cmd_send(hw, &desc[i], i, num); + } else { + for (i = 1; i < num; i++) + trace_hclge_pf_special_cmd_send(hw, (__le32 *)&desc[i], + i, num); + } +} + +static void hclge_trace_cmd_get(struct hclge_comm_hw *hw, struct hclge_desc *desc, + int num, bool is_special) +{ + int i; + + if (!HCLGE_COMM_SEND_SYNC(le16_to_cpu(desc->flag))) + return; + + trace_hclge_pf_cmd_get(hw, desc, 0, num); + + if (!is_special) { + for (i = 1; i < num; i++) + trace_hclge_pf_cmd_get(hw, &desc[i], i, num); + } else { + for (i = 1; i < num; i++) + trace_hclge_pf_special_cmd_get(hw, (__le32 *)&desc[i], + i, num); + } +} + +static const struct hclge_comm_cmq_ops hclge_cmq_ops = { + .trace_cmd_send = hclge_trace_cmd_send, + .trace_cmd_get = hclge_trace_cmd_get, +}; + static int hclge_mac_update_stats_defective(struct hclge_dev *hdev) { #define HCLGE_MAC_CMD_NUM 21 @@ -444,7 +490,7 @@ static int hclge_mac_update_stats_complete(struct hclge_dev *hdev) desc_num = reg_num / HCLGE_REG_NUM_PER_DESC + 1; /* This may be called inside atomic sections, - * so GFP_ATOMIC is more suitalbe here + * so GFP_ATOMIC is more suitable here */ desc = kcalloc(desc_num, sizeof(struct hclge_desc), GFP_ATOMIC); if (!desc) @@ -536,7 +582,7 @@ static u64 *hclge_comm_get_stats(struct hclge_dev *hdev, int size, u64 *data) { u64 *buf = data; - u32 i; + int i; for (i = 0; i < size; i++) { if (strs[i].stats_num > hdev->ae_dev->dev_specs.mac_stats_num) @@ -549,25 +595,21 @@ static u64 *hclge_comm_get_stats(struct hclge_dev *hdev, return buf; } -static u8 *hclge_comm_get_strings(struct hclge_dev *hdev, u32 stringset, - const struct hclge_comm_stats_str strs[], - int size, u8 *data) +static void hclge_comm_get_strings(struct hclge_dev *hdev, u32 stringset, + const struct hclge_comm_stats_str strs[], + int size, u8 **data) { - char *buff = (char *)data; - u32 i; + int i; if (stringset != ETH_SS_STATS) - return buff; + return; for (i = 0; i < size; i++) { if (strs[i].stats_num > hdev->ae_dev->dev_specs.mac_stats_num) continue; - snprintf(buff, ETH_GSTRING_LEN, "%s", strs[i].desc); - buff = buff + ETH_GSTRING_LEN; + ethtool_puts(data, strs[i].desc); } - - return (u8 *)buff; } static void hclge_update_stats_for_all(struct hclge_dev *hdev) @@ -672,44 +714,38 @@ static int hclge_get_sset_count(struct hnae3_handle *handle, int stringset) } static void hclge_get_strings(struct hnae3_handle *handle, u32 stringset, - u8 *data) + u8 **data) { struct hclge_vport *vport = hclge_get_vport(handle); struct hclge_dev *hdev = vport->back; - u8 *p = (char *)data; + const char *str; int size; if (stringset == ETH_SS_STATS) { size = ARRAY_SIZE(g_mac_stats_string); - p = hclge_comm_get_strings(hdev, stringset, g_mac_stats_string, - size, p); - p = hclge_comm_tqps_get_strings(handle, p); + hclge_comm_get_strings(hdev, stringset, g_mac_stats_string, + size, data); + hclge_comm_tqps_get_strings(handle, data); } else if (stringset == ETH_SS_TEST) { if (handle->flags & HNAE3_SUPPORT_EXTERNAL_LOOPBACK) { - memcpy(p, hns3_nic_test_strs[HNAE3_LOOP_EXTERNAL], - ETH_GSTRING_LEN); - p += ETH_GSTRING_LEN; + str = hns3_nic_test_strs[HNAE3_LOOP_EXTERNAL]; + ethtool_puts(data, str); } if (handle->flags & HNAE3_SUPPORT_APP_LOOPBACK) { - memcpy(p, hns3_nic_test_strs[HNAE3_LOOP_APP], - ETH_GSTRING_LEN); - p += ETH_GSTRING_LEN; + str = hns3_nic_test_strs[HNAE3_LOOP_APP]; + ethtool_puts(data, str); } if (handle->flags & HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK) { - memcpy(p, hns3_nic_test_strs[HNAE3_LOOP_SERIAL_SERDES], - ETH_GSTRING_LEN); - p += ETH_GSTRING_LEN; + str = hns3_nic_test_strs[HNAE3_LOOP_SERIAL_SERDES]; + ethtool_puts(data, str); } if (handle->flags & HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK) { - memcpy(p, - hns3_nic_test_strs[HNAE3_LOOP_PARALLEL_SERDES], - ETH_GSTRING_LEN); - p += ETH_GSTRING_LEN; + str = hns3_nic_test_strs[HNAE3_LOOP_PARALLEL_SERDES]; + ethtool_puts(data, str); } if (handle->flags & HNAE3_SUPPORT_PHY_LOOPBACK) { - memcpy(p, hns3_nic_test_strs[HNAE3_LOOP_PHY], - ETH_GSTRING_LEN); - p += ETH_GSTRING_LEN; + str = hns3_nic_test_strs[HNAE3_LOOP_PHY]; + ethtool_puts(data, str); } } } @@ -1537,6 +1573,9 @@ static int hclge_configure(struct hclge_dev *hdev) cfg.default_speed, ret); return ret; } + hdev->hw.mac.req_speed = hdev->hw.mac.speed; + hdev->hw.mac.req_autoneg = AUTONEG_ENABLE; + hdev->hw.mac.req_duplex = DUPLEX_FULL; hclge_parse_link_mode(hdev, cfg.speed_ability); @@ -1766,7 +1805,8 @@ static int hclge_vport_setup(struct hclge_vport *vport, u16 num_tqps) nic->pdev = hdev->pdev; nic->ae_algo = &ae_algo; - nic->numa_node_mask = hdev->numa_node_mask; + bitmap_copy(nic->numa_node_mask.bits, hdev->numa_node_mask.bits, + MAX_NUMNODES); nic->kinfo.io_base = hdev->hw.hw.io_base; ret = hclge_knic_setup(vport, num_tqps, @@ -2318,7 +2358,7 @@ static int hclge_common_thrd_config(struct hclge_dev *hdev, for (i = 0; i < 2; i++) { hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_RX_COM_THRD_ALLOC, false); - req = (struct hclge_rx_com_thrd *)&desc[i].data; + req = (struct hclge_rx_com_thrd *)desc[i].data; /* The first descriptor set the NEXT bit to 1 */ if (i == 0) @@ -2458,7 +2498,8 @@ static int hclge_init_roce_base_info(struct hclge_vport *vport) roce->pdev = nic->pdev; roce->ae_algo = nic->ae_algo; - roce->numa_node_mask = nic->numa_node_mask; + bitmap_copy(roce->numa_node_mask.bits, nic->numa_node_mask.bits, + MAX_NUMNODES); return 0; } @@ -2583,7 +2624,7 @@ int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex, u8 lan int ret; duplex = hclge_check_speed_dup(duplex, speed); - if (!mac->support_autoneg && mac->speed == speed && + if (!mac->support_autoneg && mac->speed == (u32)speed && mac->duplex == duplex && (mac->lane_num == lane_num || lane_num == 0)) return 0; @@ -2604,8 +2645,17 @@ static int hclge_cfg_mac_speed_dup_h(struct hnae3_handle *handle, int speed, { struct hclge_vport *vport = hclge_get_vport(handle); struct hclge_dev *hdev = vport->back; + int ret; + + ret = hclge_cfg_mac_speed_dup(hdev, speed, duplex, lane_num); + + if (ret) + return ret; - return hclge_cfg_mac_speed_dup(hdev, speed, duplex, lane_num); + hdev->hw.mac.req_speed = (u32)speed; + hdev->hw.mac.req_duplex = duplex; + + return 0; } static int hclge_set_autoneg_en(struct hclge_dev *hdev, bool enable) @@ -2907,17 +2957,20 @@ static int hclge_mac_init(struct hclge_dev *hdev) if (!test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) hdev->hw.mac.duplex = HCLGE_MAC_FULL; - ret = hclge_cfg_mac_speed_dup_hw(hdev, hdev->hw.mac.speed, - hdev->hw.mac.duplex, hdev->hw.mac.lane_num); - if (ret) - return ret; - if (hdev->hw.mac.support_autoneg) { ret = hclge_set_autoneg_en(hdev, hdev->hw.mac.autoneg); if (ret) return ret; } + if (!hdev->hw.mac.autoneg) { + ret = hclge_cfg_mac_speed_dup_hw(hdev, hdev->hw.mac.req_speed, + hdev->hw.mac.req_duplex, + hdev->hw.mac.lane_num); + if (ret) + return ret; + } + mac->link = 0; if (mac->user_fec_mode & BIT(HNAE3_FEC_USER_DEF)) { @@ -3037,9 +3090,7 @@ static void hclge_push_link_status(struct hclge_dev *hdev) static void hclge_update_link_status(struct hclge_dev *hdev) { - struct hnae3_handle *rhandle = &hdev->vport[0].roce; struct hnae3_handle *handle = &hdev->vport[0].nic; - struct hnae3_client *rclient = hdev->roce_client; struct hnae3_client *client = hdev->nic_client; int state; int ret; @@ -3063,8 +3114,15 @@ static void hclge_update_link_status(struct hclge_dev *hdev) client->ops->link_status_change(handle, state); hclge_config_mac_tnl_int(hdev, state); - if (rclient && rclient->ops->link_status_change) - rclient->ops->link_status_change(rhandle, state); + + if (test_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state)) { + struct hnae3_handle *rhandle = &hdev->vport[0].roce; + struct hnae3_client *rclient = hdev->roce_client; + + if (rclient && rclient->ops->link_status_change) + rclient->ops->link_status_change(rhandle, + state); + } hclge_push_link_status(hdev); } @@ -3342,9 +3400,9 @@ hclge_set_phy_link_ksettings(struct hnae3_handle *handle, return ret; } - hdev->hw.mac.autoneg = cmd->base.autoneg; - hdev->hw.mac.speed = cmd->base.speed; - hdev->hw.mac.duplex = cmd->base.duplex; + hdev->hw.mac.req_autoneg = cmd->base.autoneg; + hdev->hw.mac.req_speed = cmd->base.speed; + hdev->hw.mac.req_duplex = cmd->base.duplex; linkmode_copy(hdev->hw.mac.advertising, cmd->link_modes.advertising); return 0; @@ -3377,9 +3435,9 @@ static int hclge_tp_port_init(struct hclge_dev *hdev) if (!hnae3_dev_phy_imp_supported(hdev)) return 0; - cmd.base.autoneg = hdev->hw.mac.autoneg; - cmd.base.speed = hdev->hw.mac.speed; - cmd.base.duplex = hdev->hw.mac.duplex; + cmd.base.autoneg = hdev->hw.mac.req_autoneg; + cmd.base.speed = hdev->hw.mac.req_speed; + cmd.base.duplex = hdev->hw.mac.req_duplex; linkmode_copy(cmd.link_modes.advertising, hdev->hw.mac.advertising); return hclge_set_phy_link_ksettings(&hdev->vport->nic, &cmd); @@ -3388,7 +3446,7 @@ static int hclge_tp_port_init(struct hclge_dev *hdev) static int hclge_update_port_info(struct hclge_dev *hdev) { struct hclge_mac *mac = &hdev->hw.mac; - int speed; + u32 speed; int ret; /* get the port info from SFP cmd if not copper port */ @@ -3517,6 +3575,17 @@ static int hclge_set_vf_link_state(struct hnae3_handle *handle, int vf, return ret; } +static void hclge_set_reset_pending(struct hclge_dev *hdev, + enum hnae3_reset_type reset_type) +{ + /* When an incorrect reset type is executed, the get_reset_level + * function generates the HNAE3_NONE_RESET flag. As a result, this + * type do not need to pending. + */ + if (reset_type != HNAE3_NONE_RESET) + set_bit(reset_type, &hdev->reset_pending); +} + static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval) { u32 cmdq_src_reg, msix_src_reg, hw_err_src_reg; @@ -3537,7 +3606,7 @@ static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval) */ if (BIT(HCLGE_VECTOR0_IMPRESET_INT_B) & msix_src_reg) { dev_info(&hdev->pdev->dev, "IMP reset interrupt\n"); - set_bit(HNAE3_IMP_RESET, &hdev->reset_pending); + hclge_set_reset_pending(hdev, HNAE3_IMP_RESET); set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); *clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B); hdev->rst_stats.imp_rst_cnt++; @@ -3547,7 +3616,7 @@ static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval) if (BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) & msix_src_reg) { dev_info(&hdev->pdev->dev, "global reset interrupt\n"); set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); - set_bit(HNAE3_GLOBAL_RESET, &hdev->reset_pending); + hclge_set_reset_pending(hdev, HNAE3_GLOBAL_RESET); *clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B); hdev->rst_stats.global_rst_cnt++; return HCLGE_VECTOR0_EVENT_RST; @@ -3702,7 +3771,7 @@ static int hclge_misc_irq_init(struct hclge_dev *hdev) snprintf(hdev->misc_vector.name, HNAE3_INT_NAME_LEN, "%s-misc-%s", HCLGE_NAME, pci_name(hdev->pdev)); ret = request_irq(hdev->misc_vector.vector_irq, hclge_misc_irq_handle, - 0, hdev->misc_vector.name, hdev); + IRQF_NO_AUTOEN, hdev->misc_vector.name, hdev); if (ret) { hclge_free_vector(hdev, 0); dev_err(&hdev->pdev->dev, "request misc irq(%d) fail\n", @@ -3995,7 +4064,7 @@ static void hclge_do_reset(struct hclge_dev *hdev) case HNAE3_FUNC_RESET: dev_info(&pdev->dev, "PF reset requested\n"); /* schedule again to check later */ - set_bit(HNAE3_FUNC_RESET, &hdev->reset_pending); + hclge_set_reset_pending(hdev, HNAE3_FUNC_RESET); hclge_reset_task_schedule(hdev); break; default: @@ -4029,6 +4098,8 @@ static enum hnae3_reset_type hclge_get_reset_level(struct hnae3_ae_dev *ae_dev, clear_bit(HNAE3_FLR_RESET, addr); } + clear_bit(HNAE3_NONE_RESET, addr); + if (hdev->reset_type != HNAE3_NONE_RESET && rst_level < hdev->reset_type) return HNAE3_NONE_RESET; @@ -4170,7 +4241,7 @@ static bool hclge_reset_err_handle(struct hclge_dev *hdev) return false; } else if (hdev->rst_stats.reset_fail_cnt < MAX_RESET_FAIL_CNT) { hdev->rst_stats.reset_fail_cnt++; - set_bit(hdev->reset_type, &hdev->reset_pending); + hclge_set_reset_pending(hdev, hdev->reset_type); dev_info(&hdev->pdev->dev, "re-schedule reset task(%u)\n", hdev->rst_stats.reset_fail_cnt); @@ -4413,14 +4484,26 @@ static void hclge_reset_event(struct pci_dev *pdev, struct hnae3_handle *handle) static void hclge_set_def_reset_request(struct hnae3_ae_dev *ae_dev, enum hnae3_reset_type rst_type) { +#define HCLGE_SUPPORT_RESET_TYPE \ + (BIT(HNAE3_FLR_RESET) | BIT(HNAE3_FUNC_RESET) | \ + BIT(HNAE3_GLOBAL_RESET) | BIT(HNAE3_IMP_RESET)) + struct hclge_dev *hdev = ae_dev->priv; + if (!(BIT(rst_type) & HCLGE_SUPPORT_RESET_TYPE)) { + /* To prevent reset triggered by hclge_reset_event */ + set_bit(HNAE3_NONE_RESET, &hdev->default_reset_request); + dev_warn(&hdev->pdev->dev, "unsupported reset type %d\n", + rst_type); + return; + } + set_bit(rst_type, &hdev->default_reset_request); } static void hclge_reset_timer(struct timer_list *t) { - struct hclge_dev *hdev = from_timer(hdev, t, reset_timer); + struct hclge_dev *hdev = timer_container_of(hdev, t, reset_timer); /* if default_reset_request has no value, it means that this reset * request has already be handled, so just return here @@ -4789,7 +4872,7 @@ static int hclge_set_rss(struct hnae3_handle *handle, const u32 *indir, } static int hclge_set_rss_tuple(struct hnae3_handle *handle, - struct ethtool_rxnfc *nfc) + const struct ethtool_rxfh_fields *nfc) { struct hclge_vport *vport = hclge_get_vport(handle); struct hclge_dev *hdev = vport->back; @@ -4807,7 +4890,7 @@ static int hclge_set_rss_tuple(struct hnae3_handle *handle, } static int hclge_get_rss_tuple(struct hnae3_handle *handle, - struct ethtool_rxnfc *nfc) + struct ethtool_rxfh_fields *nfc) { struct hclge_vport *vport = hclge_get_vport(handle); u8 tuple_sets; @@ -6224,15 +6307,15 @@ static void hclge_fd_get_ip4_tuple(struct ethtool_rx_flow_spec *fs, static void hclge_fd_get_tcpip6_tuple(struct ethtool_rx_flow_spec *fs, struct hclge_fd_rule *rule, u8 ip_proto) { - be32_to_cpu_array(rule->tuples.src_ip, fs->h_u.tcp_ip6_spec.ip6src, - IPV6_SIZE); - be32_to_cpu_array(rule->tuples_mask.src_ip, fs->m_u.tcp_ip6_spec.ip6src, - IPV6_SIZE); + ipv6_addr_be32_to_cpu(rule->tuples.src_ip, + fs->h_u.tcp_ip6_spec.ip6src); + ipv6_addr_be32_to_cpu(rule->tuples_mask.src_ip, + fs->m_u.tcp_ip6_spec.ip6src); - be32_to_cpu_array(rule->tuples.dst_ip, fs->h_u.tcp_ip6_spec.ip6dst, - IPV6_SIZE); - be32_to_cpu_array(rule->tuples_mask.dst_ip, fs->m_u.tcp_ip6_spec.ip6dst, - IPV6_SIZE); + ipv6_addr_be32_to_cpu(rule->tuples.dst_ip, + fs->h_u.tcp_ip6_spec.ip6dst); + ipv6_addr_be32_to_cpu(rule->tuples_mask.dst_ip, + fs->m_u.tcp_ip6_spec.ip6dst); rule->tuples.src_port = be16_to_cpu(fs->h_u.tcp_ip6_spec.psrc); rule->tuples_mask.src_port = be16_to_cpu(fs->m_u.tcp_ip6_spec.psrc); @@ -6253,15 +6336,15 @@ static void hclge_fd_get_tcpip6_tuple(struct ethtool_rx_flow_spec *fs, static void hclge_fd_get_ip6_tuple(struct ethtool_rx_flow_spec *fs, struct hclge_fd_rule *rule) { - be32_to_cpu_array(rule->tuples.src_ip, fs->h_u.usr_ip6_spec.ip6src, - IPV6_SIZE); - be32_to_cpu_array(rule->tuples_mask.src_ip, fs->m_u.usr_ip6_spec.ip6src, - IPV6_SIZE); + ipv6_addr_be32_to_cpu(rule->tuples.src_ip, + fs->h_u.usr_ip6_spec.ip6src); + ipv6_addr_be32_to_cpu(rule->tuples_mask.src_ip, + fs->m_u.usr_ip6_spec.ip6src); - be32_to_cpu_array(rule->tuples.dst_ip, fs->h_u.usr_ip6_spec.ip6dst, - IPV6_SIZE); - be32_to_cpu_array(rule->tuples_mask.dst_ip, fs->m_u.usr_ip6_spec.ip6dst, - IPV6_SIZE); + ipv6_addr_be32_to_cpu(rule->tuples.dst_ip, + fs->h_u.usr_ip6_spec.ip6dst); + ipv6_addr_be32_to_cpu(rule->tuples_mask.dst_ip, + fs->m_u.usr_ip6_spec.ip6dst); rule->tuples.ip_proto = fs->h_u.usr_ip6_spec.l4_proto; rule->tuples_mask.ip_proto = fs->m_u.usr_ip6_spec.l4_proto; @@ -6690,21 +6773,19 @@ static void hclge_fd_get_tcpip6_info(struct hclge_fd_rule *rule, struct ethtool_tcpip6_spec *spec, struct ethtool_tcpip6_spec *spec_mask) { - cpu_to_be32_array(spec->ip6src, - rule->tuples.src_ip, IPV6_SIZE); - cpu_to_be32_array(spec->ip6dst, - rule->tuples.dst_ip, IPV6_SIZE); + ipv6_addr_cpu_to_be32(spec->ip6src, rule->tuples.src_ip); + ipv6_addr_cpu_to_be32(spec->ip6dst, rule->tuples.dst_ip); if (rule->unused_tuple & BIT(INNER_SRC_IP)) memset(spec_mask->ip6src, 0, sizeof(spec_mask->ip6src)); else - cpu_to_be32_array(spec_mask->ip6src, rule->tuples_mask.src_ip, - IPV6_SIZE); + ipv6_addr_cpu_to_be32(spec_mask->ip6src, + rule->tuples_mask.src_ip); if (rule->unused_tuple & BIT(INNER_DST_IP)) memset(spec_mask->ip6dst, 0, sizeof(spec_mask->ip6dst)); else - cpu_to_be32_array(spec_mask->ip6dst, rule->tuples_mask.dst_ip, - IPV6_SIZE); + ipv6_addr_cpu_to_be32(spec_mask->ip6dst, + rule->tuples_mask.dst_ip); spec->tclass = rule->tuples.ip_tos; spec_mask->tclass = rule->unused_tuple & BIT(INNER_IP_TOS) ? @@ -6723,19 +6804,19 @@ static void hclge_fd_get_ip6_info(struct hclge_fd_rule *rule, struct ethtool_usrip6_spec *spec, struct ethtool_usrip6_spec *spec_mask) { - cpu_to_be32_array(spec->ip6src, rule->tuples.src_ip, IPV6_SIZE); - cpu_to_be32_array(spec->ip6dst, rule->tuples.dst_ip, IPV6_SIZE); + ipv6_addr_cpu_to_be32(spec->ip6src, rule->tuples.src_ip); + ipv6_addr_cpu_to_be32(spec->ip6dst, rule->tuples.dst_ip); if (rule->unused_tuple & BIT(INNER_SRC_IP)) memset(spec_mask->ip6src, 0, sizeof(spec_mask->ip6src)); else - cpu_to_be32_array(spec_mask->ip6src, - rule->tuples_mask.src_ip, IPV6_SIZE); + ipv6_addr_cpu_to_be32(spec_mask->ip6src, + rule->tuples_mask.src_ip); if (rule->unused_tuple & BIT(INNER_DST_IP)) memset(spec_mask->ip6dst, 0, sizeof(spec_mask->ip6dst)); else - cpu_to_be32_array(spec_mask->ip6dst, - rule->tuples_mask.dst_ip, IPV6_SIZE); + ipv6_addr_cpu_to_be32(spec_mask->ip6dst, + rule->tuples_mask.dst_ip); spec->tclass = rule->tuples.ip_tos; spec_mask->tclass = rule->unused_tuple & BIT(INNER_IP_TOS) ? @@ -6908,7 +6989,7 @@ static int hclge_get_all_rules(struct hnae3_handle *handle, struct hclge_dev *hdev = vport->back; struct hclge_fd_rule *rule; struct hlist_node *node2; - int cnt = 0; + u32 cnt = 0; if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) return -EOPNOTSUPP; @@ -6953,7 +7034,7 @@ static void hclge_fd_get_flow_tuples(const struct flow_keys *fkeys, } else { int i; - for (i = 0; i < IPV6_SIZE; i++) { + for (i = 0; i < IPV6_ADDR_WORDS; i++) { tuples->src_ip[i] = be32_to_cpu(flow_ip6_src[i]); tuples->dst_ip[i] = be32_to_cpu(flow_ip6_dst[i]); } @@ -7178,8 +7259,9 @@ static void hclge_get_cls_key_vlan(const struct flow_rule *flow, } } -static void hclge_get_cls_key_ip(const struct flow_rule *flow, - struct hclge_fd_rule *rule) +static int hclge_get_cls_key_ip(const struct flow_rule *flow, + struct hclge_fd_rule *rule, + struct netlink_ext_ack *extack) { u16 addr_type = 0; @@ -7188,6 +7270,9 @@ static void hclge_get_cls_key_ip(const struct flow_rule *flow, flow_rule_match_control(flow, &match); addr_type = match.key->addr_type; + + if (flow_rule_has_control_flags(match.mask->flags, extack)) + return -EOPNOTSUPP; } if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) { @@ -7204,18 +7289,20 @@ static void hclge_get_cls_key_ip(const struct flow_rule *flow, struct flow_match_ipv6_addrs match; flow_rule_match_ipv6_addrs(flow, &match); - be32_to_cpu_array(rule->tuples.src_ip, match.key->src.s6_addr32, - IPV6_SIZE); - be32_to_cpu_array(rule->tuples_mask.src_ip, - match.mask->src.s6_addr32, IPV6_SIZE); - be32_to_cpu_array(rule->tuples.dst_ip, match.key->dst.s6_addr32, - IPV6_SIZE); - be32_to_cpu_array(rule->tuples_mask.dst_ip, - match.mask->dst.s6_addr32, IPV6_SIZE); + ipv6_addr_be32_to_cpu(rule->tuples.src_ip, + match.key->src.s6_addr32); + ipv6_addr_be32_to_cpu(rule->tuples_mask.src_ip, + match.mask->src.s6_addr32); + ipv6_addr_be32_to_cpu(rule->tuples.dst_ip, + match.key->dst.s6_addr32); + ipv6_addr_be32_to_cpu(rule->tuples_mask.dst_ip, + match.mask->dst.s6_addr32); } else { rule->unused_tuple |= BIT(INNER_SRC_IP); rule->unused_tuple |= BIT(INNER_DST_IP); } + + return 0; } static void hclge_get_cls_key_port(const struct flow_rule *flow, @@ -7241,7 +7328,9 @@ static int hclge_parse_cls_flower(struct hclge_dev *hdev, struct hclge_fd_rule *rule) { struct flow_rule *flow = flow_cls_offload_flow_rule(cls_flower); + struct netlink_ext_ack *extack = cls_flower->common.extack; struct flow_dissector *dissector = flow->match.dissector; + int ret; if (dissector->used_keys & ~(BIT_ULL(FLOW_DISSECTOR_KEY_CONTROL) | @@ -7259,7 +7348,11 @@ static int hclge_parse_cls_flower(struct hclge_dev *hdev, hclge_get_cls_key_basic(flow, rule); hclge_get_cls_key_mac(flow, rule); hclge_get_cls_key_vlan(flow, rule); - hclge_get_cls_key_ip(flow, rule); + + ret = hclge_get_cls_key_ip(flow, rule, extack); + if (ret) + return ret; + hclge_get_cls_key_port(flow, rule); return 0; @@ -7782,7 +7875,7 @@ static int hclge_enable_phy_loopback(struct hclge_dev *hdev, if (ret) return ret; - return phy_loopback(phydev, true); + return phy_loopback(phydev, true, 0); } static int hclge_disable_phy_loopback(struct hclge_dev *hdev, @@ -7790,7 +7883,7 @@ static int hclge_disable_phy_loopback(struct hclge_dev *hdev, { int ret; - ret = phy_loopback(phydev, false); + ret = phy_loopback(phydev, false, 0); if (ret) return ret; @@ -7907,7 +8000,7 @@ static int hclge_set_loopback(struct hnae3_handle *handle, ret = hclge_tqp_enable(handle, en); if (ret) dev_err(&hdev->pdev->dev, "failed to %s tqp in loopback, ret = %d\n", - en ? "enable" : "disable", ret); + str_enable_disable(en), ret); return ret; } @@ -7952,8 +8045,7 @@ static void hclge_set_timer_task(struct hnae3_handle *handle, bool enable) /* Set the DOWN flag here to disable link updating */ set_bit(HCLGE_STATE_DOWN, &hdev->state); - /* flush memory to make sure DOWN is seen by service task */ - smp_mb__before_atomic(); + smp_mb__after_atomic(); /* flush memory to make sure DOWN is seen by service task */ hclge_flush_link_update(hdev); } } @@ -8131,14 +8223,14 @@ static int hclge_update_desc_vfid(struct hclge_desc *desc, int vfid, bool clr) word_num = vfid / 32; bit_num = vfid % 32; if (clr) - desc[1].data[word_num] &= cpu_to_le32(~(1 << bit_num)); + desc[1].data[word_num] &= cpu_to_le32(~(1U << bit_num)); else desc[1].data[word_num] |= cpu_to_le32(1 << bit_num); } else { word_num = (vfid - HCLGE_VF_NUM_IN_FIRST_DESC) / 32; bit_num = vfid % 32; if (clr) - desc[2].data[word_num] &= cpu_to_le32(~(1 << bit_num)); + desc[2].data[word_num] &= cpu_to_le32(~(1U << bit_num)); else desc[2].data[word_num] |= cpu_to_le32(1 << bit_num); } @@ -9200,7 +9292,7 @@ static int hclge_add_mgr_tbl(struct hclge_dev *hdev, static int init_mgr_tbl(struct hclge_dev *hdev) { int ret; - int i; + u32 i; for (i = 0; i < ARRAY_SIZE(hclge_mgr_table); i++) { ret = hclge_add_mgr_tbl(hdev, &hclge_mgr_table[i]); @@ -9484,33 +9576,36 @@ static bool hclge_need_enable_vport_vlan_filter(struct hclge_vport *vport) return false; } -int hclge_enable_vport_vlan_filter(struct hclge_vport *vport, bool request_en) +static int __hclge_enable_vport_vlan_filter(struct hclge_vport *vport, + bool request_en) { - struct hclge_dev *hdev = vport->back; bool need_en; int ret; - mutex_lock(&hdev->vport_lock); - - vport->req_vlan_fltr_en = request_en; - need_en = hclge_need_enable_vport_vlan_filter(vport); - if (need_en == vport->cur_vlan_fltr_en) { - mutex_unlock(&hdev->vport_lock); + if (need_en == vport->cur_vlan_fltr_en) return 0; - } ret = hclge_set_vport_vlan_filter(vport, need_en); - if (ret) { - mutex_unlock(&hdev->vport_lock); + if (ret) return ret; - } vport->cur_vlan_fltr_en = need_en; + return 0; +} + +int hclge_enable_vport_vlan_filter(struct hclge_vport *vport, bool request_en) +{ + struct hclge_dev *hdev = vport->back; + int ret; + + mutex_lock(&hdev->vport_lock); + vport->req_vlan_fltr_en = request_en; + ret = __hclge_enable_vport_vlan_filter(vport, request_en); mutex_unlock(&hdev->vport_lock); - return 0; + return ret; } static int hclge_enable_vlan_filter(struct hnae3_handle *handle, bool enable) @@ -9906,6 +10001,7 @@ static int hclge_set_vlan_protocol_type(struct hclge_dev *hdev) static int hclge_init_vlan_filter(struct hclge_dev *hdev) { struct hclge_vport *vport; + bool enable = true; int ret; int i; @@ -9925,8 +10021,12 @@ static int hclge_init_vlan_filter(struct hclge_dev *hdev) vport->cur_vlan_fltr_en = true; } + if (test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, hdev->ae_dev->caps) && + !test_bit(HNAE3_DEV_SUPPORT_PORT_VLAN_BYPASS_B, hdev->ae_dev->caps)) + enable = false; + return hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_PORT, - HCLGE_FILTER_FE_INGRESS, true, 0); + HCLGE_FILTER_FE_INGRESS, enable, 0); } static int hclge_init_vlan_type(struct hclge_dev *hdev) @@ -10526,16 +10626,19 @@ static void hclge_sync_vlan_fltr_state(struct hclge_dev *hdev) &vport->state)) continue; - ret = hclge_enable_vport_vlan_filter(vport, - vport->req_vlan_fltr_en); + mutex_lock(&hdev->vport_lock); + ret = __hclge_enable_vport_vlan_filter(vport, + vport->req_vlan_fltr_en); if (ret) { dev_err(&hdev->pdev->dev, "failed to sync vlan filter state for vport%u, ret = %d\n", vport->vport_id, ret); set_bit(HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE, &vport->state); + mutex_unlock(&hdev->vport_lock); return; } + mutex_unlock(&hdev->vport_lock); } } @@ -10616,7 +10719,7 @@ int hclge_set_vport_mtu(struct hclge_vport *vport, int new_mtu) max_frm_size = max(max_frm_size, HCLGE_MAC_DEFAULT_FRAME); mutex_lock(&hdev->vport_lock); /* VF's mps must fit within hdev->mps */ - if (vport->vport_id && max_frm_size > hdev->mps) { + if (vport->vport_id && (u32)max_frm_size > hdev->mps) { mutex_unlock(&hdev->vport_lock); return -EINVAL; } else if (vport->vport_id) { @@ -10627,7 +10730,7 @@ int hclge_set_vport_mtu(struct hclge_vport *vport, int new_mtu) /* PF's mps must be greater then VF's mps */ for (i = 1; i < hdev->num_alloc_vport; i++) - if (max_frm_size < hdev->vport[i].mps) { + if ((u32)max_frm_size < hdev->vport[i].mps) { dev_err(&hdev->pdev->dev, "failed to set pf mtu for less than vport %d, mps = %u.\n", i, hdev->vport[i].mps); @@ -10839,6 +10942,24 @@ static u32 hclge_get_fw_version(struct hnae3_handle *handle) return hdev->fw_version; } +int hclge_query_scc_version(struct hclge_dev *hdev, u32 *scc_version) +{ + struct hclge_comm_query_scc_cmd *resp; + struct hclge_desc desc; + int ret; + + hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_SCC_VER, 1); + resp = (struct hclge_comm_query_scc_cmd *)desc.data; + + ret = hclge_cmd_send(&hdev->hw, &desc, 1); + if (ret) + return ret; + + *scc_version = le32_to_cpu(resp->scc_version); + + return 0; +} + static void hclge_set_flowctrl_adv(struct hclge_dev *hdev, u32 rx_en, u32 tx_en) { struct phy_device *phydev = hdev->hw.mac.phydev; @@ -11085,9 +11206,9 @@ static void hclge_info_show(struct hclge_dev *hdev) dev_info(dev, "This is %s PF\n", hdev->flag & HCLGE_FLAG_MAIN ? "main" : "not main"); dev_info(dev, "DCB %s\n", - handle->kinfo.tc_info.dcb_ets_active ? "enable" : "disable"); + str_enable_disable(handle->kinfo.tc_info.dcb_ets_active)); dev_info(dev, "MQPRIO %s\n", - handle->kinfo.tc_info.mqprio_active ? "enable" : "disable"); + str_enable_disable(handle->kinfo.tc_info.mqprio_active)); dev_info(dev, "Default tx spare buffer size: %u\n", hdev->tx_spare_buf_size); @@ -11099,7 +11220,7 @@ static int hclge_init_nic_client_instance(struct hnae3_ae_dev *ae_dev, { struct hnae3_client *client = vport->nic.client; struct hclge_dev *hdev = ae_dev->priv; - int rst_cnt = hdev->rst_stats.reset_cnt; + u32 rst_cnt = hdev->rst_stats.reset_cnt; int ret; ret = client->ops->init_instance(&vport->nic); @@ -11143,7 +11264,7 @@ static int hclge_init_roce_client_instance(struct hnae3_ae_dev *ae_dev, { struct hclge_dev *hdev = ae_dev->priv; struct hnae3_client *client; - int rst_cnt; + u32 rst_cnt; int ret; if (!hnae3_dev_roce_supported(hdev) || !hdev->roce_client || @@ -11236,6 +11357,12 @@ clear_roce: return ret; } +static bool hclge_uninit_need_wait(struct hclge_dev *hdev) +{ + return test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) || + test_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state); +} + static void hclge_uninit_client_instance(struct hnae3_client *client, struct hnae3_ae_dev *ae_dev) { @@ -11244,7 +11371,7 @@ static void hclge_uninit_client_instance(struct hnae3_client *client, if (hdev->roce_client) { clear_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state); - while (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) + while (hclge_uninit_need_wait(hdev)) msleep(HCLGE_WAIT_RESET_DONE); hdev->roce_client->ops->uninit_instance(&vport->roce, 0); @@ -11302,7 +11429,7 @@ static int hclge_pci_init(struct hclge_dev *hdev) ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); if (ret) { dev_err(&pdev->dev, - "can't set consistent PCI DMA"); + "can't set consistent PCI DMA\n"); goto err_disable_device; } dev_warn(&pdev->dev, "set DMA mask to 32 bits\n"); @@ -11350,7 +11477,7 @@ static void hclge_pci_uninit(struct hclge_dev *hdev) pcim_iounmap(pdev, hdev->hw.hw.io_base); pci_free_irq_vectors(pdev); - pci_release_mem_regions(pdev); + pci_release_regions(pdev); pci_disable_device(pdev); } @@ -11371,7 +11498,7 @@ static void hclge_state_uninit(struct hclge_dev *hdev) set_bit(HCLGE_STATE_REMOVING, &hdev->state); if (hdev->reset_timer.function) - del_timer_sync(&hdev->reset_timer); + timer_delete_sync(&hdev->reset_timer); if (hdev->service_task.work.func) cancel_delayed_work_sync(&hdev->service_task); } @@ -11422,8 +11549,8 @@ static void hclge_reset_done(struct hnae3_ae_dev *ae_dev) dev_err(&hdev->pdev->dev, "fail to rebuild, ret=%d\n", ret); hdev->reset_type = HNAE3_NONE_RESET; - clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); - up(&hdev->reset_sem); + if (test_and_clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) + up(&hdev->reset_sem); } static void hclge_clear_resetting_state(struct hclge_dev *hdev) @@ -11622,16 +11749,13 @@ static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev) if (ret) goto out; - ret = hclge_devlink_init(hdev); - if (ret) - goto err_pci_uninit; - /* Firmware command queue initialize */ ret = hclge_comm_cmd_queue_init(hdev->pdev, &hdev->hw.hw); if (ret) - goto err_devlink_uninit; + goto err_pci_uninit; /* Firmware command initialize */ + hclge_comm_cmd_init_ops(&hdev->hw.hw, &hclge_cmq_ops); ret = hclge_comm_cmd_init(hdev->ae_dev, &hdev->hw.hw, &hdev->fw_version, true, hdev->reset_pending); if (ret) @@ -11757,7 +11881,7 @@ static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev) ret = hclge_update_port_info(hdev); if (ret) - goto err_mdiobus_unreg; + goto err_ptp_uninit; INIT_KFIFO(hdev->mac_tnl_log); @@ -11789,24 +11913,30 @@ static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev) hclge_init_rxd_adv_layout(hdev); - /* Enable MISC vector(vector0) */ - hclge_enable_vector(&hdev->misc_vector, true); - ret = hclge_init_wol(hdev); if (ret) dev_warn(&pdev->dev, "failed to wake on lan init, ret = %d\n", ret); + ret = hclge_devlink_init(hdev); + if (ret) + goto err_ptp_uninit; + hclge_state_init(hdev); hdev->last_reset_time = jiffies; + /* Enable MISC vector(vector0) */ + enable_irq(hdev->misc_vector.vector_irq); + hclge_enable_vector(&hdev->misc_vector, true); + dev_info(&hdev->pdev->dev, "%s driver initialization finished.\n", HCLGE_DRIVER_NAME); hclge_task_schedule(hdev, round_jiffies_relative(HZ)); - return 0; +err_ptp_uninit: + hclge_ptp_uninit(hdev); err_mdiobus_unreg: if (hdev->hw.mac.phydev) mdiobus_unregister(hdev->hw.mac.mdio_bus); @@ -11816,8 +11946,6 @@ err_msi_uninit: pci_free_irq_vectors(pdev); err_cmd_uninit: hclge_comm_cmd_uninit(hdev->ae_dev, &hdev->hw.hw); -err_devlink_uninit: - hclge_devlink_uninit(hdev); err_pci_uninit: pcim_iounmap(pdev, hdev->hw.hw.io_base); pci_release_regions(pdev); @@ -11854,7 +11982,7 @@ static int hclge_set_vf_spoofchk_hw(struct hclge_dev *hdev, int vf, bool enable) if (ret) { dev_err(&hdev->pdev->dev, "Set vf %d mac spoof check %s failed, ret=%d\n", - vf, enable ? "on" : "off", ret); + vf, str_on_off(enable), ret); return ret; } @@ -11862,7 +11990,7 @@ static int hclge_set_vf_spoofchk_hw(struct hclge_dev *hdev, int vf, bool enable) if (ret) dev_err(&hdev->pdev->dev, "Set vf %d vlan spoof check %s failed, ret=%d\n", - vf, enable ? "on" : "off", ret); + vf, str_on_off(enable), ret); return ret; } @@ -11966,7 +12094,7 @@ static int hclge_vf_rate_param_check(struct hclge_dev *hdev, int min_tx_rate, int max_tx_rate) { if (min_tx_rate != 0 || - max_tx_rate < 0 || max_tx_rate > hdev->hw.mac.max_speed) { + max_tx_rate < 0 || (u32)max_tx_rate > hdev->hw.mac.max_speed) { dev_err(&hdev->pdev->dev, "min_tx_rate:%d [0], max_tx_rate:%d [0, %u]\n", min_tx_rate, max_tx_rate, hdev->hw.mac.max_speed); @@ -11991,7 +12119,7 @@ static int hclge_set_vf_rate(struct hnae3_handle *handle, int vf, if (!vport) return -EINVAL; - if (!force && max_tx_rate == vport->vf_info.max_tx_rate) + if (!force && (u32)max_tx_rate == vport->vf_info.max_tx_rate) return 0; ret = hclge_tm_qs_shaper_cfg(vport, max_tx_rate); @@ -12206,7 +12334,7 @@ static void hclge_uninit_ae_dev(struct hnae3_ae_dev *ae_dev) /* Disable MISC vector(vector0) */ hclge_enable_vector(&hdev->misc_vector, false); - synchronize_irq(hdev->misc_vector.vector_irq); + disable_irq(hdev->misc_vector.vector_irq); /* Disable all hw interrupts */ hclge_config_mac_tnl_int(hdev, false); @@ -12742,7 +12870,7 @@ static const struct hnae3_ae_ops hclge_ops = { .get_fd_all_rules = hclge_get_all_rules, .enable_fd = hclge_enable_fd, .add_arfs_entry = hclge_add_fd_entry_by_arfs, - .dbg_read_cmd = hclge_dbg_read_cmd, + .dbg_get_read_func = hclge_dbg_get_read_func, .handle_hw_ras_error = hclge_handle_hw_ras_error, .get_hw_reset_stat = hclge_get_hw_reset_stat, .ae_dev_resetting = hclge_ae_dev_resetting, @@ -12782,7 +12910,7 @@ static struct hnae3_ae_algo ae_algo = { static int __init hclge_init(void) { - pr_info("%s is initializing\n", HCLGE_NAME); + pr_debug("%s is initializing\n", HCLGE_NAME); hclge_wq = alloc_workqueue("%s", WQ_UNBOUND, 0, HCLGE_NAME); if (!hclge_wq) { @@ -12797,9 +12925,11 @@ static int __init hclge_init(void) static void __exit hclge_exit(void) { + hnae3_acquire_unload_lock(); hnae3_unregister_ae_algo_prepare(&ae_algo); hnae3_unregister_ae_algo(&ae_algo); destroy_workqueue(hclge_wq); + hnae3_release_unload_lock(); } module_init(hclge_init); module_exit(hclge_exit); diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h index e821dd2f1528..032b472d2368 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h @@ -8,7 +8,9 @@ #include <linux/phy.h> #include <linux/if_vlan.h> #include <linux/kfifo.h> + #include <net/devlink.h> +#include <net/ipv6.h> #include "hclge_cmd.h" #include "hclge_ptp.h" @@ -279,11 +281,14 @@ struct hclge_mac { u8 media_type; /* port media type, e.g. fibre/copper/backplane */ u8 mac_addr[ETH_ALEN]; u8 autoneg; + u8 req_autoneg; u8 duplex; + u8 req_duplex; u8 support_autoneg; u8 speed_type; /* 0: sfp speed, 1: active speed */ u8 lane_num; u32 speed; + u32 req_speed; u32 max_speed; u32 speed_ability; /* speed ability supported by current media */ u32 module_type; /* sub media type, e.g. kr/cr/sr/lr */ @@ -715,15 +720,15 @@ struct hclge_fd_cfg { }; #define IPV4_INDEX 3 -#define IPV6_SIZE 4 + struct hclge_fd_rule_tuples { u8 src_mac[ETH_ALEN]; u8 dst_mac[ETH_ALEN]; /* Be compatible for ip address of both ipv4 and ipv6. * For ipv4 address, we store it in src/dst_ip[3]. */ - u32 src_ip[IPV6_SIZE]; - u32 dst_ip[IPV6_SIZE]; + u32 src_ip[IPV6_ADDR_WORDS]; + u32 dst_ip[IPV6_ADDR_WORDS]; u16 src_port; u16 dst_port; u16 vlan_tag1; @@ -891,7 +896,7 @@ struct hclge_dev { u16 fdir_pf_filter_count; /* Num of guaranteed filters for this PF */ u16 num_alloc_vport; /* Num vports this driver supports */ - u32 numa_node_mask; + nodemask_t numa_node_mask; u16 rx_buf_len; u16 num_tx_desc; /* desc num of per tx queue */ u16 num_rx_desc; /* desc num of per rx queue */ @@ -1137,8 +1142,8 @@ int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id); int hclge_vport_start(struct hclge_vport *vport); void hclge_vport_stop(struct hclge_vport *vport); int hclge_set_vport_mtu(struct hclge_vport *vport, int new_mtu); -int hclge_dbg_read_cmd(struct hnae3_handle *handle, enum hnae3_dbg_cmd cmd, - char *buf, int len); +int hclge_dbg_get_read_func(struct hnae3_handle *handle, enum hnae3_dbg_cmd cmd, + read_func *func); u16 hclge_covert_handle_qid_global(struct hnae3_handle *handle, u16 queue_id); int hclge_notify_client(struct hclge_dev *hdev, enum hnae3_reset_notify_type type); @@ -1169,4 +1174,5 @@ int hclge_enable_vport_vlan_filter(struct hclge_vport *vport, bool request_en); int hclge_mac_update_stats(struct hclge_dev *hdev); struct hclge_vport *hclge_get_vf_vport(struct hclge_dev *hdev, int vf); int hclge_inform_vf_reset(struct hclge_vport *vport, u16 reset_type); +int hclge_query_scc_version(struct hclge_dev *hdev, u32 *scc_version); #endif diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mbx.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mbx.c index d4a0e0be7a72..c7ff12a6c076 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mbx.c +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mbx.c @@ -749,16 +749,17 @@ static int hclge_get_rss_key(struct hclge_vport *vport, #define HCLGE_RSS_MBX_RESP_LEN 8 struct hclge_dev *hdev = vport->back; struct hclge_comm_rss_cfg *rss_cfg; + int rss_hash_key_size; u8 index; index = mbx_req->msg.data[0]; rss_cfg = &hdev->rss_cfg; + rss_hash_key_size = sizeof(rss_cfg->rss_hash_key); /* Check the query index of rss_hash_key from VF, make sure no * more than the size of rss_hash_key. */ - if (((index + 1) * HCLGE_RSS_MBX_RESP_LEN) > - sizeof(rss_cfg->rss_hash_key)) { + if (((index + 1) * HCLGE_RSS_MBX_RESP_LEN) > rss_hash_key_size) { dev_warn(&hdev->pdev->dev, "failed to get the rss hash key, the index(%u) invalid !\n", index); @@ -800,7 +801,7 @@ static void hclge_handle_link_change_event(struct hclge_dev *hdev, static bool hclge_cmd_crq_empty(struct hclge_hw *hw) { - u32 tail = hclge_read_dev(hw, HCLGE_COMM_NIC_CRQ_TAIL_REG); + int tail = hclge_read_dev(hw, HCLGE_COMM_NIC_CRQ_TAIL_REG); return tail == hw->hw.cmq.crq.next_to_use; } @@ -1077,12 +1078,13 @@ static void hclge_mbx_request_handling(struct hclge_mbx_ops_param *param) hdev = param->vport->back; cmd_func = hclge_mbx_ops_list[param->req->msg.code]; - if (cmd_func) - ret = cmd_func(param); - else + if (!cmd_func) { dev_err(&hdev->pdev->dev, "un-supported mailbox message, code = %u\n", param->req->msg.code); + return; + } + ret = cmd_func(param); /* PF driver should not reply IMP */ if (hnae3_get_bit(param->req->mbx_need_resp, HCLGE_MBX_NEED_RESP_B) && diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mdio.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mdio.c index 85fb11de43a1..96553109f44c 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mdio.c +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mdio.c @@ -151,7 +151,7 @@ int hclge_mac_mdio_config(struct hclge_dev *hdev) mdio_bus->parent = &hdev->pdev->dev; mdio_bus->priv = hdev; - mdio_bus->phy_mask = ~(1 << mac->phy_addr); + mdio_bus->phy_mask = ~(1U << mac->phy_addr); ret = mdiobus_register(mdio_bus); if (ret) { dev_err(mdio_bus->parent, @@ -191,6 +191,9 @@ static void hclge_mac_adjust_link(struct net_device *netdev) if (ret) netdev_err(netdev, "failed to adjust link.\n"); + hdev->hw.mac.req_speed = (u32)speed; + hdev->hw.mac.req_duplex = (u8)duplex; + ret = hclge_cfg_flowctrl(hdev); if (ret) netdev_err(netdev, "failed to configure flow control.\n"); @@ -255,7 +258,7 @@ void hclge_mac_start_phy(struct hclge_dev *hdev) if (!phydev) return; - phy_loopback(phydev, false); + phy_loopback(phydev, false, 0); phy_start(phydev); } diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ptp.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ptp.c index 507d7ce26d83..4bd52eab3914 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ptp.c +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ptp.c @@ -2,6 +2,7 @@ // Copyright (c) 2021 Hisilicon Limited. #include <linux/skbuff.h> +#include <linux/string_choices.h> #include "hclge_main.h" #include "hnae3.h" @@ -58,6 +59,9 @@ bool hclge_ptp_set_tx_info(struct hnae3_handle *handle, struct sk_buff *skb) struct hclge_dev *hdev = vport->back; struct hclge_ptp *ptp = hdev->ptp; + if (!ptp) + return false; + if (!test_bit(HCLGE_PTP_FLAG_TX_EN, &ptp->flags) || test_and_set_bit(HCLGE_STATE_PTP_TX_HANDLING, &hdev->state)) { ptp->tx_skipped++; @@ -223,7 +227,7 @@ static int hclge_ptp_int_en(struct hclge_dev *hdev, bool en) if (ret) dev_err(&hdev->pdev->dev, "failed to %s ptp interrupt, ret = %d\n", - en ? "enable" : "disable", ret); + str_enable_disable(en), ret); return ret; } @@ -378,7 +382,7 @@ int hclge_ptp_set_cfg(struct hclge_dev *hdev, struct ifreq *ifr) } int hclge_ptp_get_ts_info(struct hnae3_handle *handle, - struct ethtool_ts_info *info) + struct kernel_ethtool_ts_info *info) { struct hclge_vport *vport = hclge_get_vport(handle); struct hclge_dev *hdev = vport->back; @@ -389,16 +393,12 @@ int hclge_ptp_get_ts_info(struct hnae3_handle *handle, } info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | - SOF_TIMESTAMPING_RX_SOFTWARE | - SOF_TIMESTAMPING_SOFTWARE | SOF_TIMESTAMPING_TX_HARDWARE | SOF_TIMESTAMPING_RX_HARDWARE | SOF_TIMESTAMPING_RAW_HARDWARE; if (hdev->ptp->clock) info->phc_index = ptp_clock_index(hdev->ptp->clock); - else - info->phc_index = -1; info->tx_types = BIT(HWTSTAMP_TX_OFF) | BIT(HWTSTAMP_TX_ON); @@ -440,6 +440,13 @@ static int hclge_ptp_create_clock(struct hclge_dev *hdev) ptp->info.settime64 = hclge_ptp_settime; ptp->info.n_alarm = 0; + + spin_lock_init(&ptp->lock); + ptp->io_base = hdev->hw.hw.io_base + HCLGE_PTP_REG_OFFSET; + ptp->ts_cfg.rx_filter = HWTSTAMP_FILTER_NONE; + ptp->ts_cfg.tx_type = HWTSTAMP_TX_OFF; + hdev->ptp = ptp; + ptp->clock = ptp_clock_register(&ptp->info, &hdev->pdev->dev); if (IS_ERR(ptp->clock)) { dev_err(&hdev->pdev->dev, @@ -451,12 +458,6 @@ static int hclge_ptp_create_clock(struct hclge_dev *hdev) return -ENODEV; } - spin_lock_init(&ptp->lock); - ptp->io_base = hdev->hw.hw.io_base + HCLGE_PTP_REG_OFFSET; - ptp->ts_cfg.rx_filter = HWTSTAMP_FILTER_NONE; - ptp->ts_cfg.tx_type = HWTSTAMP_TX_OFF; - hdev->ptp = ptp; - return 0; } @@ -484,7 +485,7 @@ int hclge_ptp_init(struct hclge_dev *hdev) ret = hclge_ptp_get_cycle(hdev); if (ret) - return ret; + goto out; } ret = hclge_ptp_int_en(hdev, true); @@ -496,14 +497,14 @@ int hclge_ptp_init(struct hclge_dev *hdev) if (ret) { dev_err(&hdev->pdev->dev, "failed to init freq, ret = %d\n", ret); - goto out; + goto out_clear_int; } ret = hclge_ptp_set_ts_mode(hdev, &hdev->ptp->ts_cfg); if (ret) { dev_err(&hdev->pdev->dev, "failed to init ts mode, ret = %d\n", ret); - goto out; + goto out_clear_int; } ktime_get_real_ts64(&ts); @@ -511,7 +512,7 @@ int hclge_ptp_init(struct hclge_dev *hdev) if (ret) { dev_err(&hdev->pdev->dev, "failed to init ts time, ret = %d\n", ret); - goto out; + goto out_clear_int; } set_bit(HCLGE_STATE_PTP_EN, &hdev->state); @@ -519,6 +520,9 @@ int hclge_ptp_init(struct hclge_dev *hdev) return 0; +out_clear_int: + clear_bit(HCLGE_PTP_FLAG_EN, &hdev->ptp->flags); + hclge_ptp_int_en(hdev, false); out: hclge_ptp_destroy_clock(hdev); diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ptp.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ptp.h index bbee74cd8404..61faddcc3dd0 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ptp.h +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ptp.h @@ -25,7 +25,7 @@ struct ifreq; #define HCLGE_PTP_TIME_SEC_H_MASK GENMASK(15, 0) #define HCLGE_PTP_TIME_SEC_L_REG 0x54 #define HCLGE_PTP_TIME_NSEC_REG 0x58 -#define HCLGE_PTP_TIME_NSEC_MASK GENMASK(29, 0) +#define HCLGE_PTP_TIME_NSEC_MASK 0x3fffffffLL #define HCLGE_PTP_TIME_NSEC_NEG BIT(31) #define HCLGE_PTP_TIME_SYNC_REG 0x5C #define HCLGE_PTP_TIME_SYNC_EN BIT(0) @@ -138,6 +138,6 @@ int hclge_ptp_set_cfg(struct hclge_dev *hdev, struct ifreq *ifr); int hclge_ptp_init(struct hclge_dev *hdev); void hclge_ptp_uninit(struct hclge_dev *hdev); int hclge_ptp_get_ts_info(struct hnae3_handle *handle, - struct ethtool_ts_info *info); + struct kernel_ethtool_ts_info *info); int hclge_ptp_cfg_qry(struct hclge_dev *hdev, u32 *cfg); #endif diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_regs.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_regs.c index 43c1c18fa81f..8c057192aae6 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_regs.c +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_regs.c @@ -510,9 +510,9 @@ out: static int hclge_fetch_pf_reg(struct hclge_dev *hdev, void *data, struct hnae3_knic_private_info *kinfo) { -#define HCLGE_RING_REG_OFFSET 0x200 #define HCLGE_RING_INT_REG_OFFSET 0x4 + struct hnae3_queue *tqp; int i, j, reg_num; int data_num_sum; u32 *reg = data; @@ -533,10 +533,11 @@ static int hclge_fetch_pf_reg(struct hclge_dev *hdev, void *data, reg_num = ARRAY_SIZE(ring_reg_addr_list); for (j = 0; j < kinfo->num_tqps; j++) { reg += hclge_reg_get_tlv(HCLGE_REG_TAG_RING, reg_num, reg); + tqp = kinfo->tqp[j]; for (i = 0; i < reg_num; i++) - *reg++ = hclge_read_dev(&hdev->hw, - ring_reg_addr_list[i] + - HCLGE_RING_REG_OFFSET * j); + *reg++ = readl_relaxed(tqp->io_base - + HCLGE_TQP_REG_OFFSET + + ring_reg_addr_list[i]); } data_num_sum += (reg_num + HCLGE_REG_TLV_SPACE) * kinfo->num_tqps; diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_trace.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_trace.h index f3cd5a376eca..7103cf04bffc 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_trace.h +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_trace.h @@ -10,6 +10,7 @@ #include <linux/tracepoint.h> +#define PF_DESC_LEN (sizeof(struct hclge_desc) / sizeof(u32)) #define PF_GET_MBX_LEN (sizeof(struct hclge_mbx_vf_to_pf_cmd) / sizeof(u32)) #define PF_SEND_MBX_LEN (sizeof(struct hclge_mbx_pf_to_vf_cmd) / sizeof(u32)) @@ -32,8 +33,8 @@ TRACE_EVENT(hclge_pf_mbx_get, __entry->vfid = req->mbx_src_vfid; __entry->code = req->msg.code; __entry->subcode = req->msg.subcode; - __assign_str(pciname, pci_name(hdev->pdev)); - __assign_str(devname, hdev->vport[0].nic.kinfo.netdev->name); + __assign_str(pciname); + __assign_str(devname); memcpy(__entry->mbx_data, req, sizeof(struct hclge_mbx_vf_to_pf_cmd)); ), @@ -63,8 +64,8 @@ TRACE_EVENT(hclge_pf_mbx_send, TP_fast_assign( __entry->vfid = req->dest_vfid; __entry->code = le16_to_cpu(req->msg.code); - __assign_str(pciname, pci_name(hdev->pdev)); - __assign_str(devname, hdev->vport[0].nic.kinfo.netdev->name); + __assign_str(pciname); + __assign_str(devname); memcpy(__entry->mbx_data, req, sizeof(struct hclge_mbx_pf_to_vf_cmd)); ), @@ -77,6 +78,99 @@ TRACE_EVENT(hclge_pf_mbx_send, ) ); +DECLARE_EVENT_CLASS(hclge_pf_cmd_template, + TP_PROTO(struct hclge_comm_hw *hw, + struct hclge_desc *desc, + int index, + int num), + TP_ARGS(hw, desc, index, num), + + TP_STRUCT__entry(__field(u16, opcode) + __field(u16, flag) + __field(u16, retval) + __field(u16, rsv) + __field(int, index) + __field(int, num) + __string(pciname, pci_name(hw->cmq.csq.pdev)) + __array(u32, data, HCLGE_DESC_DATA_LEN)), + + TP_fast_assign(int i; + __entry->opcode = le16_to_cpu(desc->opcode); + __entry->flag = le16_to_cpu(desc->flag); + __entry->retval = le16_to_cpu(desc->retval); + __entry->rsv = le16_to_cpu(desc->rsv); + __entry->index = index; + __entry->num = num; + __assign_str(pciname); + for (i = 0; i < HCLGE_DESC_DATA_LEN; i++) + __entry->data[i] = le32_to_cpu(desc->data[i]);), + + TP_printk("%s opcode:0x%04x %d-%d flag:0x%04x retval:0x%04x rsv:0x%04x data:%s", + __get_str(pciname), __entry->opcode, + __entry->index, __entry->num, + __entry->flag, __entry->retval, __entry->rsv, + __print_array(__entry->data, + HCLGE_DESC_DATA_LEN, sizeof(u32))) +); + +DEFINE_EVENT(hclge_pf_cmd_template, hclge_pf_cmd_send, + TP_PROTO(struct hclge_comm_hw *hw, + struct hclge_desc *desc, + int index, + int num), + TP_ARGS(hw, desc, index, num) +); + +DEFINE_EVENT(hclge_pf_cmd_template, hclge_pf_cmd_get, + TP_PROTO(struct hclge_comm_hw *hw, + struct hclge_desc *desc, + int index, + int num), + TP_ARGS(hw, desc, index, num) +); + +DECLARE_EVENT_CLASS(hclge_pf_special_cmd_template, + TP_PROTO(struct hclge_comm_hw *hw, + __le32 *data, + int index, + int num), + TP_ARGS(hw, data, index, num), + + TP_STRUCT__entry(__field(int, index) + __field(int, num) + __string(pciname, pci_name(hw->cmq.csq.pdev)) + __array(u32, data, PF_DESC_LEN)), + + TP_fast_assign(int i; + __entry->index = index; + __entry->num = num; + __assign_str(pciname); + for (i = 0; i < PF_DESC_LEN; i++) + __entry->data[i] = le32_to_cpu(data[i]); + ), + + TP_printk("%s %d-%d data:%s", + __get_str(pciname), + __entry->index, __entry->num, + __print_array(__entry->data, + PF_DESC_LEN, sizeof(u32))) +); + +DEFINE_EVENT(hclge_pf_special_cmd_template, hclge_pf_special_cmd_send, + TP_PROTO(struct hclge_comm_hw *hw, + __le32 *desc, + int index, + int num), + TP_ARGS(hw, desc, index, num)); + +DEFINE_EVENT(hclge_pf_special_cmd_template, hclge_pf_special_cmd_get, + TP_PROTO(struct hclge_comm_hw *hw, + __le32 *desc, + int index, + int num), + TP_ARGS(hw, desc, index, num) +); + #endif /* _HCLGE_TRACE_H_ */ /* This must be outside ifdef _HCLGE_TRACE_H */ diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c index 0aa9beefd1c7..8fcf220a120d 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c +++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c @@ -11,6 +11,7 @@ #include "hnae3.h" #include "hclgevf_devlink.h" #include "hclge_comm_rss.h" +#include "hclgevf_trace.h" #define HCLGEVF_NAME "hclgevf" @@ -47,6 +48,42 @@ int hclgevf_cmd_send(struct hclgevf_hw *hw, struct hclge_desc *desc, int num) return hclge_comm_cmd_send(&hw->hw, desc, num); } +static void hclgevf_trace_cmd_send(struct hclge_comm_hw *hw, struct hclge_desc *desc, + int num, bool is_special) +{ + int i; + + trace_hclge_vf_cmd_send(hw, desc, 0, num); + + if (is_special) + return; + + for (i = 1; i < num; i++) + trace_hclge_vf_cmd_send(hw, &desc[i], i, num); +} + +static void hclgevf_trace_cmd_get(struct hclge_comm_hw *hw, struct hclge_desc *desc, + int num, bool is_special) +{ + int i; + + if (!HCLGE_COMM_SEND_SYNC(le16_to_cpu(desc->flag))) + return; + + trace_hclge_vf_cmd_get(hw, desc, 0, num); + + if (is_special) + return; + + for (i = 1; i < num; i++) + trace_hclge_vf_cmd_get(hw, &desc[i], i, num); +} + +static const struct hclge_comm_cmq_ops hclgevf_cmq_ops = { + .trace_cmd_send = hclgevf_trace_cmd_send, + .trace_cmd_get = hclgevf_trace_cmd_get, +}; + void hclgevf_arq_init(struct hclgevf_dev *hdev) { struct hclge_comm_cmq *cmdq = &hdev->hw.hw.cmq; @@ -93,12 +130,10 @@ static int hclgevf_get_sset_count(struct hnae3_handle *handle, int strset) } static void hclgevf_get_strings(struct hnae3_handle *handle, u32 strset, - u8 *data) + u8 **data) { - u8 *p = (char *)data; - if (strset == ETH_SS_STATS) - p = hclge_comm_tqps_get_strings(handle, p); + hclge_comm_tqps_get_strings(handle, data); } static void hclgevf_get_stats(struct hnae3_handle *handle, u64 *data) @@ -412,7 +447,8 @@ static int hclgevf_set_handle_info(struct hclgevf_dev *hdev) nic->ae_algo = &ae_algovf; nic->pdev = hdev->pdev; - nic->numa_node_mask = hdev->numa_node_mask; + bitmap_copy(nic->numa_node_mask.bits, hdev->numa_node_mask.bits, + MAX_NUMNODES); nic->flags |= HNAE3_SUPPORT_VF; nic->kinfo.io_base = hdev->hw.hw.io_base; @@ -570,7 +606,7 @@ static int hclgevf_set_rss(struct hnae3_handle *handle, const u32 *indir, } static int hclgevf_set_rss_tuple(struct hnae3_handle *handle, - struct ethtool_rxnfc *nfc) + const struct ethtool_rxfh_fields *nfc) { struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); int ret; @@ -588,7 +624,7 @@ static int hclgevf_set_rss_tuple(struct hnae3_handle *handle, } static int hclgevf_get_rss_tuple(struct hnae3_handle *handle, - struct ethtool_rxnfc *nfc) + struct ethtool_rxfh_fields *nfc) { struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); u8 tuple_sets; @@ -1256,9 +1292,8 @@ static void hclgevf_sync_vlan_filter(struct hclgevf_dev *hdev) rtnl_unlock(); } -static int hclgevf_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable) +static int hclgevf_en_hw_strip_rxvtag_cmd(struct hclgevf_dev *hdev, bool enable) { - struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); struct hclge_vf_to_pf_msg send_msg; hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN, @@ -1267,6 +1302,19 @@ static int hclgevf_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable) return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0); } +static int hclgevf_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable) +{ + struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); + int ret; + + ret = hclgevf_en_hw_strip_rxvtag_cmd(hdev, enable); + if (ret) + return ret; + + hdev->rxvtag_strip_en = enable; + return 0; +} + static int hclgevf_reset_tqp(struct hnae3_handle *handle) { #define HCLGEVF_RESET_ALL_QUEUE_DONE 1U @@ -1357,6 +1405,17 @@ static int hclgevf_notify_roce_client(struct hclgevf_dev *hdev, return ret; } +static void hclgevf_set_reset_pending(struct hclgevf_dev *hdev, + enum hnae3_reset_type reset_type) +{ + /* When an incorrect reset type is executed, the get_reset_level + * function generates the HNAE3_NONE_RESET flag. As a result, this + * type do not need to pending. + */ + if (reset_type != HNAE3_NONE_RESET) + set_bit(reset_type, &hdev->reset_pending); +} + static int hclgevf_reset_wait(struct hclgevf_dev *hdev) { #define HCLGEVF_RESET_WAIT_US 20000 @@ -1506,7 +1565,7 @@ static void hclgevf_reset_err_handle(struct hclgevf_dev *hdev) hdev->rst_stats.rst_fail_cnt); if (hdev->rst_stats.rst_fail_cnt < HCLGEVF_RESET_MAX_FAIL_CNT) - set_bit(hdev->reset_type, &hdev->reset_pending); + hclgevf_set_reset_pending(hdev, hdev->reset_type); if (hclgevf_is_reset_pending(hdev)) { set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); @@ -1626,6 +1685,8 @@ static enum hnae3_reset_type hclgevf_get_reset_level(unsigned long *addr) clear_bit(HNAE3_FLR_RESET, addr); } + clear_bit(HNAE3_NONE_RESET, addr); + return rst_level; } @@ -1635,14 +1696,15 @@ static void hclgevf_reset_event(struct pci_dev *pdev, struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); struct hclgevf_dev *hdev = ae_dev->priv; - dev_info(&hdev->pdev->dev, "received reset request from VF enet\n"); - if (hdev->default_reset_request) hdev->reset_level = hclgevf_get_reset_level(&hdev->default_reset_request); else hdev->reset_level = HNAE3_VF_FUNC_RESET; + dev_info(&hdev->pdev->dev, "received reset request from VF enet, reset level is %d\n", + hdev->reset_level); + /* reset of this VF requested */ set_bit(HCLGEVF_RESET_REQUESTED, &hdev->reset_state); hclgevf_reset_task_schedule(hdev); @@ -1653,8 +1715,20 @@ static void hclgevf_reset_event(struct pci_dev *pdev, static void hclgevf_set_def_reset_request(struct hnae3_ae_dev *ae_dev, enum hnae3_reset_type rst_type) { +#define HCLGEVF_SUPPORT_RESET_TYPE \ + (BIT(HNAE3_VF_RESET) | BIT(HNAE3_VF_FUNC_RESET) | \ + BIT(HNAE3_VF_PF_FUNC_RESET) | BIT(HNAE3_VF_FULL_RESET) | \ + BIT(HNAE3_FLR_RESET) | BIT(HNAE3_VF_EXP_RESET)) + struct hclgevf_dev *hdev = ae_dev->priv; + if (!(BIT(rst_type) & HCLGEVF_SUPPORT_RESET_TYPE)) { + /* To prevent reset triggered by hclge_reset_event */ + set_bit(HNAE3_NONE_RESET, &hdev->default_reset_request); + dev_info(&hdev->pdev->dev, "unsupported reset type %d\n", + rst_type); + return; + } set_bit(rst_type, &hdev->default_reset_request); } @@ -1709,8 +1783,8 @@ static void hclgevf_reset_done(struct hnae3_ae_dev *ae_dev) ret); hdev->reset_type = HNAE3_NONE_RESET; - clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state); - up(&hdev->reset_sem); + if (test_and_clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) + up(&hdev->reset_sem); } static u32 hclgevf_get_fw_version(struct hnae3_handle *handle) @@ -1811,14 +1885,14 @@ static void hclgevf_reset_service_task(struct hclgevf_dev *hdev) */ if (hdev->reset_attempts > HCLGEVF_MAX_RESET_ATTEMPTS_CNT) { /* prepare for full reset of stack + pcie interface */ - set_bit(HNAE3_VF_FULL_RESET, &hdev->reset_pending); + hclgevf_set_reset_pending(hdev, HNAE3_VF_FULL_RESET); /* "defer" schedule the reset task again */ set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); } else { hdev->reset_attempts++; - set_bit(hdev->reset_level, &hdev->reset_pending); + hclgevf_set_reset_pending(hdev, hdev->reset_level); set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); } hclgevf_reset_task_schedule(hdev); @@ -1941,7 +2015,7 @@ static enum hclgevf_evt_cause hclgevf_check_evt_cause(struct hclgevf_dev *hdev, rst_ing_reg = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING); dev_info(&hdev->pdev->dev, "receive reset interrupt 0x%x!\n", rst_ing_reg); - set_bit(HNAE3_VF_RESET, &hdev->reset_pending); + hclgevf_set_reset_pending(hdev, HNAE3_VF_RESET); set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); *clearval = ~(1U << HCLGEVF_VECTOR0_RST_INT_B); @@ -1983,7 +2057,7 @@ static enum hclgevf_evt_cause hclgevf_check_evt_cause(struct hclgevf_dev *hdev, static void hclgevf_reset_timer(struct timer_list *t) { - struct hclgevf_dev *hdev = from_timer(hdev, t, reset_timer); + struct hclgevf_dev *hdev = timer_container_of(hdev, t, reset_timer); hclgevf_clear_event_cause(hdev, HCLGEVF_VECTOR0_EVENT_RST); hclgevf_reset_task_schedule(hdev); @@ -2082,8 +2156,8 @@ static int hclgevf_init_roce_base_info(struct hclgevf_dev *hdev) roce->pdev = nic->pdev; roce->ae_algo = nic->ae_algo; - roce->numa_node_mask = nic->numa_node_mask; - + bitmap_copy(roce->numa_node_mask.bits, nic->numa_node_mask.bits, + MAX_NUMNODES); return 0; } @@ -2142,12 +2216,13 @@ static int hclgevf_rss_init_hw(struct hclgevf_dev *hdev) tc_valid, tc_size); } -static int hclgevf_init_vlan_config(struct hclgevf_dev *hdev) +static int hclgevf_init_vlan_config(struct hclgevf_dev *hdev, + bool rxvtag_strip_en) { struct hnae3_handle *nic = &hdev->nic; int ret; - ret = hclgevf_en_hw_strip_rxvtag(nic, true); + ret = hclgevf_en_hw_strip_rxvtag(nic, rxvtag_strip_en); if (ret) { dev_err(&hdev->pdev->dev, "failed to enable rx vlan offload, ret = %d\n", ret); @@ -2180,8 +2255,7 @@ static void hclgevf_set_timer_task(struct hnae3_handle *handle, bool enable) } else { set_bit(HCLGEVF_STATE_DOWN, &hdev->state); - /* flush memory to make sure DOWN is seen by service task */ - smp_mb__before_atomic(); + smp_mb__after_atomic(); /* flush memory to make sure DOWN is seen by service task */ hclgevf_flush_link_update(hdev); } } @@ -2252,6 +2326,8 @@ static void hclgevf_state_init(struct hclgevf_dev *hdev) clear_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state); INIT_DELAYED_WORK(&hdev->service_task, hclgevf_service_task); + /* timer needs to be initialized before misc irq */ + timer_setup(&hdev->reset_timer, hclgevf_reset_timer, 0); mutex_init(&hdev->mbx_resp.mbx_mutex); sema_init(&hdev->reset_sem, 1); @@ -2389,7 +2465,7 @@ static int hclgevf_init_nic_client_instance(struct hnae3_ae_dev *ae_dev, struct hnae3_client *client) { struct hclgevf_dev *hdev = ae_dev->priv; - int rst_cnt = hdev->rst_stats.rst_cnt; + u32 rst_cnt = hdev->rst_stats.rst_cnt; int ret; ret = client->ops->init_instance(&hdev->nic); @@ -2549,7 +2625,7 @@ static int hclgevf_pci_init(struct hclgevf_dev *hdev) ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); if (ret) { - dev_err(&pdev->dev, "can't set consistent PCI DMA, exiting"); + dev_err(&pdev->dev, "can't set consistent PCI DMA, exiting\n"); goto err_disable_device; } @@ -2796,6 +2872,7 @@ static int hclgevf_reset_hdev(struct hclgevf_dev *hdev) } hclgevf_arq_init(hdev); + ret = hclge_comm_cmd_init(hdev->ae_dev, &hdev->hw.hw, &hdev->fw_version, false, hdev->reset_pending); @@ -2815,7 +2892,7 @@ static int hclgevf_reset_hdev(struct hclgevf_dev *hdev) if (ret) return ret; - ret = hclgevf_init_vlan_config(hdev); + ret = hclgevf_init_vlan_config(hdev, hdev->rxvtag_strip_en); if (ret) { dev_err(&hdev->pdev->dev, "failed(%d) to initialize VLAN config\n", ret); @@ -2845,15 +2922,13 @@ static int hclgevf_init_hdev(struct hclgevf_dev *hdev) if (ret) return ret; - ret = hclgevf_devlink_init(hdev); - if (ret) - goto err_devlink_init; - ret = hclge_comm_cmd_queue_init(hdev->pdev, &hdev->hw.hw); if (ret) goto err_cmd_queue_init; hclgevf_arq_init(hdev); + + hclge_comm_cmd_init_ops(&hdev->hw.hw, &hclgevf_cmq_ops); ret = hclge_comm_cmd_init(hdev->ae_dev, &hdev->hw.hw, &hdev->fw_version, false, hdev->reset_pending); @@ -2932,7 +3007,7 @@ static int hclgevf_init_hdev(struct hclgevf_dev *hdev) goto err_config; } - ret = hclgevf_init_vlan_config(hdev); + ret = hclgevf_init_vlan_config(hdev, true); if (ret) { dev_err(&hdev->pdev->dev, "failed(%d) to initialize VLAN config\n", ret); @@ -2941,6 +3016,10 @@ static int hclgevf_init_hdev(struct hclgevf_dev *hdev) hclgevf_init_rxd_adv_layout(hdev); + ret = hclgevf_devlink_init(hdev); + if (ret) + goto err_config; + set_bit(HCLGEVF_STATE_SERVICE_INITED, &hdev->state); hdev->last_reset_time = jiffies; @@ -2948,7 +3027,6 @@ static int hclgevf_init_hdev(struct hclgevf_dev *hdev) HCLGEVF_DRIVER_NAME); hclgevf_task_schedule(hdev, round_jiffies_relative(HZ)); - timer_setup(&hdev->reset_timer, hclgevf_reset_timer, 0); return 0; @@ -2960,8 +3038,6 @@ err_misc_irq_init: err_cmd_init: hclge_comm_cmd_uninit(hdev->ae_dev, &hdev->hw.hw); err_cmd_queue_init: - hclgevf_devlink_uninit(hdev); -err_devlink_init: hclgevf_pci_uninit(hdev); clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); return ret; @@ -3018,11 +3094,7 @@ static void hclgevf_uninit_ae_dev(struct hnae3_ae_dev *ae_dev) static u32 hclgevf_get_max_channels(struct hclgevf_dev *hdev) { - struct hnae3_handle *nic = &hdev->nic; - struct hnae3_knic_private_info *kinfo = &nic->kinfo; - - return min_t(u32, hdev->rss_size_max, - hdev->num_tqps / kinfo->tc_info.num_tc); + return min(hdev->rss_size_max, hdev->num_tqps); } /** @@ -3347,8 +3419,10 @@ static int __init hclgevf_init(void) static void __exit hclgevf_exit(void) { + hnae3_acquire_unload_lock(); hnae3_unregister_ae_algo(&ae_algovf); destroy_workqueue(hclgevf_wq); + hnae3_release_unload_lock(); } module_init(hclgevf_init); module_exit(hclgevf_exit); diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h index a73f2bf3a56a..0208425ab594 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h +++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h @@ -236,7 +236,7 @@ struct hclgevf_dev { u16 rss_size_max; /* HW defined max RSS task queue */ u16 num_alloc_vport; /* num vports this driver supports */ - u32 numa_node_mask; + nodemask_t numa_node_mask; u16 rx_buf_len; u16 num_tx_desc; /* desc num of per tx queue */ u16 num_rx_desc; /* desc num of per rx queue */ @@ -253,6 +253,7 @@ struct hclgevf_dev { int *vector_irq; bool gro_en; + bool rxvtag_strip_en; unsigned long vlan_del_fail_bmap[BITS_TO_LONGS(VLAN_N_VID)]; diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_mbx.c b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_mbx.c index 85c2a634c8f9..f5c99ca54369 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_mbx.c +++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_mbx.c @@ -159,7 +159,7 @@ static bool hclgevf_cmd_crq_empty(struct hclgevf_hw *hw) { u32 tail = hclgevf_read_dev(hw, HCLGE_COMM_NIC_CRQ_TAIL_REG); - return tail == hw->hw.cmq.crq.next_to_use; + return tail == (u32)hw->hw.cmq.crq.next_to_use; } static void hclgevf_handle_mbx_response(struct hclgevf_dev *hdev, diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_regs.c b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_regs.c index 65b9dcd38137..9de01e344e27 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_regs.c +++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_regs.c @@ -123,40 +123,42 @@ int hclgevf_get_regs_len(struct hnae3_handle *handle) void hclgevf_get_regs(struct hnae3_handle *handle, u32 *version, void *data) { -#define HCLGEVF_RING_REG_OFFSET 0x200 #define HCLGEVF_RING_INT_REG_OFFSET 0x4 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle); - int i, j, reg_um; + struct hnae3_queue *tqp; + int i, j, reg_num; u32 *reg = data; *version = hdev->fw_version; reg += hclgevf_reg_get_header(reg); /* fetching per-VF registers values from VF PCIe register space */ - reg_um = sizeof(cmdq_reg_addr_list) / sizeof(u32); - reg += hclgevf_reg_get_tlv(HCLGEVF_REG_TAG_CMDQ, reg_um, reg); - for (i = 0; i < reg_um; i++) + reg_num = ARRAY_SIZE(cmdq_reg_addr_list); + reg += hclgevf_reg_get_tlv(HCLGEVF_REG_TAG_CMDQ, reg_num, reg); + for (i = 0; i < reg_num; i++) *reg++ = hclgevf_read_dev(&hdev->hw, cmdq_reg_addr_list[i]); - reg_um = sizeof(common_reg_addr_list) / sizeof(u32); - reg += hclgevf_reg_get_tlv(HCLGEVF_REG_TAG_COMMON, reg_um, reg); - for (i = 0; i < reg_um; i++) + reg_num = ARRAY_SIZE(common_reg_addr_list); + reg += hclgevf_reg_get_tlv(HCLGEVF_REG_TAG_COMMON, reg_num, reg); + for (i = 0; i < reg_num; i++) *reg++ = hclgevf_read_dev(&hdev->hw, common_reg_addr_list[i]); - reg_um = sizeof(ring_reg_addr_list) / sizeof(u32); + reg_num = ARRAY_SIZE(ring_reg_addr_list); for (j = 0; j < hdev->num_tqps; j++) { - reg += hclgevf_reg_get_tlv(HCLGEVF_REG_TAG_RING, reg_um, reg); - for (i = 0; i < reg_um; i++) - *reg++ = hclgevf_read_dev(&hdev->hw, - ring_reg_addr_list[i] + - HCLGEVF_RING_REG_OFFSET * j); + reg += hclgevf_reg_get_tlv(HCLGEVF_REG_TAG_RING, reg_num, reg); + tqp = &hdev->htqp[j].q; + for (i = 0; i < reg_num; i++) + *reg++ = readl_relaxed(tqp->io_base - + HCLGEVF_TQP_REG_OFFSET + + ring_reg_addr_list[i]); } - reg_um = sizeof(tqp_intr_reg_addr_list) / sizeof(u32); + reg_num = ARRAY_SIZE(tqp_intr_reg_addr_list); for (j = 0; j < hdev->num_msi_used - 1; j++) { - reg += hclgevf_reg_get_tlv(HCLGEVF_REG_TAG_TQP_INTR, reg_um, reg); - for (i = 0; i < reg_um; i++) + reg += hclgevf_reg_get_tlv(HCLGEVF_REG_TAG_TQP_INTR, + reg_num, reg); + for (i = 0; i < reg_num; i++) *reg++ = hclgevf_read_dev(&hdev->hw, tqp_intr_reg_addr_list[i] + HCLGEVF_RING_INT_REG_OFFSET * j); diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_trace.h b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_trace.h index b259e95dd53c..66b084309c91 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_trace.h +++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_trace.h @@ -30,8 +30,8 @@ TRACE_EVENT(hclge_vf_mbx_get, TP_fast_assign( __entry->vfid = req->dest_vfid; __entry->code = le16_to_cpu(req->msg.code); - __assign_str(pciname, pci_name(hdev->pdev)); - __assign_str(devname, hdev->nic.kinfo.netdev->name); + __assign_str(pciname); + __assign_str(devname); memcpy(__entry->mbx_data, req, sizeof(struct hclge_mbx_pf_to_vf_cmd)); ), @@ -63,8 +63,8 @@ TRACE_EVENT(hclge_vf_mbx_send, __entry->vfid = req->mbx_src_vfid; __entry->code = req->msg.code; __entry->subcode = req->msg.subcode; - __assign_str(pciname, pci_name(hdev->pdev)); - __assign_str(devname, hdev->nic.kinfo.netdev->name); + __assign_str(pciname); + __assign_str(devname); memcpy(__entry->mbx_data, req, sizeof(struct hclge_mbx_vf_to_pf_cmd)); ), @@ -77,6 +77,56 @@ TRACE_EVENT(hclge_vf_mbx_send, ) ); +DECLARE_EVENT_CLASS(hclge_vf_cmd_template, + TP_PROTO(struct hclge_comm_hw *hw, + struct hclge_desc *desc, + int index, + int num), + + TP_ARGS(hw, desc, index, num), + + TP_STRUCT__entry(__field(u16, opcode) + __field(u16, flag) + __field(u16, retval) + __field(u16, rsv) + __field(int, index) + __field(int, num) + __string(pciname, pci_name(hw->cmq.csq.pdev)) + __array(u32, data, HCLGE_DESC_DATA_LEN)), + + TP_fast_assign(int i; + __entry->opcode = le16_to_cpu(desc->opcode); + __entry->flag = le16_to_cpu(desc->flag); + __entry->retval = le16_to_cpu(desc->retval); + __entry->rsv = le16_to_cpu(desc->rsv); + __entry->index = index; + __entry->num = num; + __assign_str(pciname); + for (i = 0; i < HCLGE_DESC_DATA_LEN; i++) + __entry->data[i] = le32_to_cpu(desc->data[i]);), + + TP_printk("%s opcode:0x%04x %d-%d flag:0x%04x retval:0x%04x rsv:0x%04x data:%s", + __get_str(pciname), __entry->opcode, + __entry->index, __entry->num, + __entry->flag, __entry->retval, __entry->rsv, + __print_array(__entry->data, + HCLGE_DESC_DATA_LEN, sizeof(u32))) +); + +DEFINE_EVENT(hclge_vf_cmd_template, hclge_vf_cmd_send, + TP_PROTO(struct hclge_comm_hw *hw, + struct hclge_desc *desc, + int index, + int num), + TP_ARGS(hw, desc, index, num)); + +DEFINE_EVENT(hclge_vf_cmd_template, hclge_vf_cmd_get, + TP_PROTO(struct hclge_comm_hw *hw, + struct hclge_desc *desc, + int index, + int num), + TP_ARGS(hw, desc, index, num)); + #endif /* _HCLGEVF_TRACE_H_ */ /* This must be outside ifdef _HCLGEVF_TRACE_H */ |