diff options
Diffstat (limited to 'tools/perf/arch/x86/tests')
| -rw-r--r-- | tools/perf/arch/x86/tests/Build | 33 | ||||
| -rw-r--r-- | tools/perf/arch/x86/tests/amd-ibs-period.c | 1032 | ||||
| -rw-r--r-- | tools/perf/arch/x86/tests/arch-tests.c | 2 | ||||
| -rw-r--r-- | tools/perf/arch/x86/tests/dwarf-unwind.c | 2 | ||||
| -rwxr-xr-x | tools/perf/arch/x86/tests/gen-insn-x86-dat.sh | 2 | ||||
| -rw-r--r-- | tools/perf/arch/x86/tests/insn-x86-dat-32.c | 116 | ||||
| -rw-r--r-- | tools/perf/arch/x86/tests/insn-x86-dat-64.c | 1026 | ||||
| -rw-r--r-- | tools/perf/arch/x86/tests/insn-x86-dat-src.c | 597 | ||||
| -rw-r--r-- | tools/perf/arch/x86/tests/intel-cqm.c | 128 | ||||
| -rw-r--r-- | tools/perf/arch/x86/tests/intel-pt-test.c | 4 |
10 files changed, 2801 insertions, 141 deletions
diff --git a/tools/perf/arch/x86/tests/Build b/tools/perf/arch/x86/tests/Build index b87f46e5feea..5e00cbfd2d56 100644 --- a/tools/perf/arch/x86/tests/Build +++ b/tools/perf/arch/x86/tests/Build @@ -1,12 +1,27 @@ -perf-$(CONFIG_DWARF_UNWIND) += regs_load.o -perf-$(CONFIG_DWARF_UNWIND) += dwarf-unwind.o +perf-test-$(CONFIG_DWARF_UNWIND) += regs_load.o +perf-test-$(CONFIG_DWARF_UNWIND) += dwarf-unwind.o -perf-y += arch-tests.o -perf-y += sample-parsing.o -perf-y += hybrid.o -perf-$(CONFIG_AUXTRACE) += intel-pt-test.o +perf-test-y += arch-tests.o +perf-test-y += sample-parsing.o +perf-test-y += hybrid.o +perf-test-$(CONFIG_AUXTRACE) += intel-pt-test.o ifeq ($(CONFIG_EXTRA_TESTS),y) -perf-$(CONFIG_AUXTRACE) += insn-x86.o +perf-test-$(CONFIG_AUXTRACE) += insn-x86.o endif -perf-$(CONFIG_X86_64) += bp-modify.o -perf-y += amd-ibs-via-core-pmu.o +perf-test-$(CONFIG_X86_64) += bp-modify.o +perf-test-y += amd-ibs-via-core-pmu.o +perf-test-y += amd-ibs-period.o + +ifdef SHELLCHECK + SHELL_TESTS := gen-insn-x86-dat.sh + SHELL_TEST_LOGS := $(SHELL_TESTS:%=%.shellcheck_log) +else + SHELL_TESTS := + SHELL_TEST_LOGS := +endif + +$(OUTPUT)%.shellcheck_log: % + $(call rule_mkdir) + $(Q)$(call echo-cmd,test)shellcheck -a -S warning "$<" > $@ || (cat $@ && rm $@ && false) + +perf-test-y += $(SHELL_TEST_LOGS) diff --git a/tools/perf/arch/x86/tests/amd-ibs-period.c b/tools/perf/arch/x86/tests/amd-ibs-period.c new file mode 100644 index 000000000000..223e059e04de --- /dev/null +++ b/tools/perf/arch/x86/tests/amd-ibs-period.c @@ -0,0 +1,1032 @@ +// SPDX-License-Identifier: GPL-2.0 +#include <sched.h> +#include <sys/syscall.h> +#include <sys/mman.h> +#include <sys/ioctl.h> +#include <sys/utsname.h> +#include <string.h> + +#include "arch-tests.h" +#include "linux/perf_event.h" +#include "linux/zalloc.h" +#include "tests/tests.h" +#include "../perf-sys.h" +#include "pmu.h" +#include "pmus.h" +#include "debug.h" +#include "util.h" +#include "strbuf.h" +#include "../util/env.h" + +static int page_size; + +#define PERF_MMAP_DATA_PAGES 32L +#define PERF_MMAP_DATA_SIZE (PERF_MMAP_DATA_PAGES * page_size) +#define PERF_MMAP_DATA_MASK (PERF_MMAP_DATA_SIZE - 1) +#define PERF_MMAP_TOTAL_PAGES (PERF_MMAP_DATA_PAGES + 1) +#define PERF_MMAP_TOTAL_SIZE (PERF_MMAP_TOTAL_PAGES * page_size) + +#define rmb() asm volatile("lfence":::"memory") + +enum { + FD_ERROR, + FD_SUCCESS, +}; + +enum { + IBS_FETCH, + IBS_OP, +}; + +struct perf_pmu *fetch_pmu; +struct perf_pmu *op_pmu; +unsigned int perf_event_max_sample_rate; + +/* Dummy workload to generate IBS samples. */ +static int dummy_workload_1(unsigned long count) +{ + int (*func)(void); + int ret = 0; + char *p; + char insn1[] = { + 0xb8, 0x01, 0x00, 0x00, 0x00, /* mov 1,%eax */ + 0xc3, /* ret */ + 0xcc, /* int 3 */ + }; + + char insn2[] = { + 0xb8, 0x02, 0x00, 0x00, 0x00, /* mov 2,%eax */ + 0xc3, /* ret */ + 0xcc, /* int 3 */ + }; + + p = zalloc(2 * page_size); + if (!p) { + printf("malloc() failed. %m"); + return 1; + } + + func = (void *)((unsigned long)(p + page_size - 1) & ~(page_size - 1)); + + ret = mprotect(func, page_size, PROT_READ | PROT_WRITE | PROT_EXEC); + if (ret) { + printf("mprotect() failed. %m"); + goto out; + } + + if (count < 100000) + count = 100000; + else if (count > 10000000) + count = 10000000; + while (count--) { + memcpy((void *)func, insn1, sizeof(insn1)); + if (func() != 1) { + pr_debug("ERROR insn1\n"); + ret = -1; + goto out; + } + memcpy((void *)func, insn2, sizeof(insn2)); + if (func() != 2) { + pr_debug("ERROR insn2\n"); + ret = -1; + goto out; + } + } + +out: + free(p); + return ret; +} + +/* Another dummy workload to generate IBS samples. */ +static void dummy_workload_2(char *perf) +{ + char bench[] = " bench sched messaging -g 10 -l 5000 > /dev/null 2>&1"; + char taskset[] = "taskset -c 0 "; + int ret __maybe_unused; + struct strbuf sb; + char *cmd; + + strbuf_init(&sb, 0); + strbuf_add(&sb, taskset, strlen(taskset)); + strbuf_add(&sb, perf, strlen(perf)); + strbuf_add(&sb, bench, strlen(bench)); + cmd = strbuf_detach(&sb, NULL); + ret = system(cmd); + free(cmd); +} + +static int sched_affine(int cpu) +{ + cpu_set_t set; + + CPU_ZERO(&set); + CPU_SET(cpu, &set); + if (sched_setaffinity(getpid(), sizeof(set), &set) == -1) { + pr_debug("sched_setaffinity() failed. [%m]"); + return -1; + } + return 0; +} + +static void +copy_sample_data(void *src, unsigned long offset, void *dest, size_t size) +{ + size_t chunk1_size, chunk2_size; + + if ((offset + size) < (size_t)PERF_MMAP_DATA_SIZE) { + memcpy(dest, src + offset, size); + } else { + chunk1_size = PERF_MMAP_DATA_SIZE - offset; + chunk2_size = size - chunk1_size; + + memcpy(dest, src + offset, chunk1_size); + memcpy(dest + chunk1_size, src, chunk2_size); + } +} + +static int rb_read(struct perf_event_mmap_page *rb, void *dest, size_t size) +{ + void *base; + unsigned long data_tail, data_head; + + /* Casting to (void *) is needed. */ + base = (void *)rb + page_size; + + data_head = rb->data_head; + rmb(); + data_tail = rb->data_tail; + + if ((data_head - data_tail) < size) + return -1; + + data_tail &= PERF_MMAP_DATA_MASK; + copy_sample_data(base, data_tail, dest, size); + rb->data_tail += size; + return 0; +} + +static void rb_skip(struct perf_event_mmap_page *rb, size_t size) +{ + size_t data_head = rb->data_head; + + rmb(); + + if ((rb->data_tail + size) > data_head) + rb->data_tail = data_head; + else + rb->data_tail += size; +} + +/* Sample period value taken from perf sample must match with expected value. */ +static int period_equal(unsigned long exp_period, unsigned long act_period) +{ + return exp_period == act_period ? 0 : -1; +} + +/* + * Sample period value taken from perf sample must be >= minimum sample period + * supported by IBS HW. + */ +static int period_higher(unsigned long min_period, unsigned long act_period) +{ + return min_period <= act_period ? 0 : -1; +} + +static int rb_drain_samples(struct perf_event_mmap_page *rb, + unsigned long exp_period, + int *nr_samples, + int (*callback)(unsigned long, unsigned long)) +{ + struct perf_event_header hdr; + unsigned long period; + int ret = 0; + + /* + * PERF_RECORD_SAMPLE: + * struct { + * struct perf_event_header hdr; + * { u64 period; } && PERF_SAMPLE_PERIOD + * }; + */ + while (1) { + if (rb_read(rb, &hdr, sizeof(hdr))) + return ret; + + if (hdr.type == PERF_RECORD_SAMPLE) { + (*nr_samples)++; + period = 0; + if (rb_read(rb, &period, sizeof(period))) + pr_debug("rb_read(period) error. [%m]"); + ret |= callback(exp_period, period); + } else { + rb_skip(rb, hdr.size - sizeof(hdr)); + } + } + return ret; +} + +static long perf_event_open(struct perf_event_attr *attr, pid_t pid, + int cpu, int group_fd, unsigned long flags) +{ + return syscall(__NR_perf_event_open, attr, pid, cpu, group_fd, flags); +} + +static void fetch_prepare_attr(struct perf_event_attr *attr, + unsigned long long config, int freq, + unsigned long sample_period) +{ + memset(attr, 0, sizeof(struct perf_event_attr)); + + attr->type = fetch_pmu->type; + attr->size = sizeof(struct perf_event_attr); + attr->config = config; + attr->disabled = 1; + attr->sample_type = PERF_SAMPLE_PERIOD; + attr->freq = freq; + attr->sample_period = sample_period; /* = ->sample_freq */ +} + +static void op_prepare_attr(struct perf_event_attr *attr, + unsigned long config, int freq, + unsigned long sample_period) +{ + memset(attr, 0, sizeof(struct perf_event_attr)); + + attr->type = op_pmu->type; + attr->size = sizeof(struct perf_event_attr); + attr->config = config; + attr->disabled = 1; + attr->sample_type = PERF_SAMPLE_PERIOD; + attr->freq = freq; + attr->sample_period = sample_period; /* = ->sample_freq */ +} + +struct ibs_configs { + /* Input */ + unsigned long config; + + /* Expected output */ + unsigned long period; + int fd; +}; + +/* + * Somehow first Fetch event with sample period = 0x10 causes 0 + * samples. So start with large period and decrease it gradually. + */ +struct ibs_configs fetch_configs[] = { + { .config = 0xffff, .period = 0xffff0, .fd = FD_SUCCESS }, + { .config = 0x1000, .period = 0x10000, .fd = FD_SUCCESS }, + { .config = 0xff, .period = 0xff0, .fd = FD_SUCCESS }, + { .config = 0x1, .period = 0x10, .fd = FD_SUCCESS }, + { .config = 0x0, .period = -1, .fd = FD_ERROR }, + { .config = 0x10000, .period = -1, .fd = FD_ERROR }, +}; + +struct ibs_configs op_configs[] = { + { .config = 0x0, .period = -1, .fd = FD_ERROR }, + { .config = 0x1, .period = -1, .fd = FD_ERROR }, + { .config = 0x8, .period = -1, .fd = FD_ERROR }, + { .config = 0x9, .period = 0x90, .fd = FD_SUCCESS }, + { .config = 0xf, .period = 0xf0, .fd = FD_SUCCESS }, + { .config = 0x1000, .period = 0x10000, .fd = FD_SUCCESS }, + { .config = 0xffff, .period = 0xffff0, .fd = FD_SUCCESS }, + { .config = 0x10000, .period = -1, .fd = FD_ERROR }, + { .config = 0x100000, .period = 0x100000, .fd = FD_SUCCESS }, + { .config = 0xf00000, .period = 0xf00000, .fd = FD_SUCCESS }, + { .config = 0xf0ffff, .period = 0xfffff0, .fd = FD_SUCCESS }, + { .config = 0x1f0ffff, .period = 0x1fffff0, .fd = FD_SUCCESS }, + { .config = 0x7f0ffff, .period = 0x7fffff0, .fd = FD_SUCCESS }, + { .config = 0x8f0ffff, .period = -1, .fd = FD_ERROR }, + { .config = 0x17f0ffff, .period = -1, .fd = FD_ERROR }, +}; + +static int __ibs_config_test(int ibs_type, struct ibs_configs *config, int *nr_samples) +{ + struct perf_event_attr attr; + int fd, i; + void *rb; + int ret = 0; + + if (ibs_type == IBS_FETCH) + fetch_prepare_attr(&attr, config->config, 0, 0); + else + op_prepare_attr(&attr, config->config, 0, 0); + + /* CPU0, All processes */ + fd = perf_event_open(&attr, -1, 0, -1, 0); + if (config->fd == FD_ERROR) { + if (fd != -1) { + close(fd); + return -1; + } + return 0; + } + if (fd <= -1) + return -1; + + rb = mmap(NULL, PERF_MMAP_TOTAL_SIZE, PROT_READ | PROT_WRITE, + MAP_SHARED, fd, 0); + if (rb == MAP_FAILED) { + pr_debug("mmap() failed. [%m]\n"); + return -1; + } + + ioctl(fd, PERF_EVENT_IOC_RESET, 0); + ioctl(fd, PERF_EVENT_IOC_ENABLE, 0); + + i = 5; + while (i--) { + dummy_workload_1(1000000); + + ret = rb_drain_samples(rb, config->period, nr_samples, + period_equal); + if (ret) + break; + } + + ioctl(fd, PERF_EVENT_IOC_DISABLE, 0); + munmap(rb, PERF_MMAP_TOTAL_SIZE); + close(fd); + return ret; +} + +static int ibs_config_test(void) +{ + int nr_samples = 0; + unsigned long i; + int ret = 0; + int r; + + pr_debug("\nIBS config tests:\n"); + pr_debug("-----------------\n"); + + pr_debug("Fetch PMU tests:\n"); + for (i = 0; i < ARRAY_SIZE(fetch_configs); i++) { + nr_samples = 0; + r = __ibs_config_test(IBS_FETCH, &(fetch_configs[i]), &nr_samples); + + if (fetch_configs[i].fd == FD_ERROR) { + pr_debug("0x%-16lx: %-4s\n", fetch_configs[i].config, + !r ? "Ok" : "Fail"); + } else { + /* + * Although nr_samples == 0 is reported as Fail here, + * the failure status is not cascaded up because, we + * can not decide whether test really failed or not + * without actual samples. + */ + pr_debug("0x%-16lx: %-4s (nr samples: %d)\n", fetch_configs[i].config, + (!r && nr_samples != 0) ? "Ok" : "Fail", nr_samples); + } + + ret |= r; + } + + pr_debug("Op PMU tests:\n"); + for (i = 0; i < ARRAY_SIZE(op_configs); i++) { + nr_samples = 0; + r = __ibs_config_test(IBS_OP, &(op_configs[i]), &nr_samples); + + if (op_configs[i].fd == FD_ERROR) { + pr_debug("0x%-16lx: %-4s\n", op_configs[i].config, + !r ? "Ok" : "Fail"); + } else { + /* + * Although nr_samples == 0 is reported as Fail here, + * the failure status is not cascaded up because, we + * can not decide whether test really failed or not + * without actual samples. + */ + pr_debug("0x%-16lx: %-4s (nr samples: %d)\n", op_configs[i].config, + (!r && nr_samples != 0) ? "Ok" : "Fail", nr_samples); + } + + ret |= r; + } + + return ret; +} + +struct ibs_period { + /* Input */ + int freq; + unsigned long sample_freq; + + /* Output */ + int ret; + unsigned long period; +}; + +struct ibs_period fetch_period[] = { + { .freq = 0, .sample_freq = 0, .ret = FD_ERROR, .period = -1 }, + { .freq = 0, .sample_freq = 1, .ret = FD_ERROR, .period = -1 }, + { .freq = 0, .sample_freq = 0xf, .ret = FD_ERROR, .period = -1 }, + { .freq = 0, .sample_freq = 0x10, .ret = FD_SUCCESS, .period = 0x10 }, + { .freq = 0, .sample_freq = 0x11, .ret = FD_SUCCESS, .period = 0x10 }, + { .freq = 0, .sample_freq = 0x8f, .ret = FD_SUCCESS, .period = 0x80 }, + { .freq = 0, .sample_freq = 0x90, .ret = FD_SUCCESS, .period = 0x90 }, + { .freq = 0, .sample_freq = 0x91, .ret = FD_SUCCESS, .period = 0x90 }, + { .freq = 0, .sample_freq = 0x4d2, .ret = FD_SUCCESS, .period = 0x4d0 }, + { .freq = 0, .sample_freq = 0x1007, .ret = FD_SUCCESS, .period = 0x1000 }, + { .freq = 0, .sample_freq = 0xfff0, .ret = FD_SUCCESS, .period = 0xfff0 }, + { .freq = 0, .sample_freq = 0xffff, .ret = FD_SUCCESS, .period = 0xfff0 }, + { .freq = 0, .sample_freq = 0x10010, .ret = FD_SUCCESS, .period = 0x10010 }, + { .freq = 0, .sample_freq = 0x7fffff, .ret = FD_SUCCESS, .period = 0x7ffff0 }, + { .freq = 0, .sample_freq = 0xfffffff, .ret = FD_SUCCESS, .period = 0xffffff0 }, + { .freq = 1, .sample_freq = 0, .ret = FD_ERROR, .period = -1 }, + { .freq = 1, .sample_freq = 1, .ret = FD_SUCCESS, .period = 0x10 }, + { .freq = 1, .sample_freq = 0xf, .ret = FD_SUCCESS, .period = 0x10 }, + { .freq = 1, .sample_freq = 0x10, .ret = FD_SUCCESS, .period = 0x10 }, + { .freq = 1, .sample_freq = 0x11, .ret = FD_SUCCESS, .period = 0x10 }, + { .freq = 1, .sample_freq = 0x8f, .ret = FD_SUCCESS, .period = 0x10 }, + { .freq = 1, .sample_freq = 0x90, .ret = FD_SUCCESS, .period = 0x10 }, + { .freq = 1, .sample_freq = 0x91, .ret = FD_SUCCESS, .period = 0x10 }, + { .freq = 1, .sample_freq = 0x4d2, .ret = FD_SUCCESS, .period = 0x10 }, + { .freq = 1, .sample_freq = 0x1007, .ret = FD_SUCCESS, .period = 0x10 }, + { .freq = 1, .sample_freq = 0xfff0, .ret = FD_SUCCESS, .period = 0x10 }, + { .freq = 1, .sample_freq = 0xffff, .ret = FD_SUCCESS, .period = 0x10 }, + { .freq = 1, .sample_freq = 0x10010, .ret = FD_SUCCESS, .period = 0x10 }, + /* ret=FD_ERROR because freq > default perf_event_max_sample_rate (100000) */ + { .freq = 1, .sample_freq = 0x7fffff, .ret = FD_ERROR, .period = -1 }, +}; + +struct ibs_period op_period[] = { + { .freq = 0, .sample_freq = 0, .ret = FD_ERROR, .period = -1 }, + { .freq = 0, .sample_freq = 1, .ret = FD_ERROR, .period = -1 }, + { .freq = 0, .sample_freq = 0xf, .ret = FD_ERROR, .period = -1 }, + { .freq = 0, .sample_freq = 0x10, .ret = FD_ERROR, .period = -1 }, + { .freq = 0, .sample_freq = 0x11, .ret = FD_ERROR, .period = -1 }, + { .freq = 0, .sample_freq = 0x8f, .ret = FD_ERROR, .period = -1 }, + { .freq = 0, .sample_freq = 0x90, .ret = FD_SUCCESS, .period = 0x90 }, + { .freq = 0, .sample_freq = 0x91, .ret = FD_SUCCESS, .period = 0x90 }, + { .freq = 0, .sample_freq = 0x4d2, .ret = FD_SUCCESS, .period = 0x4d0 }, + { .freq = 0, .sample_freq = 0x1007, .ret = FD_SUCCESS, .period = 0x1000 }, + { .freq = 0, .sample_freq = 0xfff0, .ret = FD_SUCCESS, .period = 0xfff0 }, + { .freq = 0, .sample_freq = 0xffff, .ret = FD_SUCCESS, .period = 0xfff0 }, + { .freq = 0, .sample_freq = 0x10010, .ret = FD_SUCCESS, .period = 0x10010 }, + { .freq = 0, .sample_freq = 0x7fffff, .ret = FD_SUCCESS, .period = 0x7ffff0 }, + { .freq = 0, .sample_freq = 0xfffffff, .ret = FD_SUCCESS, .period = 0xffffff0 }, + { .freq = 1, .sample_freq = 0, .ret = FD_ERROR, .period = -1 }, + { .freq = 1, .sample_freq = 1, .ret = FD_SUCCESS, .period = 0x90 }, + { .freq = 1, .sample_freq = 0xf, .ret = FD_SUCCESS, .period = 0x90 }, + { .freq = 1, .sample_freq = 0x10, .ret = FD_SUCCESS, .period = 0x90 }, + { .freq = 1, .sample_freq = 0x11, .ret = FD_SUCCESS, .period = 0x90 }, + { .freq = 1, .sample_freq = 0x8f, .ret = FD_SUCCESS, .period = 0x90 }, + { .freq = 1, .sample_freq = 0x90, .ret = FD_SUCCESS, .period = 0x90 }, + { .freq = 1, .sample_freq = 0x91, .ret = FD_SUCCESS, .period = 0x90 }, + { .freq = 1, .sample_freq = 0x4d2, .ret = FD_SUCCESS, .period = 0x90 }, + { .freq = 1, .sample_freq = 0x1007, .ret = FD_SUCCESS, .period = 0x90 }, + { .freq = 1, .sample_freq = 0xfff0, .ret = FD_SUCCESS, .period = 0x90 }, + { .freq = 1, .sample_freq = 0xffff, .ret = FD_SUCCESS, .period = 0x90 }, + { .freq = 1, .sample_freq = 0x10010, .ret = FD_SUCCESS, .period = 0x90 }, + /* ret=FD_ERROR because freq > default perf_event_max_sample_rate (100000) */ + { .freq = 1, .sample_freq = 0x7fffff, .ret = FD_ERROR, .period = -1 }, +}; + +static int __ibs_period_constraint_test(int ibs_type, struct ibs_period *period, + int *nr_samples) +{ + struct perf_event_attr attr; + int ret = 0; + void *rb; + int fd; + + if (period->freq && period->sample_freq > perf_event_max_sample_rate) + period->ret = FD_ERROR; + + if (ibs_type == IBS_FETCH) + fetch_prepare_attr(&attr, 0, period->freq, period->sample_freq); + else + op_prepare_attr(&attr, 0, period->freq, period->sample_freq); + + /* CPU0, All processes */ + fd = perf_event_open(&attr, -1, 0, -1, 0); + if (period->ret == FD_ERROR) { + if (fd != -1) { + close(fd); + return -1; + } + return 0; + } + if (fd <= -1) + return -1; + + rb = mmap(NULL, PERF_MMAP_TOTAL_SIZE, PROT_READ | PROT_WRITE, + MAP_SHARED, fd, 0); + if (rb == MAP_FAILED) { + pr_debug("mmap() failed. [%m]\n"); + close(fd); + return -1; + } + + ioctl(fd, PERF_EVENT_IOC_RESET, 0); + ioctl(fd, PERF_EVENT_IOC_ENABLE, 0); + + if (period->freq) { + dummy_workload_1(100000); + ret = rb_drain_samples(rb, period->period, nr_samples, + period_higher); + } else { + dummy_workload_1(period->sample_freq * 10); + ret = rb_drain_samples(rb, period->period, nr_samples, + period_equal); + } + + ioctl(fd, PERF_EVENT_IOC_DISABLE, 0); + munmap(rb, PERF_MMAP_TOTAL_SIZE); + close(fd); + return ret; +} + +static int ibs_period_constraint_test(void) +{ + unsigned long i; + int nr_samples; + int ret = 0; + int r; + + pr_debug("\nIBS sample period constraint tests:\n"); + pr_debug("-----------------------------------\n"); + + pr_debug("Fetch PMU test:\n"); + for (i = 0; i < ARRAY_SIZE(fetch_period); i++) { + nr_samples = 0; + r = __ibs_period_constraint_test(IBS_FETCH, &fetch_period[i], + &nr_samples); + + if (fetch_period[i].ret == FD_ERROR) { + pr_debug("freq %d, sample_freq %9ld: %-4s\n", + fetch_period[i].freq, fetch_period[i].sample_freq, + !r ? "Ok" : "Fail"); + } else { + /* + * Although nr_samples == 0 is reported as Fail here, + * the failure status is not cascaded up because, we + * can not decide whether test really failed or not + * without actual samples. + */ + pr_debug("freq %d, sample_freq %9ld: %-4s (nr samples: %d)\n", + fetch_period[i].freq, fetch_period[i].sample_freq, + (!r && nr_samples != 0) ? "Ok" : "Fail", nr_samples); + } + ret |= r; + } + + pr_debug("Op PMU test:\n"); + for (i = 0; i < ARRAY_SIZE(op_period); i++) { + nr_samples = 0; + r = __ibs_period_constraint_test(IBS_OP, &op_period[i], + &nr_samples); + + if (op_period[i].ret == FD_ERROR) { + pr_debug("freq %d, sample_freq %9ld: %-4s\n", + op_period[i].freq, op_period[i].sample_freq, + !r ? "Ok" : "Fail"); + } else { + /* + * Although nr_samples == 0 is reported as Fail here, + * the failure status is not cascaded up because, we + * can not decide whether test really failed or not + * without actual samples. + */ + pr_debug("freq %d, sample_freq %9ld: %-4s (nr samples: %d)\n", + op_period[i].freq, op_period[i].sample_freq, + (!r && nr_samples != 0) ? "Ok" : "Fail", nr_samples); + } + ret |= r; + } + + return ret; +} + +struct ibs_ioctl { + /* Input */ + int freq; + unsigned long period; + + /* Expected output */ + int ret; +}; + +struct ibs_ioctl fetch_ioctl[] = { + { .freq = 0, .period = 0x0, .ret = FD_ERROR }, + { .freq = 0, .period = 0x1, .ret = FD_ERROR }, + { .freq = 0, .period = 0xf, .ret = FD_ERROR }, + { .freq = 0, .period = 0x10, .ret = FD_SUCCESS }, + { .freq = 0, .period = 0x11, .ret = FD_ERROR }, + { .freq = 0, .period = 0x1f, .ret = FD_ERROR }, + { .freq = 0, .period = 0x20, .ret = FD_SUCCESS }, + { .freq = 0, .period = 0x80, .ret = FD_SUCCESS }, + { .freq = 0, .period = 0x8f, .ret = FD_ERROR }, + { .freq = 0, .period = 0x90, .ret = FD_SUCCESS }, + { .freq = 0, .period = 0x91, .ret = FD_ERROR }, + { .freq = 0, .period = 0x100, .ret = FD_SUCCESS }, + { .freq = 0, .period = 0xfff0, .ret = FD_SUCCESS }, + { .freq = 0, .period = 0xffff, .ret = FD_ERROR }, + { .freq = 0, .period = 0x10000, .ret = FD_SUCCESS }, + { .freq = 0, .period = 0x1fff0, .ret = FD_SUCCESS }, + { .freq = 0, .period = 0x1fff5, .ret = FD_ERROR }, + { .freq = 1, .period = 0x0, .ret = FD_ERROR }, + { .freq = 1, .period = 0x1, .ret = FD_SUCCESS }, + { .freq = 1, .period = 0xf, .ret = FD_SUCCESS }, + { .freq = 1, .period = 0x10, .ret = FD_SUCCESS }, + { .freq = 1, .period = 0x11, .ret = FD_SUCCESS }, + { .freq = 1, .period = 0x1f, .ret = FD_SUCCESS }, + { .freq = 1, .period = 0x20, .ret = FD_SUCCESS }, + { .freq = 1, .period = 0x80, .ret = FD_SUCCESS }, + { .freq = 1, .period = 0x8f, .ret = FD_SUCCESS }, + { .freq = 1, .period = 0x90, .ret = FD_SUCCESS }, + { .freq = 1, .period = 0x91, .ret = FD_SUCCESS }, + { .freq = 1, .period = 0x100, .ret = FD_SUCCESS }, +}; + +struct ibs_ioctl op_ioctl[] = { + { .freq = 0, .period = 0x0, .ret = FD_ERROR }, + { .freq = 0, .period = 0x1, .ret = FD_ERROR }, + { .freq = 0, .period = 0xf, .ret = FD_ERROR }, + { .freq = 0, .period = 0x10, .ret = FD_ERROR }, + { .freq = 0, .period = 0x11, .ret = FD_ERROR }, + { .freq = 0, .period = 0x1f, .ret = FD_ERROR }, + { .freq = 0, .period = 0x20, .ret = FD_ERROR }, + { .freq = 0, .period = 0x80, .ret = FD_ERROR }, + { .freq = 0, .period = 0x8f, .ret = FD_ERROR }, + { .freq = 0, .period = 0x90, .ret = FD_SUCCESS }, + { .freq = 0, .period = 0x91, .ret = FD_ERROR }, + { .freq = 0, .period = 0x100, .ret = FD_SUCCESS }, + { .freq = 0, .period = 0xfff0, .ret = FD_SUCCESS }, + { .freq = 0, .period = 0xffff, .ret = FD_ERROR }, + { .freq = 0, .period = 0x10000, .ret = FD_SUCCESS }, + { .freq = 0, .period = 0x1fff0, .ret = FD_SUCCESS }, + { .freq = 0, .period = 0x1fff5, .ret = FD_ERROR }, + { .freq = 1, .period = 0x0, .ret = FD_ERROR }, + { .freq = 1, .period = 0x1, .ret = FD_SUCCESS }, + { .freq = 1, .period = 0xf, .ret = FD_SUCCESS }, + { .freq = 1, .period = 0x10, .ret = FD_SUCCESS }, + { .freq = 1, .period = 0x11, .ret = FD_SUCCESS }, + { .freq = 1, .period = 0x1f, .ret = FD_SUCCESS }, + { .freq = 1, .period = 0x20, .ret = FD_SUCCESS }, + { .freq = 1, .period = 0x80, .ret = FD_SUCCESS }, + { .freq = 1, .period = 0x8f, .ret = FD_SUCCESS }, + { .freq = 1, .period = 0x90, .ret = FD_SUCCESS }, + { .freq = 1, .period = 0x91, .ret = FD_SUCCESS }, + { .freq = 1, .period = 0x100, .ret = FD_SUCCESS }, +}; + +static int __ibs_ioctl_test(int ibs_type, struct ibs_ioctl *ibs_ioctl) +{ + struct perf_event_attr attr; + int ret = 0; + int fd; + int r; + + if (ibs_type == IBS_FETCH) + fetch_prepare_attr(&attr, 0, ibs_ioctl->freq, 1000); + else + op_prepare_attr(&attr, 0, ibs_ioctl->freq, 1000); + + /* CPU0, All processes */ + fd = perf_event_open(&attr, -1, 0, -1, 0); + if (fd <= -1) { + pr_debug("event_open() Failed\n"); + return -1; + } + + r = ioctl(fd, PERF_EVENT_IOC_PERIOD, &ibs_ioctl->period); + if ((ibs_ioctl->ret == FD_SUCCESS && r <= -1) || + (ibs_ioctl->ret == FD_ERROR && r >= 0)) { + ret = -1; + } + + close(fd); + return ret; +} + +static int ibs_ioctl_test(void) +{ + unsigned long i; + int ret = 0; + int r; + + pr_debug("\nIBS ioctl() tests:\n"); + pr_debug("------------------\n"); + + pr_debug("Fetch PMU tests\n"); + for (i = 0; i < ARRAY_SIZE(fetch_ioctl); i++) { + r = __ibs_ioctl_test(IBS_FETCH, &fetch_ioctl[i]); + + pr_debug("ioctl(%s = 0x%-7lx): %s\n", + fetch_ioctl[i].freq ? "freq " : "period", + fetch_ioctl[i].period, r ? "Fail" : "Ok"); + ret |= r; + } + + pr_debug("Op PMU tests\n"); + for (i = 0; i < ARRAY_SIZE(op_ioctl); i++) { + r = __ibs_ioctl_test(IBS_OP, &op_ioctl[i]); + + pr_debug("ioctl(%s = 0x%-7lx): %s\n", + op_ioctl[i].freq ? "freq " : "period", + op_ioctl[i].period, r ? "Fail" : "Ok"); + ret |= r; + } + + return ret; +} + +static int ibs_freq_neg_test(void) +{ + struct perf_event_attr attr; + int fd; + + pr_debug("\nIBS freq (negative) tests:\n"); + pr_debug("--------------------------\n"); + + /* + * Assuming perf_event_max_sample_rate <= 100000, + * config: 0x300D40 ==> MaxCnt: 200000 + */ + op_prepare_attr(&attr, 0x300D40, 1, 0); + + /* CPU0, All processes */ + fd = perf_event_open(&attr, -1, 0, -1, 0); + if (fd != -1) { + pr_debug("freq 1, sample_freq 200000: Fail\n"); + close(fd); + return -1; + } + + pr_debug("freq 1, sample_freq 200000: Ok\n"); + + return 0; +} + +struct ibs_l3missonly { + /* Input */ + int freq; + unsigned long sample_freq; + + /* Expected output */ + int ret; + unsigned long min_period; +}; + +struct ibs_l3missonly fetch_l3missonly = { + .freq = 1, + .sample_freq = 10000, + .ret = FD_SUCCESS, + .min_period = 0x10, +}; + +struct ibs_l3missonly op_l3missonly = { + .freq = 1, + .sample_freq = 10000, + .ret = FD_SUCCESS, + .min_period = 0x90, +}; + +static int __ibs_l3missonly_test(char *perf, int ibs_type, int *nr_samples, + struct ibs_l3missonly *l3missonly) +{ + struct perf_event_attr attr; + int ret = 0; + void *rb; + int fd; + + if (l3missonly->sample_freq > perf_event_max_sample_rate) + l3missonly->ret = FD_ERROR; + + if (ibs_type == IBS_FETCH) { + fetch_prepare_attr(&attr, 0x800000000000000UL, l3missonly->freq, + l3missonly->sample_freq); + } else { + op_prepare_attr(&attr, 0x10000, l3missonly->freq, + l3missonly->sample_freq); + } + + /* CPU0, All processes */ + fd = perf_event_open(&attr, -1, 0, -1, 0); + if (l3missonly->ret == FD_ERROR) { + if (fd != -1) { + close(fd); + return -1; + } + return 0; + } + if (fd == -1) { + pr_debug("perf_event_open() failed. [%m]\n"); + return -1; + } + + rb = mmap(NULL, PERF_MMAP_TOTAL_SIZE, PROT_READ | PROT_WRITE, + MAP_SHARED, fd, 0); + if (rb == MAP_FAILED) { + pr_debug("mmap() failed. [%m]\n"); + close(fd); + return -1; + } + + ioctl(fd, PERF_EVENT_IOC_RESET, 0); + ioctl(fd, PERF_EVENT_IOC_ENABLE, 0); + + dummy_workload_2(perf); + + ioctl(fd, PERF_EVENT_IOC_DISABLE, 0); + + ret = rb_drain_samples(rb, l3missonly->min_period, nr_samples, period_higher); + + munmap(rb, PERF_MMAP_TOTAL_SIZE); + close(fd); + return ret; +} + +static int ibs_l3missonly_test(char *perf) +{ + int nr_samples = 0; + int ret = 0; + int r = 0; + + pr_debug("\nIBS L3MissOnly test: (takes a while)\n"); + pr_debug("--------------------\n"); + + if (perf_pmu__has_format(fetch_pmu, "l3missonly")) { + nr_samples = 0; + r = __ibs_l3missonly_test(perf, IBS_FETCH, &nr_samples, &fetch_l3missonly); + if (fetch_l3missonly.ret == FD_ERROR) { + pr_debug("Fetch L3MissOnly: %-4s\n", !r ? "Ok" : "Fail"); + } else { + /* + * Although nr_samples == 0 is reported as Fail here, + * the failure status is not cascaded up because, we + * can not decide whether test really failed or not + * without actual samples. + */ + pr_debug("Fetch L3MissOnly: %-4s (nr_samples: %d)\n", + (!r && nr_samples != 0) ? "Ok" : "Fail", nr_samples); + } + ret |= r; + } + + if (perf_pmu__has_format(op_pmu, "l3missonly")) { + nr_samples = 0; + r = __ibs_l3missonly_test(perf, IBS_OP, &nr_samples, &op_l3missonly); + if (op_l3missonly.ret == FD_ERROR) { + pr_debug("Op L3MissOnly: %-4s\n", !r ? "Ok" : "Fail"); + } else { + /* + * Although nr_samples == 0 is reported as Fail here, + * the failure status is not cascaded up because, we + * can not decide whether test really failed or not + * without actual samples. + */ + pr_debug("Op L3MissOnly: %-4s (nr_samples: %d)\n", + (!r && nr_samples != 0) ? "Ok" : "Fail", nr_samples); + } + ret |= r; + } + + return ret; +} + +static unsigned int get_perf_event_max_sample_rate(void) +{ + unsigned int max_sample_rate = 100000; + FILE *fp; + int ret; + + fp = fopen("/proc/sys/kernel/perf_event_max_sample_rate", "r"); + if (!fp) { + pr_debug("Can't open perf_event_max_sample_rate. Assuming %d\n", + max_sample_rate); + goto out; + } + + ret = fscanf(fp, "%d", &max_sample_rate); + if (ret == EOF) { + pr_debug("Can't read perf_event_max_sample_rate. Assuming 100000\n"); + max_sample_rate = 100000; + } + fclose(fp); + +out: + return max_sample_rate; +} + +/* + * Bunch of IBS sample period fixes that this test exercise went in v6.15. + * Skip the test on older kernels to distinguish between test failure due + * to a new bug vs known failure due to older kernel. + */ +static bool kernel_v6_15_or_newer(void) +{ + struct utsname utsname; + char *endptr = NULL; + long major, minor; + + if (uname(&utsname) < 0) { + pr_debug("uname() failed. [%m]"); + return false; + } + + major = strtol(utsname.release, &endptr, 10); + endptr++; + minor = strtol(endptr, NULL, 10); + + return major >= 6 && minor >= 15; +} + +int test__amd_ibs_period(struct test_suite *test __maybe_unused, + int subtest __maybe_unused) +{ + char perf[PATH_MAX] = {'\0'}; + int ret = TEST_OK; + + page_size = sysconf(_SC_PAGESIZE); + + /* + * Reading perf_event_max_sample_rate only once _might_ cause some + * of the test to fail if kernel changes it after reading it here. + */ + perf_event_max_sample_rate = get_perf_event_max_sample_rate(); + fetch_pmu = perf_pmus__find("ibs_fetch"); + op_pmu = perf_pmus__find("ibs_op"); + + if (!x86__is_amd_cpu() || !fetch_pmu || !op_pmu) + return TEST_SKIP; + + if (!kernel_v6_15_or_newer()) { + pr_debug("Need v6.15 or newer kernel. Skipping.\n"); + return TEST_SKIP; + } + + perf_exe(perf, sizeof(perf)); + + if (sched_affine(0)) + return TEST_FAIL; + + /* + * Perf event can be opened in two modes: + * 1 Freq mode + * perf_event_attr->freq = 1, ->sample_freq = <frequency> + * 2 Sample period mode + * perf_event_attr->freq = 0, ->sample_period = <period> + * + * Instead of using above interface, IBS event in 'sample period mode' + * can also be opened by passing <period> value directly in a MaxCnt + * bitfields of perf_event_attr->config. Test this IBS specific special + * interface. + */ + if (ibs_config_test()) + ret = TEST_FAIL; + + /* + * IBS Fetch and Op PMUs have HW constraints on minimum sample period. + * Also, sample period value must be in multiple of 0x10. Test that IBS + * driver honors HW constraints for various possible values in Freq as + * well as Sample Period mode IBS events. + */ + if (ibs_period_constraint_test()) + ret = TEST_FAIL; + + /* + * Test ioctl() with various sample period values for IBS event. + */ + if (ibs_ioctl_test()) + ret = TEST_FAIL; + + /* + * Test that opening of freq mode IBS event fails when the freq value + * is passed through ->config, not explicitly in ->sample_freq. Also + * use high freq value (beyond perf_event_max_sample_rate) to test IBS + * driver do not bypass perf_event_max_sample_rate checks. + */ + if (ibs_freq_neg_test()) + ret = TEST_FAIL; + + /* + * L3MissOnly is a post-processing filter, i.e. IBS HW checks for L3 + * Miss at the completion of the tagged uOp. The sample is discarded + * if the tagged uOp did not cause L3Miss. Also, IBS HW internally + * resets CurCnt to a small pseudo-random value and resumes counting. + * A new uOp is tagged once CurCnt reaches to MaxCnt. But the process + * repeats until the tagged uOp causes an L3 Miss. + * + * With the freq mode event, the next sample period is calculated by + * generic kernel on every sample to achieve desired freq of samples. + * + * Since the number of times HW internally reset CurCnt and the pseudo- + * random value of CurCnt for all those occurrences are not known to SW, + * the sample period adjustment by kernel goes for a toes for freq mode + * IBS events. Kernel will set very small period for the next sample if + * the window between current sample and prev sample is too high due to + * multiple samples being discarded internally by IBS HW. + * + * Test that IBS sample period constraints are honored when L3MissOnly + * is ON. + */ + if (ibs_l3missonly_test(perf)) + ret = TEST_FAIL; + + return ret; +} diff --git a/tools/perf/arch/x86/tests/arch-tests.c b/tools/perf/arch/x86/tests/arch-tests.c index a216a5d172ed..bfee2432515b 100644 --- a/tools/perf/arch/x86/tests/arch-tests.c +++ b/tools/perf/arch/x86/tests/arch-tests.c @@ -25,6 +25,7 @@ DEFINE_SUITE("x86 bp modify", bp_modify); #endif DEFINE_SUITE("x86 Sample parsing", x86_sample_parsing); DEFINE_SUITE("AMD IBS via core pmu", amd_ibs_via_core_pmu); +DEFINE_SUITE_EXCLUSIVE("AMD IBS sample period", amd_ibs_period); static struct test_case hybrid_tests[] = { TEST_CASE_REASON("x86 hybrid event parsing", hybrid, "not hybrid"), { .name = NULL, } @@ -50,6 +51,7 @@ struct test_suite *arch_tests[] = { #endif &suite__x86_sample_parsing, &suite__amd_ibs_via_core_pmu, + &suite__amd_ibs_period, &suite__hybrid, NULL, }; diff --git a/tools/perf/arch/x86/tests/dwarf-unwind.c b/tools/perf/arch/x86/tests/dwarf-unwind.c index c05c0a85dad4..e91a73d09cec 100644 --- a/tools/perf/arch/x86/tests/dwarf-unwind.c +++ b/tools/perf/arch/x86/tests/dwarf-unwind.c @@ -53,7 +53,7 @@ static int sample_ustack(struct perf_sample *sample, int test__arch_unwind_sample(struct perf_sample *sample, struct thread *thread) { - struct regs_dump *regs = &sample->user_regs; + struct regs_dump *regs = perf_sample__user_regs(sample); u64 *buf; buf = malloc(sizeof(u64) * PERF_REGS_MAX); diff --git a/tools/perf/arch/x86/tests/gen-insn-x86-dat.sh b/tools/perf/arch/x86/tests/gen-insn-x86-dat.sh index 0d0a003a9c5e..89c46532cd5c 100755 --- a/tools/perf/arch/x86/tests/gen-insn-x86-dat.sh +++ b/tools/perf/arch/x86/tests/gen-insn-x86-dat.sh @@ -11,7 +11,7 @@ if [ "$(uname -m)" != "x86_64" ]; then exit 1 fi -cd $(dirname $0) +cd "$(dirname $0)" trap 'echo "Might need a more recent version of binutils"' EXIT diff --git a/tools/perf/arch/x86/tests/insn-x86-dat-32.c b/tools/perf/arch/x86/tests/insn-x86-dat-32.c index ba429cadb18f..ce9645edaf68 100644 --- a/tools/perf/arch/x86/tests/insn-x86-dat-32.c +++ b/tools/perf/arch/x86/tests/insn-x86-dat-32.c @@ -3107,6 +3107,122 @@ "62 f5 7c 08 2e ca \tvucomish %xmm2,%xmm1",}, {{0x62, 0xf5, 0x7c, 0x08, 0x2e, 0x8c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "", "62 f5 7c 08 2e 8c c8 78 56 34 12 \tvucomish 0x12345678(%eax,%ecx,8),%xmm1",}, +{{0xf3, 0x0f, 0x38, 0xdc, 0xd1, }, 5, 0, "", "", +"f3 0f 38 dc d1 \tloadiwkey %xmm1,%xmm2",}, +{{0xf3, 0x0f, 0x38, 0xfa, 0xd0, }, 5, 0, "", "", +"f3 0f 38 fa d0 \tencodekey128 %eax,%edx",}, +{{0xf3, 0x0f, 0x38, 0xfb, 0xd0, }, 5, 0, "", "", +"f3 0f 38 fb d0 \tencodekey256 %eax,%edx",}, +{{0xf3, 0x0f, 0x38, 0xdc, 0x5a, 0x77, }, 6, 0, "", "", +"f3 0f 38 dc 5a 77 \taesenc128kl 0x77(%edx),%xmm3",}, +{{0xf3, 0x0f, 0x38, 0xde, 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%eax,%edx",}, +{{0xf3, 0x0f, 0x38, 0xfb, 0xd0, }, 5, 0, "", "", +"f3 0f 38 fb d0 \tencodekey256 %eax,%edx",}, +{{0x67, 0xf3, 0x0f, 0x38, 0xdc, 0x5a, 0x77, }, 7, 0, "", "", +"67 f3 0f 38 dc 5a 77 \taesenc128kl 0x77(%edx),%xmm3",}, +{{0x67, 0xf3, 0x0f, 0x38, 0xde, 0x5a, 0x77, }, 7, 0, "", "", +"67 f3 0f 38 de 5a 77 \taesenc256kl 0x77(%edx),%xmm3",}, +{{0x67, 0xf3, 0x0f, 0x38, 0xdd, 0x5a, 0x77, }, 7, 0, "", "", +"67 f3 0f 38 dd 5a 77 \taesdec128kl 0x77(%edx),%xmm3",}, +{{0x67, 0xf3, 0x0f, 0x38, 0xdf, 0x5a, 0x77, }, 7, 0, "", "", +"67 f3 0f 38 df 5a 77 \taesdec256kl 0x77(%edx),%xmm3",}, +{{0x67, 0xf3, 0x0f, 0x38, 0xd8, 0x42, 0x77, }, 7, 0, "", "", +"67 f3 0f 38 d8 42 77 \taesencwide128kl 0x77(%edx)",}, +{{0x67, 0xf3, 0x0f, 0x38, 0xd8, 0x52, 0x77, }, 7, 0, "", "", +"67 f3 0f 38 d8 52 77 \taesencwide256kl 0x77(%edx)",}, +{{0x67, 0xf3, 0x0f, 0x38, 0xd8, 0x4a, 0x77, }, 7, 0, "", "", +"67 f3 0f 38 d8 4a 77 \taesdecwide128kl 0x77(%edx)",}, +{{0x67, 0xf3, 0x0f, 0x38, 0xd8, 0x5a, 0x77, }, 7, 0, "", "", +"67 f3 0f 38 d8 5a 77 \taesdecwide256kl 0x77(%edx)",}, +{{0x67, 0x0f, 0x38, 0xfc, 0x08, }, 5, 0, "", "", +"67 0f 38 fc 08 \taadd %ecx,(%eax)",}, +{{0x0f, 0x38, 0xfc, 0x14, 0x25, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", +"0f 38 fc 14 25 78 56 34 12 \taadd %edx,0x12345678",}, +{{0x67, 0x0f, 0x38, 0xfc, 0x94, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 10, 0, "", "", +"67 0f 38 fc 94 c8 78 56 34 12 \taadd %edx,0x12345678(%eax,%ecx,8)",}, +{{0x67, 0x66, 0x0f, 0x38, 0xfc, 0x08, }, 6, 0, "", "", +"67 66 0f 38 fc 08 \taand %ecx,(%eax)",}, +{{0x66, 0x0f, 0x38, 0xfc, 0x14, 0x25, 0x78, 0x56, 0x34, 0x12, }, 10, 0, "", "", +"66 0f 38 fc 14 25 78 56 34 12 \taand %edx,0x12345678",}, +{{0x67, 0x66, 0x0f, 0x38, 0xfc, 0x94, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "", +"67 66 0f 38 fc 94 c8 78 56 34 12 \taand %edx,0x12345678(%eax,%ecx,8)",}, +{{0x67, 0xf2, 0x0f, 0x38, 0xfc, 0x08, }, 6, 0, "", "", +"67 f2 0f 38 fc 08 \taor %ecx,(%eax)",}, +{{0xf2, 0x0f, 0x38, 0xfc, 0x14, 0x25, 0x78, 0x56, 0x34, 0x12, }, 10, 0, "", "", +"f2 0f 38 fc 14 25 78 56 34 12 \taor %edx,0x12345678",}, +{{0x67, 0xf2, 0x0f, 0x38, 0xfc, 0x94, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "", +"67 f2 0f 38 fc 94 c8 78 56 34 12 \taor %edx,0x12345678(%eax,%ecx,8)",}, +{{0x67, 0xf3, 0x0f, 0x38, 0xfc, 0x08, }, 6, 0, "", "", +"67 f3 0f 38 fc 08 \taxor %ecx,(%eax)",}, +{{0xf3, 0x0f, 0x38, 0xfc, 0x14, 0x25, 0x78, 0x56, 0x34, 0x12, }, 10, 0, "", "", +"f3 0f 38 fc 14 25 78 56 34 12 \taxor %edx,0x12345678",}, +{{0x67, 0xf3, 0x0f, 0x38, 0xfc, 0x94, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "", +"67 f3 0f 38 fc 94 c8 78 56 34 12 \taxor %edx,0x12345678(%eax,%ecx,8)",}, +{{0x67, 0xc4, 0xe2, 0x7a, 0xb1, 0x31, }, 6, 0, "", "", +"67 c4 e2 7a b1 31 \tvbcstnebf162ps (%ecx),%xmm6",}, +{{0x67, 0xc4, 0xe2, 0x79, 0xb1, 0x31, }, 6, 0, "", "", +"67 c4 e2 79 b1 31 \tvbcstnesh2ps (%ecx),%xmm6",}, +{{0x67, 0xc4, 0xe2, 0x7a, 0xb0, 0x31, }, 6, 0, "", "", +"67 c4 e2 7a b0 31 \tvcvtneebf162ps (%ecx),%xmm6",}, +{{0x67, 0xc4, 0xe2, 0x79, 0xb0, 0x31, }, 6, 0, "", "", +"67 c4 e2 79 b0 31 \tvcvtneeph2ps (%ecx),%xmm6",}, +{{0x67, 0xc4, 0xe2, 0x7b, 0xb0, 0x31, }, 6, 0, "", "", +"67 c4 e2 7b b0 31 \tvcvtneobf162ps (%ecx),%xmm6",}, +{{0x67, 0xc4, 0xe2, 0x78, 0xb0, 0x31, }, 6, 0, "", "", +"67 c4 e2 78 b0 31 \tvcvtneoph2ps (%ecx),%xmm6",}, +{{0x62, 0xf2, 0x7e, 0x08, 0x72, 0xf1, }, 6, 0, "", "", +"62 f2 7e 08 72 f1 \tvcvtneps2bf16 %xmm1,%xmm6",}, +{{0xc4, 0xe2, 0x6b, 0x50, 0xd9, }, 5, 0, "", "", +"c4 e2 6b 50 d9 \tvpdpbssd %xmm1,%xmm2,%xmm3",}, +{{0xc4, 0xe2, 0x6b, 0x51, 0xd9, }, 5, 0, "", "", +"c4 e2 6b 51 d9 \tvpdpbssds %xmm1,%xmm2,%xmm3",}, +{{0xc4, 0xe2, 0x6a, 0x50, 0xd9, }, 5, 0, "", "", +"c4 e2 6a 50 d9 \tvpdpbsud %xmm1,%xmm2,%xmm3",}, +{{0xc4, 0xe2, 0x6a, 0x51, 0xd9, }, 5, 0, "", "", +"c4 e2 6a 51 d9 \tvpdpbsuds %xmm1,%xmm2,%xmm3",}, +{{0xc4, 0xe2, 0x68, 0x50, 0xd9, }, 5, 0, "", "", +"c4 e2 68 50 d9 \tvpdpbuud %xmm1,%xmm2,%xmm3",}, +{{0xc4, 0xe2, 0x68, 0x51, 0xd9, }, 5, 0, "", "", +"c4 e2 68 51 d9 \tvpdpbuuds %xmm1,%xmm2,%xmm3",}, +{{0xc4, 0xe2, 0x6a, 0xd2, 0xd9, }, 5, 0, "", "", +"c4 e2 6a d2 d9 \tvpdpwsud %xmm1,%xmm2,%xmm3",}, +{{0xc4, 0xe2, 0x6a, 0xd3, 0xd9, }, 5, 0, "", "", +"c4 e2 6a d3 d9 \tvpdpwsuds %xmm1,%xmm2,%xmm3",}, +{{0xc4, 0xe2, 0x69, 0xd2, 0xd9, }, 5, 0, "", "", +"c4 e2 69 d2 d9 \tvpdpwusd %xmm1,%xmm2,%xmm3",}, +{{0xc4, 0xe2, 0x69, 0xd3, 0xd9, }, 5, 0, "", "", +"c4 e2 69 d3 d9 \tvpdpwusds %xmm1,%xmm2,%xmm3",}, +{{0xc4, 0xe2, 0x68, 0xd2, 0xd9, }, 5, 0, "", "", +"c4 e2 68 d2 d9 \tvpdpwuud %xmm1,%xmm2,%xmm3",}, +{{0xc4, 0xe2, 0x68, 0xd3, 0xd9, }, 5, 0, "", "", +"c4 e2 68 d3 d9 \tvpdpwuuds %xmm1,%xmm2,%xmm3",}, +{{0x62, 0xf2, 0xed, 0x08, 0xb5, 0xd9, }, 6, 0, "", "", +"62 f2 ed 08 b5 d9 \tvpmadd52huq %xmm1,%xmm2,%xmm3",}, +{{0x62, 0xf2, 0xed, 0x08, 0xb4, 0xd9, }, 6, 0, "", "", +"62 f2 ed 08 b4 d9 \tvpmadd52luq %xmm1,%xmm2,%xmm3",}, +{{0xc4, 0xe2, 0x7f, 0xcc, 0xd1, }, 5, 0, "", "", +"c4 e2 7f cc d1 \tvsha512msg1 %xmm1,%ymm2",}, +{{0xc4, 0xe2, 0x7f, 0xcd, 0xd1, }, 5, 0, "", "", +"c4 e2 7f cd d1 \tvsha512msg2 %ymm1,%ymm2",}, +{{0xc4, 0xe2, 0x6f, 0xcb, 0xd9, }, 5, 0, "", "", +"c4 e2 6f cb d9 \tvsha512rnds2 %xmm1,%ymm2,%ymm3",}, +{{0xc4, 0xe2, 0x68, 0xda, 0xd9, }, 5, 0, "", "", +"c4 e2 68 da d9 \tvsm3msg1 %xmm1,%xmm2,%xmm3",}, +{{0xc4, 0xe2, 0x69, 0xda, 0xd9, }, 5, 0, "", "", +"c4 e2 69 da d9 \tvsm3msg2 %xmm1,%xmm2,%xmm3",}, +{{0xc4, 0xe3, 0x69, 0xde, 0xd9, 0xa1, }, 6, 0, "", "", +"c4 e3 69 de d9 a1 \tvsm3rnds2 $0xa1,%xmm1,%xmm2,%xmm3",}, +{{0xc4, 0xe2, 0x6a, 0xda, 0xd9, }, 5, 0, "", "", +"c4 e2 6a da d9 \tvsm4key4 %xmm1,%xmm2,%xmm3",}, +{{0xc4, 0xe2, 0x6b, 0xda, 0xd9, }, 5, 0, "", "", +"c4 e2 6b da d9 \tvsm4rnds4 %xmm1,%xmm2,%xmm3",}, +{{0x67, 0x0f, 0x0d, 0x00, }, 4, 0, "", "", +"67 0f 0d 00 \tprefetch (%eax)",}, +{{0x67, 0x0f, 0x18, 0x08, }, 4, 0, "", "", +"67 0f 18 08 \tprefetcht0 (%eax)",}, +{{0x67, 0x0f, 0x18, 0x10, }, 4, 0, "", "", +"67 0f 18 10 \tprefetcht1 (%eax)",}, +{{0x67, 0x0f, 0x18, 0x18, }, 4, 0, "", "", +"67 0f 18 18 \tprefetcht2 (%eax)",}, +{{0x67, 0x0f, 0x18, 0x00, }, 4, 0, "", "", +"67 0f 18 00 \tprefetchnta (%eax)",}, +{{0x0f, 0x01, 0xc6, }, 3, 0, "", "", +"0f 01 c6 \twrmsrns",}, {{0xf3, 0x0f, 0x3a, 0xf0, 0xc0, 0x00, }, 6, 0, "", "", "f3 0f 3a f0 c0 00 \threset $0x0",}, {{0x0f, 0x01, 0xe8, }, 3, 0, "", "", diff --git a/tools/perf/arch/x86/tests/insn-x86-dat-src.c b/tools/perf/arch/x86/tests/insn-x86-dat-src.c index a391464c8dee..f55505c75d51 100644 --- a/tools/perf/arch/x86/tests/insn-x86-dat-src.c +++ b/tools/perf/arch/x86/tests/insn-x86-dat-src.c @@ -2628,6 +2628,512 @@ int main(void) asm volatile("vucomish 0x12345678(%rax,%rcx,8), %xmm1"); asm volatile("vucomish 0x12345678(%eax,%ecx,8), %xmm1"); + /* Key Locker */ + + asm volatile("loadiwkey %xmm1, %xmm2"); + asm volatile("encodekey128 %eax, %edx"); + asm volatile("encodekey256 %eax, %edx"); + asm volatile("aesenc128kl 0x77(%rdx), %xmm3"); + asm volatile("aesenc256kl 0x77(%rdx), %xmm3"); + asm volatile("aesdec128kl 0x77(%rdx), %xmm3"); + asm volatile("aesdec256kl 0x77(%rdx), %xmm3"); + asm volatile("aesencwide128kl 0x77(%rdx)"); + asm volatile("aesencwide256kl 0x77(%rdx)"); + asm volatile("aesdecwide128kl 0x77(%rdx)"); + asm volatile("aesdecwide256kl 0x77(%rdx)"); + + /* Remote Atomic Operations */ + + asm volatile("aadd %ecx,(%rax)"); + asm volatile("aadd %edx,(%r8)"); + asm volatile("aadd %edx,0x12345678(%rax,%rcx,8)"); + asm volatile("aadd %edx,0x12345678(%r8,%rcx,8)"); + asm volatile("aadd %rcx,(%rax)"); + asm volatile("aadd %rdx,(%r8)"); + asm volatile("aadd %rdx,(0x12345678)"); + asm volatile("aadd %rdx,0x12345678(%rax,%rcx,8)"); + asm volatile("aadd %rdx,0x12345678(%r8,%rcx,8)"); + + asm volatile("aand %ecx,(%rax)"); + asm volatile("aand %edx,(%r8)"); + asm volatile("aand %edx,0x12345678(%rax,%rcx,8)"); + asm volatile("aand %edx,0x12345678(%r8,%rcx,8)"); + asm volatile("aand %rcx,(%rax)"); + asm volatile("aand %rdx,(%r8)"); + asm volatile("aand %rdx,(0x12345678)"); + asm volatile("aand %rdx,0x12345678(%rax,%rcx,8)"); + asm volatile("aand %rdx,0x12345678(%r8,%rcx,8)"); + + asm volatile("aor %ecx,(%rax)"); + asm volatile("aor %edx,(%r8)"); + asm volatile("aor %edx,0x12345678(%rax,%rcx,8)"); + asm volatile("aor %edx,0x12345678(%r8,%rcx,8)"); + asm volatile("aor %rcx,(%rax)"); + asm volatile("aor %rdx,(%r8)"); + asm volatile("aor %rdx,(0x12345678)"); + asm volatile("aor %rdx,0x12345678(%rax,%rcx,8)"); + asm volatile("aor %rdx,0x12345678(%r8,%rcx,8)"); + + asm volatile("axor %ecx,(%rax)"); + asm volatile("axor %edx,(%r8)"); + asm volatile("axor %edx,0x12345678(%rax,%rcx,8)"); + asm volatile("axor %edx,0x12345678(%r8,%rcx,8)"); + asm volatile("axor %rcx,(%rax)"); + asm volatile("axor %rdx,(%r8)"); + asm volatile("axor %rdx,(0x12345678)"); + asm volatile("axor %rdx,0x12345678(%rax,%rcx,8)"); + asm volatile("axor %rdx,0x12345678(%r8,%rcx,8)"); + + /* VEX CMPxxXADD */ + + asm volatile("cmpbexadd %ebx,%ecx,(%r9)"); + asm volatile("cmpbxadd %ebx,%ecx,(%r9)"); + asm volatile("cmplexadd %ebx,%ecx,(%r9)"); + asm volatile("cmplxadd %ebx,%ecx,(%r9)"); + asm volatile("cmpnbexadd %ebx,%ecx,(%r9)"); + asm volatile("cmpnbxadd %ebx,%ecx,(%r9)"); + asm volatile("cmpnlexadd %ebx,%ecx,(%r9)"); + asm volatile("cmpnlxadd %ebx,%ecx,(%r9)"); + asm volatile("cmpnoxadd %ebx,%ecx,(%r9)"); + asm volatile("cmpnpxadd %ebx,%ecx,(%r9)"); + asm volatile("cmpnsxadd %ebx,%ecx,(%r9)"); + asm volatile("cmpnzxadd %ebx,%ecx,(%r9)"); + asm volatile("cmpoxadd %ebx,%ecx,(%r9)"); + asm volatile("cmppxadd %ebx,%ecx,(%r9)"); + asm volatile("cmpsxadd %ebx,%ecx,(%r9)"); + asm volatile("cmpzxadd %ebx,%ecx,(%r9)"); + + /* Pre-fetch */ + + asm volatile("prefetch (%rax)"); + asm volatile("prefetcht0 (%rax)"); + asm volatile("prefetcht1 (%rax)"); + asm volatile("prefetcht2 (%rax)"); + asm volatile("prefetchnta (%rax)"); + asm volatile("prefetchit0 0x12345678(%rip)"); + asm volatile("prefetchit1 0x12345678(%rip)"); + + /* MSR List */ + + asm volatile("rdmsrlist"); + asm volatile("wrmsrlist"); + + /* User Read/Write MSR */ + + asm volatile("urdmsr %rdx,%rax"); + asm volatile("urdmsr %rdx,%r22"); + asm volatile("urdmsr $0x7f,%r12"); + asm volatile("uwrmsr %rax,%rdx"); + asm volatile("uwrmsr %r22,%rdx"); + asm volatile("uwrmsr %r12,$0x7f"); + + /* AVX NE Convert */ + + asm volatile("vbcstnebf162ps (%rcx),%xmm6"); + asm volatile("vbcstnesh2ps (%rcx),%xmm6"); + asm volatile("vcvtneebf162ps (%rcx),%xmm6"); + asm volatile("vcvtneeph2ps (%rcx),%xmm6"); + asm volatile("vcvtneobf162ps (%rcx),%xmm6"); + asm volatile("vcvtneoph2ps (%rcx),%xmm6"); + asm volatile("vcvtneps2bf16 %xmm1,%xmm6"); + + /* FRED */ + + asm volatile("erets"); /* Expecting: erets indirect 0 */ + asm volatile("eretu"); /* Expecting: eretu indirect 0 */ + + /* AMX Complex */ + + asm volatile("tcmmimfp16ps %tmm1,%tmm2,%tmm3"); + asm volatile("tcmmrlfp16ps %tmm1,%tmm2,%tmm3"); + + /* AMX FP16 */ + + asm volatile("tdpfp16ps %tmm1,%tmm2,%tmm3"); + + /* REX2 */ + + asm volatile("test $0x5, %r18b"); + asm volatile("test $0x5, %r18d"); + asm volatile("test $0x5, %r18"); + asm volatile("test $0x5, %r18w"); + asm volatile("imull %eax, %r14d"); + asm volatile("imull %eax, %r17d"); + asm volatile("punpckldq (%r18), %mm2"); + asm volatile("leal (%rax), %r16d"); + asm volatile("leal (%rax), %r31d"); + asm volatile("leal (,%r16), %eax"); + asm volatile("leal (,%r31), %eax"); + asm volatile("leal (%r16), %eax"); + asm volatile("leal (%r31), %eax"); + asm volatile("leaq (%rax), %r15"); + asm volatile("leaq (%rax), %r16"); + asm volatile("leaq (%r15), %rax"); + asm volatile("leaq (%r16), %rax"); + asm volatile("leaq (,%r15), %rax"); + asm volatile("leaq (,%r16), %rax"); + asm volatile("add (%r16), %r8"); + asm volatile("add (%r16), %r15"); + asm volatile("mov (,%r9), %r16"); + asm volatile("mov (,%r14), %r16"); + asm volatile("sub (%r10), %r31"); + asm volatile("sub (%r13), %r31"); + asm volatile("leal 1(%r16, %r21), %eax"); + asm volatile("leal 1(%r16, %r26), %r31d"); + asm volatile("leal 129(%r21, %r9), %eax"); + asm volatile("leal 129(%r26, %r9), %r31d"); + /* + * Have to use .byte for jmpabs because gas does not support the + * mnemonic for some reason, but then it also gets the source line wrong + * with .byte, so the following is a workaround. + */ + asm volatile(""); /* Expecting: jmp indirect 0 */ + asm volatile(".byte 0xd5, 0x00, 0xa1, 0xef, 0xcd, 0xab, 0x90, 0x78, 0x56, 0x34, 0x12"); + asm volatile("pushp %rbx"); + asm volatile("pushp %r16"); + asm volatile("pushp %r31"); + asm volatile("popp %r31"); + asm volatile("popp %r16"); + asm volatile("popp %rbx"); + + /* APX */ + + asm volatile("bextr %r25d,%edx,%r10d"); + asm volatile("bextr %r25d,0x123(%r31,%rax,4),%edx"); + asm volatile("bextr %r31,%r15,%r11"); + asm volatile("bextr %r31,0x123(%r31,%rax,4),%r15"); + asm volatile("blsi %r25d,%edx"); + asm volatile("blsi %r31,%r15"); + asm volatile("blsi 0x123(%r31,%rax,4),%r25d"); + asm volatile("blsi 0x123(%r31,%rax,4),%r31"); + asm volatile("blsmsk %r25d,%edx"); + asm volatile("blsmsk %r31,%r15"); + asm volatile("blsmsk 0x123(%r31,%rax,4),%r25d"); + asm volatile("blsmsk 0x123(%r31,%rax,4),%r31"); + asm volatile("blsr %r25d,%edx"); + asm volatile("blsr %r31,%r15"); + asm volatile("blsr 0x123(%r31,%rax,4),%r25d"); + asm volatile("blsr 0x123(%r31,%rax,4),%r31"); + asm volatile("bzhi %r25d,%edx,%r10d"); + asm volatile("bzhi %r25d,0x123(%r31,%rax,4),%edx"); + asm volatile("bzhi %r31,%r15,%r11"); + asm volatile("bzhi %r31,0x123(%r31,%rax,4),%r15"); + asm volatile("cmpbexadd %r25d,%edx,0x123(%r31,%rax,4)"); + asm volatile("cmpbexadd %r31,%r15,0x123(%r31,%rax,4)"); + asm volatile("cmpbxadd %r25d,%edx,0x123(%r31,%rax,4)"); + asm volatile("cmpbxadd %r31,%r15,0x123(%r31,%rax,4)"); + asm volatile("cmplxadd %r25d,%edx,0x123(%r31,%rax,4)"); + asm volatile("cmplxadd %r31,%r15,0x123(%r31,%rax,4)"); + asm volatile("cmpnbexadd %r25d,%edx,0x123(%r31,%rax,4)"); + asm volatile("cmpnbexadd %r31,%r15,0x123(%r31,%rax,4)"); + asm volatile("cmpnbxadd %r25d,%edx,0x123(%r31,%rax,4)"); + asm volatile("cmpnbxadd %r31,%r15,0x123(%r31,%rax,4)"); + asm volatile("cmpnlexadd %r25d,%edx,0x123(%r31,%rax,4)"); + asm volatile("cmpnlexadd %r31,%r15,0x123(%r31,%rax,4)"); + asm volatile("cmpnlxadd %r25d,%edx,0x123(%r31,%rax,4)"); + asm volatile("cmpnlxadd %r31,%r15,0x123(%r31,%rax,4)"); + asm volatile("cmpnoxadd %r25d,%edx,0x123(%r31,%rax,4)"); + asm volatile("cmpnoxadd %r31,%r15,0x123(%r31,%rax,4)"); + asm volatile("cmpnpxadd %r25d,%edx,0x123(%r31,%rax,4)"); + asm volatile("cmpnpxadd %r31,%r15,0x123(%r31,%rax,4)"); + asm volatile("cmpnsxadd %r25d,%edx,0x123(%r31,%rax,4)"); + asm volatile("cmpnsxadd %r31,%r15,0x123(%r31,%rax,4)"); + asm volatile("cmpnzxadd %r25d,%edx,0x123(%r31,%rax,4)"); + asm volatile("cmpnzxadd %r31,%r15,0x123(%r31,%rax,4)"); + asm volatile("cmpoxadd %r25d,%edx,0x123(%r31,%rax,4)"); + asm volatile("cmpoxadd %r31,%r15,0x123(%r31,%rax,4)"); + asm volatile("cmppxadd %r25d,%edx,0x123(%r31,%rax,4)"); + asm volatile("cmppxadd %r31,%r15,0x123(%r31,%rax,4)"); + asm volatile("cmpsxadd %r25d,%edx,0x123(%r31,%rax,4)"); + asm volatile("cmpsxadd %r31,%r15,0x123(%r31,%rax,4)"); + asm volatile("cmpzxadd %r25d,%edx,0x123(%r31,%rax,4)"); + asm volatile("cmpzxadd %r31,%r15,0x123(%r31,%rax,4)"); + asm volatile("crc32q %r31, %r22"); + asm volatile("crc32q (%r31), %r22"); + asm volatile("crc32b %r19b, %r17"); + asm volatile("crc32b %r19b, %r21d"); + asm volatile("crc32b (%r19),%ebx"); + asm volatile("crc32l %r31d, %r23d"); + asm volatile("crc32l (%r31), %r23d"); + asm volatile("crc32w %r31w, %r21d"); + asm volatile("crc32w (%r31),%r21d"); + asm volatile("crc32 %rax, %r18"); + asm volatile("enqcmd 0x123(%r31d,%eax,4),%r25d"); + asm volatile("enqcmd 0x123(%r31,%rax,4),%r31"); + asm volatile("enqcmds 0x123(%r31d,%eax,4),%r25d"); + asm volatile("enqcmds 0x123(%r31,%rax,4),%r31"); + asm volatile("invept 0x123(%r31,%rax,4),%r31"); + asm volatile("invpcid 0x123(%r31,%rax,4),%r31"); + asm volatile("invvpid 0x123(%r31,%rax,4),%r31"); + asm volatile("kmovb %k5,%r25d"); + asm volatile("kmovb %k5,0x123(%r31,%rax,4)"); + asm volatile("kmovb %r25d,%k5"); + asm volatile("kmovb 0x123(%r31,%rax,4),%k5"); + asm volatile("kmovd %k5,%r25d"); + asm volatile("kmovd %k5,0x123(%r31,%rax,4)"); + asm volatile("kmovd %r25d,%k5"); + asm volatile("kmovd 0x123(%r31,%rax,4),%k5"); + asm volatile("kmovq %k5,%r31"); + asm volatile("kmovq %k5,0x123(%r31,%rax,4)"); + asm volatile("kmovq %r31,%k5"); + asm volatile("kmovq 0x123(%r31,%rax,4),%k5"); + asm volatile("kmovw %k5,%r25d"); + asm volatile("kmovw %k5,0x123(%r31,%rax,4)"); + asm volatile("kmovw %r25d,%k5"); + asm volatile("kmovw 0x123(%r31,%rax,4),%k5"); + asm volatile("ldtilecfg 0x123(%r31,%rax,4)"); + asm volatile("movbe %r18w,%ax"); + asm volatile("movbe %r15w,%ax"); + asm volatile("movbe %r18w,0x123(%r16,%rax,4)"); + asm volatile("movbe %r18w,0x123(%r31,%rax,4)"); + asm volatile("movbe %r25d,%edx"); + asm volatile("movbe %r15d,%edx"); + asm volatile("movbe %r25d,0x123(%r16,%rax,4)"); + asm volatile("movbe %r31,%r15"); + asm volatile("movbe %r8,%r15"); + asm volatile("movbe %r31,0x123(%r16,%rax,4)"); + asm volatile("movbe %r31,0x123(%r31,%rax,4)"); + asm volatile("movbe 0x123(%r16,%rax,4),%r31"); + asm volatile("movbe 0x123(%r31,%rax,4),%r18w"); + asm volatile("movbe 0x123(%r31,%rax,4),%r25d"); + asm volatile("movdir64b 0x123(%r31d,%eax,4),%r25d"); + asm volatile("movdir64b 0x123(%r31,%rax,4),%r31"); + asm volatile("movdiri %r25d,0x123(%r31,%rax,4)"); + asm volatile("movdiri %r31,0x123(%r31,%rax,4)"); + asm volatile("pdep %r25d,%edx,%r10d"); + asm volatile("pdep %r31,%r15,%r11"); + asm volatile("pdep 0x123(%r31,%rax,4),%r25d,%edx"); + asm volatile("pdep 0x123(%r31,%rax,4),%r31,%r15"); + asm volatile("pext %r25d,%edx,%r10d"); + asm volatile("pext %r31,%r15,%r11"); + asm volatile("pext 0x123(%r31,%rax,4),%r25d,%edx"); + asm volatile("pext 0x123(%r31,%rax,4),%r31,%r15"); + asm volatile("shlx %r25d,%edx,%r10d"); + asm volatile("shlx %r25d,0x123(%r31,%rax,4),%edx"); + asm volatile("shlx %r31,%r15,%r11"); + asm volatile("shlx %r31,0x123(%r31,%rax,4),%r15"); + asm volatile("shrx %r25d,%edx,%r10d"); + asm volatile("shrx %r25d,0x123(%r31,%rax,4),%edx"); + asm volatile("shrx %r31,%r15,%r11"); + asm volatile("shrx %r31,0x123(%r31,%rax,4),%r15"); + asm volatile("sttilecfg 0x123(%r31,%rax,4)"); + asm volatile("tileloadd 0x123(%r31,%rax,4),%tmm6"); + asm volatile("tileloaddt1 0x123(%r31,%rax,4),%tmm6"); + asm volatile("tilestored %tmm6,0x123(%r31,%rax,4)"); + asm volatile("vbroadcastf128 (%r16),%ymm3"); + asm volatile("vbroadcasti128 (%r16),%ymm3"); + asm volatile("vextractf128 $1,%ymm3,(%r16)"); + asm volatile("vextracti128 $1,%ymm3,(%r16)"); + asm volatile("vinsertf128 $1,(%r16),%ymm3,%ymm8"); + asm volatile("vinserti128 $1,(%r16),%ymm3,%ymm8"); + asm volatile("vroundpd $1,(%r24),%xmm6"); + asm volatile("vroundps $2,(%r24),%xmm6"); + asm volatile("vroundsd $3,(%r24),%xmm6,%xmm3"); + asm volatile("vroundss $4,(%r24),%xmm6,%xmm3"); + asm volatile("wrssd %r25d,0x123(%r31,%rax,4)"); + asm volatile("wrssq %r31,0x123(%r31,%rax,4)"); + asm volatile("wrussd %r25d,0x123(%r31,%rax,4)"); + asm volatile("wrussq %r31,0x123(%r31,%rax,4)"); + + /* APX new data destination */ + + asm volatile("adc $0x1234,%ax,%r30w"); + asm volatile("adc %r15b,%r17b,%r18b"); + asm volatile("adc %r15d,(%r8),%r18d"); + asm volatile("adc (%r15,%rax,1),%r16b,%r8b"); + asm volatile("adc (%r15,%rax,1),%r16w,%r8w"); + asm volatile("adcl $0x11,(%r19,%rax,4),%r20d"); + asm volatile("adcx %r15d,%r8d,%r18d"); + asm volatile("adcx (%r15,%r31,1),%r8"); + asm volatile("adcx (%r15,%r31,1),%r8d,%r18d"); + asm volatile("add $0x1234,%ax,%r30w"); + asm volatile("add $0x12344433,%r15,%r16"); + asm volatile("add $0x34,%r13b,%r17b"); + asm volatile("add $0xfffffffff4332211,%rax,%r8"); + asm volatile("add %r31,%r8,%r16"); + asm volatile("add %r31,(%r8),%r16"); + asm volatile("add %r31,(%r8,%r16,8),%r16"); + asm volatile("add %r31b,%r8b,%r16b"); + asm volatile("add %r31d,%r8d,%r16d"); + asm volatile("add %r31w,%r8w,%r16w"); + asm volatile("add (%r31),%r8,%r16"); + asm volatile("add 0x9090(%r31,%r16,1),%r8,%r16"); + asm volatile("addb %r31b,%r8b,%r16b"); + asm volatile("addl %r31d,%r8d,%r16d"); + asm volatile("addl $0x11,(%r19,%rax,4),%r20d"); + asm volatile("addq %r31,%r8,%r16"); + asm volatile("addq $0x12344433,(%r15,%rcx,4),%r16"); + asm volatile("addw %r31w,%r8w,%r16w"); + asm volatile("adox %r15d,%r8d,%r18d"); + asm volatile("{load} add %r31,%r8,%r16"); + asm volatile("{store} add %r31,%r8,%r16"); + asm volatile("adox (%r15,%r31,1),%r8"); + asm volatile("adox (%r15,%r31,1),%r8d,%r18d"); + asm volatile("and $0x1234,%ax,%r30w"); + asm volatile("and %r15b,%r17b,%r18b"); + asm volatile("and %r15d,(%r8),%r18d"); + asm volatile("and (%r15,%rax,1),%r16b,%r8b"); + asm volatile("and (%r15,%rax,1),%r16w,%r8w"); + asm volatile("andl $0x11,(%r19,%rax,4),%r20d"); + asm volatile("cmova 0x90909090(%eax),%edx,%r8d"); + asm volatile("cmovae 0x90909090(%eax),%edx,%r8d"); + asm volatile("cmovb 0x90909090(%eax),%edx,%r8d"); + asm volatile("cmovbe 0x90909090(%eax),%edx,%r8d"); + asm volatile("cmove 0x90909090(%eax),%edx,%r8d"); + asm volatile("cmovg 0x90909090(%eax),%edx,%r8d"); + asm volatile("cmovge 0x90909090(%eax),%edx,%r8d"); + asm volatile("cmovl 0x90909090(%eax),%edx,%r8d"); + asm volatile("cmovle 0x90909090(%eax),%edx,%r8d"); + asm volatile("cmovne 0x90909090(%eax),%edx,%r8d"); + asm volatile("cmovno 0x90909090(%eax),%edx,%r8d"); + asm volatile("cmovnp 0x90909090(%eax),%edx,%r8d"); + asm volatile("cmovns 0x90909090(%eax),%edx,%r8d"); + asm volatile("cmovo 0x90909090(%eax),%edx,%r8d"); + asm volatile("cmovp 0x90909090(%eax),%edx,%r8d"); + asm volatile("cmovs 0x90909090(%eax),%edx,%r8d"); + asm volatile("dec %rax,%r17"); + asm volatile("decb (%r31,%r12,1),%r8b"); + asm volatile("imul 0x909(%rax,%r31,8),%rdx,%r25"); + asm volatile("imul 0x90909(%eax),%edx,%r8d"); + asm volatile("inc %r31,%r16"); + asm volatile("inc %r31,%r8"); + asm volatile("inc %rax,%rbx"); + asm volatile("neg %rax,%r17"); + asm volatile("negb (%r31,%r12,1),%r8b"); + asm volatile("not %rax,%r17"); + asm volatile("notb (%r31,%r12,1),%r8b"); + asm volatile("or $0x1234,%ax,%r30w"); + asm volatile("or %r15b,%r17b,%r18b"); + asm volatile("or %r15d,(%r8),%r18d"); + asm volatile("or (%r15,%rax,1),%r16b,%r8b"); + asm volatile("or (%r15,%rax,1),%r16w,%r8w"); + asm volatile("orl $0x11,(%r19,%rax,4),%r20d"); + asm volatile("rcl $0x2,%r12b,%r31b"); + asm volatile("rcl %cl,%r16b,%r8b"); + asm volatile("rclb $0x1,(%rax),%r31b"); + asm volatile("rcll $0x2,(%rax),%r31d"); + asm volatile("rclw $0x1,(%rax),%r31w"); + asm volatile("rclw %cl,(%r19,%rax,4),%r31w"); + asm volatile("rcr $0x2,%r12b,%r31b"); + asm volatile("rcr %cl,%r16b,%r8b"); + asm volatile("rcrb $0x1,(%rax),%r31b"); + asm volatile("rcrl $0x2,(%rax),%r31d"); + asm volatile("rcrw $0x1,(%rax),%r31w"); + asm volatile("rcrw %cl,(%r19,%rax,4),%r31w"); + asm volatile("rol $0x2,%r12b,%r31b"); + asm volatile("rol %cl,%r16b,%r8b"); + asm volatile("rolb $0x1,(%rax),%r31b"); + asm volatile("roll $0x2,(%rax),%r31d"); + asm volatile("rolw $0x1,(%rax),%r31w"); + asm volatile("rolw %cl,(%r19,%rax,4),%r31w"); + asm volatile("ror $0x2,%r12b,%r31b"); + asm volatile("ror %cl,%r16b,%r8b"); + asm volatile("rorb $0x1,(%rax),%r31b"); + asm volatile("rorl $0x2,(%rax),%r31d"); + asm volatile("rorw $0x1,(%rax),%r31w"); + asm volatile("rorw %cl,(%r19,%rax,4),%r31w"); + asm volatile("sar $0x2,%r12b,%r31b"); + asm volatile("sar %cl,%r16b,%r8b"); + asm volatile("sarb $0x1,(%rax),%r31b"); + asm volatile("sarl $0x2,(%rax),%r31d"); + asm volatile("sarw $0x1,(%rax),%r31w"); + asm volatile("sarw %cl,(%r19,%rax,4),%r31w"); + asm volatile("sbb $0x1234,%ax,%r30w"); + asm volatile("sbb %r15b,%r17b,%r18b"); + asm volatile("sbb %r15d,(%r8),%r18d"); + asm volatile("sbb (%r15,%rax,1),%r16b,%r8b"); + asm volatile("sbb (%r15,%rax,1),%r16w,%r8w"); + asm volatile("sbbl $0x11,(%r19,%rax,4),%r20d"); + asm volatile("shl $0x2,%r12b,%r31b"); + asm volatile("shl $0x2,%r12b,%r31b"); + asm volatile("shl %cl,%r16b,%r8b"); + asm volatile("shl %cl,%r16b,%r8b"); + asm volatile("shlb $0x1,(%rax),%r31b"); + asm volatile("shlb $0x1,(%rax),%r31b"); + asm volatile("shld $0x1,%r12,(%rax),%r31"); + asm volatile("shld $0x2,%r15d,(%rax),%r31d"); + asm volatile("shld $0x2,%r8w,%r12w,%r31w"); + asm volatile("shld %cl,%r12,%r16,%r8"); + asm volatile("shld %cl,%r13w,(%r19,%rax,4),%r31w"); + asm volatile("shld %cl,%r9w,(%rax),%r31w"); + asm volatile("shll $0x2,(%rax),%r31d"); + asm volatile("shll $0x2,(%rax),%r31d"); + asm volatile("shlw $0x1,(%rax),%r31w"); + asm volatile("shlw $0x1,(%rax),%r31w"); + asm volatile("shlw %cl,(%r19,%rax,4),%r31w"); + asm volatile("shlw %cl,(%r19,%rax,4),%r31w"); + asm volatile("shr $0x2,%r12b,%r31b"); + asm volatile("shr %cl,%r16b,%r8b"); + asm volatile("shrb $0x1,(%rax),%r31b"); + asm volatile("shrd $0x1,%r12,(%rax),%r31"); + asm volatile("shrd $0x2,%r15d,(%rax),%r31d"); + asm volatile("shrd $0x2,%r8w,%r12w,%r31w"); + asm volatile("shrd %cl,%r12,%r16,%r8"); + asm volatile("shrd %cl,%r13w,(%r19,%rax,4),%r31w"); + asm volatile("shrd %cl,%r9w,(%rax),%r31w"); + asm volatile("shrl $0x2,(%rax),%r31d"); + asm volatile("shrw $0x1,(%rax),%r31w"); + asm volatile("shrw %cl,(%r19,%rax,4),%r31w"); + asm volatile("sub $0x1234,%ax,%r30w"); + asm volatile("sub %r15b,%r17b,%r18b"); + asm volatile("sub %r15d,(%r8),%r18d"); + asm volatile("sub (%r15,%rax,1),%r16b,%r8b"); + asm volatile("sub (%r15,%rax,1),%r16w,%r8w"); + asm volatile("subl $0x11,(%r19,%rax,4),%r20d"); + asm volatile("xor $0x1234,%ax,%r30w"); + asm volatile("xor %r15b,%r17b,%r18b"); + asm volatile("xor %r15d,(%r8),%r18d"); + asm volatile("xor (%r15,%rax,1),%r16b,%r8b"); + asm volatile("xor (%r15,%rax,1),%r16w,%r8w"); + asm volatile("xorl $0x11,(%r19,%rax,4),%r20d"); + + /* APX suppress status flags */ + + asm volatile("{nf} add %bl,%dl,%r8b"); + asm volatile("{nf} add %dx,%ax,%r9w"); + asm volatile("{nf} add 0x123(%r8,%rax,4),%bl,%dl"); + asm volatile("{nf} add 0x123(%r8,%rax,4),%dx,%ax"); + asm volatile("{nf} or %bl,%dl,%r8b"); + asm volatile("{nf} or %dx,%ax,%r9w"); + asm volatile("{nf} or 0x123(%r8,%rax,4),%bl,%dl"); + asm volatile("{nf} or 0x123(%r8,%rax,4),%dx,%ax"); + asm volatile("{nf} and %bl,%dl,%r8b"); + asm volatile("{nf} and %dx,%ax,%r9w"); + asm volatile("{nf} and 0x123(%r8,%rax,4),%bl,%dl"); + asm volatile("{nf} and 0x123(%r8,%rax,4),%dx,%ax"); + asm volatile("{nf} shld $0x7b,%dx,%ax,%r9w"); + asm volatile("{nf} sub %bl,%dl,%r8b"); + asm volatile("{nf} sub %dx,%ax,%r9w"); + asm volatile("{nf} sub 0x123(%r8,%rax,4),%bl,%dl"); + asm volatile("{nf} sub 0x123(%r8,%rax,4),%dx,%ax"); + asm volatile("{nf} shrd $0x7b,%dx,%ax,%r9w"); + asm volatile("{nf} xor %bl,%dl,%r8b"); + asm volatile("{nf} xor %r31,%r31"); + asm volatile("{nf} xor 0x123(%r8,%rax,4),%bl,%dl"); + asm volatile("{nf} xor 0x123(%r8,%rax,4),%dx,%ax"); + asm volatile("{nf} imul $0xff90,%r9,%r15"); + asm volatile("{nf} imul $0x7b,%r9,%r15"); + asm volatile("{nf} xor $0x7b,%bl,%dl"); + asm volatile("{nf} xor $0x7b,%dx,%ax"); + asm volatile("{nf} popcnt %r9,%r31"); + asm volatile("{nf} shld %cl,%dx,%ax,%r9w"); + asm volatile("{nf} shrd %cl,%dx,%ax,%r9w"); + asm volatile("{nf} imul %r9,%r31,%r11"); + asm volatile("{nf} sar $0x7b,%bl,%dl"); + asm volatile("{nf} sar $0x7b,%dx,%ax"); + asm volatile("{nf} sar $1,%bl,%dl"); + asm volatile("{nf} sar $1,%dx,%ax"); + asm volatile("{nf} sar %cl,%bl,%dl"); + asm volatile("{nf} sar %cl,%dx,%ax"); + asm volatile("{nf} andn %r9,%r31,%r11"); + asm volatile("{nf} blsi %r9,%r31"); + asm volatile("{nf} tzcnt %r9,%r31"); + asm volatile("{nf} lzcnt %r9,%r31"); + asm volatile("{nf} idiv %bl"); + asm volatile("{nf} idiv %dx"); + asm volatile("{nf} dec %bl,%dl"); + asm volatile("{nf} dec %dx,%ax"); + #else /* #ifdef __x86_64__ */ /* bound r32, mem (same op code as EVEX prefix) */ @@ -4848,6 +5354,97 @@ int main(void) #endif /* #ifndef __x86_64__ */ + /* Key Locker */ + + asm volatile(" loadiwkey %xmm1, %xmm2"); + asm volatile(" encodekey128 %eax, %edx"); + asm volatile(" encodekey256 %eax, %edx"); + asm volatile(" aesenc128kl 0x77(%edx), %xmm3"); + asm volatile(" aesenc256kl 0x77(%edx), %xmm3"); + asm volatile(" aesdec128kl 0x77(%edx), %xmm3"); + asm volatile(" aesdec256kl 0x77(%edx), %xmm3"); + asm volatile(" aesencwide128kl 0x77(%edx)"); + asm volatile(" aesencwide256kl 0x77(%edx)"); + asm volatile(" aesdecwide128kl 0x77(%edx)"); + asm volatile(" aesdecwide256kl 0x77(%edx)"); + + /* Remote Atomic Operations */ + + asm volatile("aadd %ecx,(%eax)"); + asm volatile("aadd %edx,(0x12345678)"); + asm volatile("aadd %edx,0x12345678(%eax,%ecx,8)"); + + asm volatile("aand %ecx,(%eax)"); + asm volatile("aand %edx,(0x12345678)"); + asm volatile("aand %edx,0x12345678(%eax,%ecx,8)"); + + asm volatile("aor %ecx,(%eax)"); + asm volatile("aor %edx,(0x12345678)"); + asm volatile("aor %edx,0x12345678(%eax,%ecx,8)"); + + asm volatile("axor %ecx,(%eax)"); + asm volatile("axor %edx,(0x12345678)"); + asm volatile("axor %edx,0x12345678(%eax,%ecx,8)"); + + /* AVX NE Convert */ + + asm volatile("vbcstnebf162ps (%ecx),%xmm6"); + asm volatile("vbcstnesh2ps (%ecx),%xmm6"); + asm volatile("vcvtneebf162ps (%ecx),%xmm6"); + asm volatile("vcvtneeph2ps (%ecx),%xmm6"); + asm volatile("vcvtneobf162ps (%ecx),%xmm6"); + asm volatile("vcvtneoph2ps (%ecx),%xmm6"); + asm volatile("vcvtneps2bf16 %xmm1,%xmm6"); + + /* AVX VNNI INT16 */ + + asm volatile("vpdpbssd %xmm1,%xmm2,%xmm3"); + asm volatile("vpdpbssds %xmm1,%xmm2,%xmm3"); + asm volatile("vpdpbsud %xmm1,%xmm2,%xmm3"); + asm volatile("vpdpbsuds %xmm1,%xmm2,%xmm3"); + asm volatile("vpdpbuud %xmm1,%xmm2,%xmm3"); + asm volatile("vpdpbuuds %xmm1,%xmm2,%xmm3"); + asm volatile("vpdpwsud %xmm1,%xmm2,%xmm3"); + asm volatile("vpdpwsuds %xmm1,%xmm2,%xmm3"); + asm volatile("vpdpwusd %xmm1,%xmm2,%xmm3"); + asm volatile("vpdpwusds %xmm1,%xmm2,%xmm3"); + asm volatile("vpdpwuud %xmm1,%xmm2,%xmm3"); + asm volatile("vpdpwuuds %xmm1,%xmm2,%xmm3"); + + /* AVX IFMA */ + + asm volatile("vpmadd52huq %xmm1,%xmm2,%xmm3"); + asm volatile("vpmadd52luq %xmm1,%xmm2,%xmm3"); + + /* AVX SHA512 */ + + asm volatile("vsha512msg1 %xmm1,%ymm2"); + asm volatile("vsha512msg2 %ymm1,%ymm2"); + asm volatile("vsha512rnds2 %xmm1,%ymm2,%ymm3"); + + /* AVX SM3 */ + + asm volatile("vsm3msg1 %xmm1,%xmm2,%xmm3"); + asm volatile("vsm3msg2 %xmm1,%xmm2,%xmm3"); + asm volatile("vsm3rnds2 $0xa1,%xmm1,%xmm2,%xmm3"); + + /* AVX SM4 */ + + asm volatile("vsm4key4 %xmm1,%xmm2,%xmm3"); + asm volatile("vsm4rnds4 %xmm1,%xmm2,%xmm3"); + + /* Pre-fetch */ + + asm volatile("prefetch (%eax)"); + asm volatile("prefetcht0 (%eax)"); + asm volatile("prefetcht1 (%eax)"); + asm volatile("prefetcht2 (%eax)"); + asm volatile("prefetchnta (%eax)"); + + /* Non-serializing write MSR */ + + asm volatile("wrmsrns"); + /* Prediction history reset */ asm volatile("hreset $0"); diff --git a/tools/perf/arch/x86/tests/intel-cqm.c b/tools/perf/arch/x86/tests/intel-cqm.c deleted file mode 100644 index 360a082fc928..000000000000 --- a/tools/perf/arch/x86/tests/intel-cqm.c +++ /dev/null @@ -1,128 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "tests/tests.h" -#include "cloexec.h" -#include "debug.h" -#include "evlist.h" -#include "evsel.h" -#include "arch-tests.h" -#include <internal/lib.h> // page_size - -#include <signal.h> -#include <sys/mman.h> -#include <sys/wait.h> -#include <errno.h> -#include <string.h> - -static pid_t spawn(void) -{ - pid_t pid; - - pid = fork(); - if (pid) - return pid; - - while(1) - sleep(5); - return 0; -} - -/* - * Create an event group that contains both a sampled hardware - * (cpu-cycles) and software (intel_cqm/llc_occupancy/) event. We then - * wait for the hardware perf counter to overflow and generate a PMI, - * which triggers an event read for both of the events in the group. - * - * Since reading Intel CQM event counters requires sending SMP IPIs, the - * CQM pmu needs to handle the above situation gracefully, and return - * the last read counter value to avoid triggering a WARN_ON_ONCE() in - * smp_call_function_many() caused by sending IPIs from NMI context. - */ -int test__intel_cqm_count_nmi_context(struct test_suite *test __maybe_unused, int subtest __maybe_unused) -{ - struct evlist *evlist = NULL; - struct evsel *evsel = NULL; - struct perf_event_attr pe; - int i, fd[2], flag, ret; - size_t mmap_len; - void *event; - pid_t pid; - int err = TEST_FAIL; - - flag = perf_event_open_cloexec_flag(); - - evlist = evlist__new(); - if (!evlist) { - pr_debug("evlist__new failed\n"); - return TEST_FAIL; - } - - ret = parse_event(evlist, "intel_cqm/llc_occupancy/"); - if (ret) { - pr_debug("parse_events failed, is \"intel_cqm/llc_occupancy/\" available?\n"); - err = TEST_SKIP; - goto out; - } - - evsel = evlist__first(evlist); - if (!evsel) { - pr_debug("evlist__first failed\n"); - goto out; - } - - memset(&pe, 0, sizeof(pe)); - pe.size = sizeof(pe); - - pe.type = PERF_TYPE_HARDWARE; - pe.config = PERF_COUNT_HW_CPU_CYCLES; - pe.read_format = PERF_FORMAT_GROUP; - - pe.sample_period = 128; - pe.sample_type = PERF_SAMPLE_IP | PERF_SAMPLE_READ; - - pid = spawn(); - - fd[0] = sys_perf_event_open(&pe, pid, -1, -1, flag); - if (fd[0] < 0) { - pr_debug("failed to open event\n"); - goto out; - } - - memset(&pe, 0, sizeof(pe)); - pe.size = sizeof(pe); - - pe.type = evsel->attr.type; - pe.config = evsel->attr.config; - - fd[1] = sys_perf_event_open(&pe, pid, -1, fd[0], flag); - if (fd[1] < 0) { - pr_debug("failed to open event\n"); - goto out; - } - - /* - * Pick a power-of-two number of pages + 1 for the meta-data - * page (struct perf_event_mmap_page). See tools/perf/design.txt. - */ - mmap_len = page_size * 65; - - event = mmap(NULL, mmap_len, PROT_READ, MAP_SHARED, fd[0], 0); - if (event == (void *)(-1)) { - pr_debug("failed to mmap %d\n", errno); - goto out; - } - - sleep(1); - - err = TEST_OK; - - munmap(event, mmap_len); - - for (i = 0; i < 2; i++) - close(fd[i]); - - kill(pid, SIGKILL); - wait(NULL); -out: - evlist__delete(evlist); - return err; -} diff --git a/tools/perf/arch/x86/tests/intel-pt-test.c b/tools/perf/arch/x86/tests/intel-pt-test.c index 09d61fa736e3..b217ed67cd4e 100644 --- a/tools/perf/arch/x86/tests/intel-pt-test.c +++ b/tools/perf/arch/x86/tests/intel-pt-test.c @@ -375,7 +375,7 @@ static int get_pt_caps(int cpu, struct pt_caps *caps) return 0; } -static bool is_hydrid(void) +static bool is_hybrid(void) { unsigned int eax, ebx, ecx, edx = 0; bool result; @@ -441,7 +441,7 @@ int test__intel_pt_hybrid_compat(struct test_suite *test, int subtest) int ret = TEST_OK; int cpu; - if (!is_hydrid()) { + if (!is_hybrid()) { test->test_cases[subtest].skip_reason = "not hybrid"; return TEST_SKIP; } |