diff options
Diffstat (limited to 'tools/perf/pmu-events/arch/x86/bonnell/memory.json')
-rw-r--r-- | tools/perf/pmu-events/arch/x86/bonnell/memory.json | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/tools/perf/pmu-events/arch/x86/bonnell/memory.json b/tools/perf/pmu-events/arch/x86/bonnell/memory.json index ac02dc2482c8..f8b45b6fb4d3 100644 --- a/tools/perf/pmu-events/arch/x86/bonnell/memory.json +++ b/tools/perf/pmu-events/arch/x86/bonnell/memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Nonzero segbase 1 bubble", + "Counter": "0,1", "EventCode": "0x5", "EventName": "MISALIGN_MEM_REF.BUBBLE", "SampleAfterValue": "200000", @@ -8,6 +9,7 @@ }, { "BriefDescription": "Nonzero segbase load 1 bubble", + "Counter": "0,1", "EventCode": "0x5", "EventName": "MISALIGN_MEM_REF.LD_BUBBLE", "SampleAfterValue": "200000", @@ -15,6 +17,7 @@ }, { "BriefDescription": "Load splits", + "Counter": "0,1", "EventCode": "0x5", "EventName": "MISALIGN_MEM_REF.LD_SPLIT", "SampleAfterValue": "200000", @@ -22,6 +25,7 @@ }, { "BriefDescription": "Load splits (At Retirement)", + "Counter": "0,1", "EventCode": "0x5", "EventName": "MISALIGN_MEM_REF.LD_SPLIT.AR", "SampleAfterValue": "200000", @@ -29,6 +33,7 @@ }, { "BriefDescription": "Nonzero segbase ld-op-st 1 bubble", + "Counter": "0,1", "EventCode": "0x5", "EventName": "MISALIGN_MEM_REF.RMW_BUBBLE", "SampleAfterValue": "200000", @@ -36,6 +41,7 @@ }, { "BriefDescription": "ld-op-st splits", + "Counter": "0,1", "EventCode": "0x5", "EventName": "MISALIGN_MEM_REF.RMW_SPLIT", "SampleAfterValue": "200000", @@ -43,6 +49,7 @@ }, { "BriefDescription": "Memory references that cross an 8-byte boundary.", + "Counter": "0,1", "EventCode": "0x5", "EventName": "MISALIGN_MEM_REF.SPLIT", "SampleAfterValue": "200000", @@ -50,6 +57,7 @@ }, { "BriefDescription": "Memory references that cross an 8-byte boundary (At Retirement)", + "Counter": "0,1", "EventCode": "0x5", "EventName": "MISALIGN_MEM_REF.SPLIT.AR", "SampleAfterValue": "200000", @@ -57,6 +65,7 @@ }, { "BriefDescription": "Nonzero segbase store 1 bubble", + "Counter": "0,1", "EventCode": "0x5", "EventName": "MISALIGN_MEM_REF.ST_BUBBLE", "SampleAfterValue": "200000", @@ -64,6 +73,7 @@ }, { "BriefDescription": "Store splits", + "Counter": "0,1", "EventCode": "0x5", "EventName": "MISALIGN_MEM_REF.ST_SPLIT", "SampleAfterValue": "200000", @@ -71,6 +81,7 @@ }, { "BriefDescription": "Store splits (Ar Retirement)", + "Counter": "0,1", "EventCode": "0x5", "EventName": "MISALIGN_MEM_REF.ST_SPLIT.AR", "SampleAfterValue": "200000", @@ -78,6 +89,7 @@ }, { "BriefDescription": "L1 hardware prefetch request", + "Counter": "0,1", "EventCode": "0x7", "EventName": "PREFETCH.HW_PREFETCH", "SampleAfterValue": "2000000", @@ -85,6 +97,7 @@ }, { "BriefDescription": "Streaming SIMD Extensions (SSE) Prefetch NTA instructions executed", + "Counter": "0,1", "EventCode": "0x7", "EventName": "PREFETCH.PREFETCHNTA", "SampleAfterValue": "200000", @@ -92,6 +105,7 @@ }, { "BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT0 instructions executed.", + "Counter": "0,1", "EventCode": "0x7", "EventName": "PREFETCH.PREFETCHT0", "SampleAfterValue": "200000", @@ -99,6 +113,7 @@ }, { "BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT1 instructions executed.", + "Counter": "0,1", "EventCode": "0x7", "EventName": "PREFETCH.PREFETCHT1", "SampleAfterValue": "200000", @@ -106,6 +121,7 @@ }, { "BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT2 instructions executed.", + "Counter": "0,1", "EventCode": "0x7", "EventName": "PREFETCH.PREFETCHT2", "SampleAfterValue": "200000", @@ -113,6 +129,7 @@ }, { "BriefDescription": "Any Software prefetch", + "Counter": "0,1", "EventCode": "0x7", "EventName": "PREFETCH.SOFTWARE_PREFETCH", "SampleAfterValue": "200000", @@ -120,6 +137,7 @@ }, { "BriefDescription": "Any Software prefetch", + "Counter": "0,1", "EventCode": "0x7", "EventName": "PREFETCH.SOFTWARE_PREFETCH.AR", "SampleAfterValue": "200000", @@ -127,6 +145,7 @@ }, { "BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT1 and PrefetchT2 instructions executed", + "Counter": "0,1", "EventCode": "0x7", "EventName": "PREFETCH.SW_L2", "SampleAfterValue": "200000", |