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-rw-r--r--tools/perf/pmu-events/arch/x86/nehalemep/cache.json352
1 files changed, 352 insertions, 0 deletions
diff --git a/tools/perf/pmu-events/arch/x86/nehalemep/cache.json b/tools/perf/pmu-events/arch/x86/nehalemep/cache.json
index 5113a4e059e4..c9d154f1d09a 100644
--- a/tools/perf/pmu-events/arch/x86/nehalemep/cache.json
+++ b/tools/perf/pmu-events/arch/x86/nehalemep/cache.json
@@ -1,6 +1,7 @@
[
{
"BriefDescription": "Cycles L1D locked",
+ "Counter": "0,1",
"EventCode": "0x63",
"EventName": "CACHE_LOCK_CYCLES.L1D",
"SampleAfterValue": "2000000",
@@ -8,6 +9,7 @@
},
{
"BriefDescription": "Cycles L1D and L2 locked",
+ "Counter": "0,1",
"EventCode": "0x63",
"EventName": "CACHE_LOCK_CYCLES.L1D_L2",
"SampleAfterValue": "2000000",
@@ -15,6 +17,7 @@
},
{
"BriefDescription": "L1D cache lines replaced in M state",
+ "Counter": "0,1",
"EventCode": "0x51",
"EventName": "L1D.M_EVICT",
"SampleAfterValue": "2000000",
@@ -22,6 +25,7 @@
},
{
"BriefDescription": "L1D cache lines allocated in the M state",
+ "Counter": "0,1",
"EventCode": "0x51",
"EventName": "L1D.M_REPL",
"SampleAfterValue": "2000000",
@@ -29,6 +33,7 @@
},
{
"BriefDescription": "L1D snoop eviction of cache lines in M state",
+ "Counter": "0,1",
"EventCode": "0x51",
"EventName": "L1D.M_SNOOP_EVICT",
"SampleAfterValue": "2000000",
@@ -36,6 +41,7 @@
},
{
"BriefDescription": "L1 data cache lines allocated",
+ "Counter": "0,1",
"EventCode": "0x51",
"EventName": "L1D.REPL",
"SampleAfterValue": "2000000",
@@ -43,6 +49,7 @@
},
{
"BriefDescription": "All references to the L1 data cache",
+ "Counter": "0,1",
"EventCode": "0x43",
"EventName": "L1D_ALL_REF.ANY",
"SampleAfterValue": "2000000",
@@ -50,6 +57,7 @@
},
{
"BriefDescription": "L1 data cacheable reads and writes",
+ "Counter": "0,1",
"EventCode": "0x43",
"EventName": "L1D_ALL_REF.CACHEABLE",
"SampleAfterValue": "2000000",
@@ -57,6 +65,7 @@
},
{
"BriefDescription": "L1 data cache read in E state",
+ "Counter": "0,1",
"EventCode": "0x40",
"EventName": "L1D_CACHE_LD.E_STATE",
"SampleAfterValue": "2000000",
@@ -64,6 +73,7 @@
},
{
"BriefDescription": "L1 data cache read in I state (misses)",
+ "Counter": "0,1",
"EventCode": "0x40",
"EventName": "L1D_CACHE_LD.I_STATE",
"SampleAfterValue": "2000000",
@@ -71,6 +81,7 @@
},
{
"BriefDescription": "L1 data cache reads",
+ "Counter": "0,1",
"EventCode": "0x40",
"EventName": "L1D_CACHE_LD.MESI",
"SampleAfterValue": "2000000",
@@ -78,6 +89,7 @@
},
{
"BriefDescription": "L1 data cache read in M state",
+ "Counter": "0,1",
"EventCode": "0x40",
"EventName": "L1D_CACHE_LD.M_STATE",
"SampleAfterValue": "2000000",
@@ -85,6 +97,7 @@
},
{
"BriefDescription": "L1 data cache read in S state",
+ "Counter": "0,1",
"EventCode": "0x40",
"EventName": "L1D_CACHE_LD.S_STATE",
"SampleAfterValue": "2000000",
@@ -92,6 +105,7 @@
},
{
"BriefDescription": "L1 data cache load locks in E state",
+ "Counter": "0,1",
"EventCode": "0x42",
"EventName": "L1D_CACHE_LOCK.E_STATE",
"SampleAfterValue": "2000000",
@@ -99,6 +113,7 @@
},
{
"BriefDescription": "L1 data cache load lock hits",
+ "Counter": "0,1",
"EventCode": "0x42",
"EventName": "L1D_CACHE_LOCK.HIT",
"SampleAfterValue": "2000000",
@@ -106,6 +121,7 @@
},
{
"BriefDescription": "L1 data cache load locks in M state",
+ "Counter": "0,1",
"EventCode": "0x42",
"EventName": "L1D_CACHE_LOCK.M_STATE",
"SampleAfterValue": "2000000",
@@ -113,6 +129,7 @@
},
{
"BriefDescription": "L1 data cache load locks in S state",
+ "Counter": "0,1",
"EventCode": "0x42",
"EventName": "L1D_CACHE_LOCK.S_STATE",
"SampleAfterValue": "2000000",
@@ -120,6 +137,7 @@
},
{
"BriefDescription": "L1D load lock accepted in fill buffer",
+ "Counter": "0,1",
"EventCode": "0x53",
"EventName": "L1D_CACHE_LOCK_FB_HIT",
"SampleAfterValue": "2000000",
@@ -127,6 +145,7 @@
},
{
"BriefDescription": "L1D prefetch load lock accepted in fill buffer",
+ "Counter": "0,1",
"EventCode": "0x52",
"EventName": "L1D_CACHE_PREFETCH_LOCK_FB_HIT",
"SampleAfterValue": "2000000",
@@ -134,6 +153,7 @@
},
{
"BriefDescription": "L1 data cache stores in E state",
+ "Counter": "0,1",
"EventCode": "0x41",
"EventName": "L1D_CACHE_ST.E_STATE",
"SampleAfterValue": "2000000",
@@ -141,6 +161,7 @@
},
{
"BriefDescription": "L1 data cache stores in M state",
+ "Counter": "0,1",
"EventCode": "0x41",
"EventName": "L1D_CACHE_ST.M_STATE",
"SampleAfterValue": "2000000",
@@ -148,6 +169,7 @@
},
{
"BriefDescription": "L1 data cache stores in S state",
+ "Counter": "0,1",
"EventCode": "0x41",
"EventName": "L1D_CACHE_ST.S_STATE",
"SampleAfterValue": "2000000",
@@ -155,6 +177,7 @@
},
{
"BriefDescription": "L1D hardware prefetch misses",
+ "Counter": "0,1",
"EventCode": "0x4E",
"EventName": "L1D_PREFETCH.MISS",
"SampleAfterValue": "200000",
@@ -162,6 +185,7 @@
},
{
"BriefDescription": "L1D hardware prefetch requests",
+ "Counter": "0,1",
"EventCode": "0x4E",
"EventName": "L1D_PREFETCH.REQUESTS",
"SampleAfterValue": "200000",
@@ -169,6 +193,7 @@
},
{
"BriefDescription": "L1D hardware prefetch requests triggered",
+ "Counter": "0,1",
"EventCode": "0x4E",
"EventName": "L1D_PREFETCH.TRIGGERS",
"SampleAfterValue": "200000",
@@ -176,6 +201,7 @@
},
{
"BriefDescription": "L1 writebacks to L2 in E state",
+ "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "L1D_WB_L2.E_STATE",
"SampleAfterValue": "100000",
@@ -183,6 +209,7 @@
},
{
"BriefDescription": "L1 writebacks to L2 in I state (misses)",
+ "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "L1D_WB_L2.I_STATE",
"SampleAfterValue": "100000",
@@ -190,6 +217,7 @@
},
{
"BriefDescription": "All L1 writebacks to L2",
+ "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "L1D_WB_L2.MESI",
"SampleAfterValue": "100000",
@@ -197,6 +225,7 @@
},
{
"BriefDescription": "L1 writebacks to L2 in M state",
+ "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "L1D_WB_L2.M_STATE",
"SampleAfterValue": "100000",
@@ -204,13 +233,47 @@
},
{
"BriefDescription": "L1 writebacks to L2 in S state",
+ "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "L1D_WB_L2.S_STATE",
"SampleAfterValue": "100000",
"UMask": "0x2"
},
{
+ "BriefDescription": "L1I instruction fetch stall cycles",
+ "Counter": "0,1,2,3",
+ "EventCode": "0x80",
+ "EventName": "L1I.CYCLES_STALLED",
+ "SampleAfterValue": "2000000",
+ "UMask": "0x4"
+ },
+ {
+ "BriefDescription": "L1I instruction fetch hits",
+ "Counter": "0,1,2,3",
+ "EventCode": "0x80",
+ "EventName": "L1I.HITS",
+ "SampleAfterValue": "2000000",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "L1I instruction fetch misses",
+ "Counter": "0,1,2,3",
+ "EventCode": "0x80",
+ "EventName": "L1I.MISSES",
+ "SampleAfterValue": "2000000",
+ "UMask": "0x2"
+ },
+ {
+ "BriefDescription": "L1I Instruction fetches",
+ "Counter": "0,1,2,3",
+ "EventCode": "0x80",
+ "EventName": "L1I.READS",
+ "SampleAfterValue": "2000000",
+ "UMask": "0x3"
+ },
+ {
"BriefDescription": "All L2 data requests",
+ "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.ANY",
"SampleAfterValue": "200000",
@@ -218,6 +281,7 @@
},
{
"BriefDescription": "L2 data demand loads in E state",
+ "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.DEMAND.E_STATE",
"SampleAfterValue": "200000",
@@ -225,6 +289,7 @@
},
{
"BriefDescription": "L2 data demand loads in I state (misses)",
+ "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.DEMAND.I_STATE",
"SampleAfterValue": "200000",
@@ -232,6 +297,7 @@
},
{
"BriefDescription": "L2 data demand requests",
+ "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.DEMAND.MESI",
"SampleAfterValue": "200000",
@@ -239,6 +305,7 @@
},
{
"BriefDescription": "L2 data demand loads in M state",
+ "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.DEMAND.M_STATE",
"SampleAfterValue": "200000",
@@ -246,6 +313,7 @@
},
{
"BriefDescription": "L2 data demand loads in S state",
+ "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.DEMAND.S_STATE",
"SampleAfterValue": "200000",
@@ -253,6 +321,7 @@
},
{
"BriefDescription": "L2 data prefetches in E state",
+ "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.PREFETCH.E_STATE",
"SampleAfterValue": "200000",
@@ -260,6 +329,7 @@
},
{
"BriefDescription": "L2 data prefetches in the I state (misses)",
+ "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.PREFETCH.I_STATE",
"SampleAfterValue": "200000",
@@ -267,6 +337,7 @@
},
{
"BriefDescription": "All L2 data prefetches",
+ "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.PREFETCH.MESI",
"SampleAfterValue": "200000",
@@ -274,6 +345,7 @@
},
{
"BriefDescription": "L2 data prefetches in M state",
+ "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.PREFETCH.M_STATE",
"SampleAfterValue": "200000",
@@ -281,6 +353,7 @@
},
{
"BriefDescription": "L2 data prefetches in the S state",
+ "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.PREFETCH.S_STATE",
"SampleAfterValue": "200000",
@@ -288,6 +361,7 @@
},
{
"BriefDescription": "L2 lines allocated",
+ "Counter": "0,1,2,3",
"EventCode": "0xF1",
"EventName": "L2_LINES_IN.ANY",
"SampleAfterValue": "100000",
@@ -295,6 +369,7 @@
},
{
"BriefDescription": "L2 lines allocated in the E state",
+ "Counter": "0,1,2,3",
"EventCode": "0xF1",
"EventName": "L2_LINES_IN.E_STATE",
"SampleAfterValue": "100000",
@@ -302,6 +377,7 @@
},
{
"BriefDescription": "L2 lines allocated in the S state",
+ "Counter": "0,1,2,3",
"EventCode": "0xF1",
"EventName": "L2_LINES_IN.S_STATE",
"SampleAfterValue": "100000",
@@ -309,6 +385,7 @@
},
{
"BriefDescription": "L2 lines evicted",
+ "Counter": "0,1,2,3",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.ANY",
"SampleAfterValue": "100000",
@@ -316,6 +393,7 @@
},
{
"BriefDescription": "L2 lines evicted by a demand request",
+ "Counter": "0,1,2,3",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.DEMAND_CLEAN",
"SampleAfterValue": "100000",
@@ -323,6 +401,7 @@
},
{
"BriefDescription": "L2 modified lines evicted by a demand request",
+ "Counter": "0,1,2,3",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.DEMAND_DIRTY",
"SampleAfterValue": "100000",
@@ -330,6 +409,7 @@
},
{
"BriefDescription": "L2 lines evicted by a prefetch request",
+ "Counter": "0,1,2,3",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.PREFETCH_CLEAN",
"SampleAfterValue": "100000",
@@ -337,6 +417,7 @@
},
{
"BriefDescription": "L2 modified lines evicted by a prefetch request",
+ "Counter": "0,1,2,3",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.PREFETCH_DIRTY",
"SampleAfterValue": "100000",
@@ -344,6 +425,7 @@
},
{
"BriefDescription": "L2 instruction fetches",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.IFETCHES",
"SampleAfterValue": "200000",
@@ -351,6 +433,7 @@
},
{
"BriefDescription": "L2 instruction fetch hits",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.IFETCH_HIT",
"SampleAfterValue": "200000",
@@ -358,6 +441,7 @@
},
{
"BriefDescription": "L2 instruction fetch misses",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.IFETCH_MISS",
"SampleAfterValue": "200000",
@@ -365,6 +449,7 @@
},
{
"BriefDescription": "L2 load hits",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.LD_HIT",
"SampleAfterValue": "200000",
@@ -372,6 +457,7 @@
},
{
"BriefDescription": "L2 load misses",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.LD_MISS",
"SampleAfterValue": "200000",
@@ -379,6 +465,7 @@
},
{
"BriefDescription": "L2 requests",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.LOADS",
"SampleAfterValue": "200000",
@@ -386,6 +473,7 @@
},
{
"BriefDescription": "All L2 misses",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.MISS",
"SampleAfterValue": "200000",
@@ -393,6 +481,7 @@
},
{
"BriefDescription": "All L2 prefetches",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.PREFETCHES",
"SampleAfterValue": "200000",
@@ -400,6 +489,7 @@
},
{
"BriefDescription": "L2 prefetch hits",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.PREFETCH_HIT",
"SampleAfterValue": "200000",
@@ -407,6 +497,7 @@
},
{
"BriefDescription": "L2 prefetch misses",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.PREFETCH_MISS",
"SampleAfterValue": "200000",
@@ -414,6 +505,7 @@
},
{
"BriefDescription": "All L2 requests",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.REFERENCES",
"SampleAfterValue": "200000",
@@ -421,6 +513,7 @@
},
{
"BriefDescription": "L2 RFO requests",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.RFOS",
"SampleAfterValue": "200000",
@@ -428,6 +521,7 @@
},
{
"BriefDescription": "L2 RFO hits",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.RFO_HIT",
"SampleAfterValue": "200000",
@@ -435,6 +529,7 @@
},
{
"BriefDescription": "L2 RFO misses",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.RFO_MISS",
"SampleAfterValue": "200000",
@@ -442,6 +537,7 @@
},
{
"BriefDescription": "All L2 transactions",
+ "Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANSACTIONS.ANY",
"SampleAfterValue": "200000",
@@ -449,6 +545,7 @@
},
{
"BriefDescription": "L2 fill transactions",
+ "Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANSACTIONS.FILL",
"SampleAfterValue": "200000",
@@ -456,6 +553,7 @@
},
{
"BriefDescription": "L2 instruction fetch transactions",
+ "Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANSACTIONS.IFETCH",
"SampleAfterValue": "200000",
@@ -463,6 +561,7 @@
},
{
"BriefDescription": "L1D writeback to L2 transactions",
+ "Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANSACTIONS.L1D_WB",
"SampleAfterValue": "200000",
@@ -470,6 +569,7 @@
},
{
"BriefDescription": "L2 Load transactions",
+ "Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANSACTIONS.LOAD",
"SampleAfterValue": "200000",
@@ -477,6 +577,7 @@
},
{
"BriefDescription": "L2 prefetch transactions",
+ "Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANSACTIONS.PREFETCH",
"SampleAfterValue": "200000",
@@ -484,6 +585,7 @@
},
{
"BriefDescription": "L2 RFO transactions",
+ "Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANSACTIONS.RFO",
"SampleAfterValue": "200000",
@@ -491,6 +593,7 @@
},
{
"BriefDescription": "L2 writeback to LLC transactions",
+ "Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANSACTIONS.WB",
"SampleAfterValue": "200000",
@@ -498,6 +601,7 @@
},
{
"BriefDescription": "L2 demand lock RFOs in E state",
+ "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.LOCK.E_STATE",
"SampleAfterValue": "100000",
@@ -505,6 +609,7 @@
},
{
"BriefDescription": "All demand L2 lock RFOs that hit the cache",
+ "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.LOCK.HIT",
"SampleAfterValue": "100000",
@@ -512,6 +617,7 @@
},
{
"BriefDescription": "L2 demand lock RFOs in I state (misses)",
+ "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.LOCK.I_STATE",
"SampleAfterValue": "100000",
@@ -519,6 +625,7 @@
},
{
"BriefDescription": "All demand L2 lock RFOs",
+ "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.LOCK.MESI",
"SampleAfterValue": "100000",
@@ -526,6 +633,7 @@
},
{
"BriefDescription": "L2 demand lock RFOs in M state",
+ "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.LOCK.M_STATE",
"SampleAfterValue": "100000",
@@ -533,6 +641,7 @@
},
{
"BriefDescription": "L2 demand lock RFOs in S state",
+ "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.LOCK.S_STATE",
"SampleAfterValue": "100000",
@@ -540,6 +649,7 @@
},
{
"BriefDescription": "All L2 demand store RFOs that hit the cache",
+ "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.RFO.HIT",
"SampleAfterValue": "100000",
@@ -547,6 +657,7 @@
},
{
"BriefDescription": "L2 demand store RFOs in I state (misses)",
+ "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.RFO.I_STATE",
"SampleAfterValue": "100000",
@@ -554,6 +665,7 @@
},
{
"BriefDescription": "All L2 demand store RFOs",
+ "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.RFO.MESI",
"SampleAfterValue": "100000",
@@ -561,6 +673,7 @@
},
{
"BriefDescription": "L2 demand store RFOs in M state",
+ "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.RFO.M_STATE",
"SampleAfterValue": "100000",
@@ -568,6 +681,7 @@
},
{
"BriefDescription": "L2 demand store RFOs in S state",
+ "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.RFO.S_STATE",
"SampleAfterValue": "100000",
@@ -575,6 +689,7 @@
},
{
"BriefDescription": "Longest latency cache miss",
+ "Counter": "0,1,2,3",
"EventCode": "0x2E",
"EventName": "LONGEST_LAT_CACHE.MISS",
"SampleAfterValue": "100000",
@@ -582,6 +697,7 @@
},
{
"BriefDescription": "Longest latency cache reference",
+ "Counter": "0,1,2,3",
"EventCode": "0x2E",
"EventName": "LONGEST_LAT_CACHE.REFERENCE",
"SampleAfterValue": "200000",
@@ -589,6 +705,7 @@
},
{
"BriefDescription": "Memory instructions retired above 0 clocks (Precise Event)",
+ "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_0",
"MSRIndex": "0x3F6",
@@ -598,6 +715,7 @@
},
{
"BriefDescription": "Memory instructions retired above 1024 clocks (Precise Event)",
+ "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_1024",
"MSRIndex": "0x3F6",
@@ -608,6 +726,7 @@
},
{
"BriefDescription": "Memory instructions retired above 128 clocks (Precise Event)",
+ "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_128",
"MSRIndex": "0x3F6",
@@ -618,6 +737,7 @@
},
{
"BriefDescription": "Memory instructions retired above 16 clocks (Precise Event)",
+ "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16",
"MSRIndex": "0x3F6",
@@ -628,6 +748,7 @@
},
{
"BriefDescription": "Memory instructions retired above 16384 clocks (Precise Event)",
+ "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16384",
"MSRIndex": "0x3F6",
@@ -638,6 +759,7 @@
},
{
"BriefDescription": "Memory instructions retired above 2048 clocks (Precise Event)",
+ "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_2048",
"MSRIndex": "0x3F6",
@@ -648,6 +770,7 @@
},
{
"BriefDescription": "Memory instructions retired above 256 clocks (Precise Event)",
+ "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_256",
"MSRIndex": "0x3F6",
@@ -658,6 +781,7 @@
},
{
"BriefDescription": "Memory instructions retired above 32 clocks (Precise Event)",
+ "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32",
"MSRIndex": "0x3F6",
@@ -668,6 +792,7 @@
},
{
"BriefDescription": "Memory instructions retired above 32768 clocks (Precise Event)",
+ "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32768",
"MSRIndex": "0x3F6",
@@ -678,6 +803,7 @@
},
{
"BriefDescription": "Memory instructions retired above 4 clocks (Precise Event)",
+ "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4",
"MSRIndex": "0x3F6",
@@ -688,6 +814,7 @@
},
{
"BriefDescription": "Memory instructions retired above 4096 clocks (Precise Event)",
+ "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4096",
"MSRIndex": "0x3F6",
@@ -698,6 +825,7 @@
},
{
"BriefDescription": "Memory instructions retired above 512 clocks (Precise Event)",
+ "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_512",
"MSRIndex": "0x3F6",
@@ -708,6 +836,7 @@
},
{
"BriefDescription": "Memory instructions retired above 64 clocks (Precise Event)",
+ "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_64",
"MSRIndex": "0x3F6",
@@ -718,6 +847,7 @@
},
{
"BriefDescription": "Memory instructions retired above 8 clocks (Precise Event)",
+ "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8",
"MSRIndex": "0x3F6",
@@ -728,6 +858,7 @@
},
{
"BriefDescription": "Memory instructions retired above 8192 clocks (Precise Event)",
+ "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8192",
"MSRIndex": "0x3F6",
@@ -738,6 +869,7 @@
},
{
"BriefDescription": "Instructions retired which contains a load (Precise Event)",
+ "Counter": "0,1,2,3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LOADS",
"PEBS": "1",
@@ -746,6 +878,7 @@
},
{
"BriefDescription": "Instructions retired which contains a store (Precise Event)",
+ "Counter": "0,1,2,3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.STORES",
"PEBS": "1",
@@ -754,6 +887,7 @@
},
{
"BriefDescription": "Retired loads that miss L1D and hit an previously allocated LFB (Precise Event)",
+ "Counter": "0,1,2,3",
"EventCode": "0xCB",
"EventName": "MEM_LOAD_RETIRED.HIT_LFB",
"PEBS": "1",
@@ -762,6 +896,7 @@
},
{
"BriefDescription": "Retired loads that hit the L1 data cache (Precise Event)",
+ "Counter": "0,1,2,3",
"EventCode": "0xCB",
"EventName": "MEM_LOAD_RETIRED.L1D_HIT",
"PEBS": "1",
@@ -770,6 +905,7 @@
},
{
"BriefDescription": "Retired loads that hit the L2 cache (Precise Event)",
+ "Counter": "0,1,2,3",
"EventCode": "0xCB",
"EventName": "MEM_LOAD_RETIRED.L2_HIT",
"PEBS": "1",
@@ -778,6 +914,7 @@
},
{
"BriefDescription": "Retired loads that miss the LLC cache (Precise Event)",
+ "Counter": "0,1,2,3",
"EventCode": "0xCB",
"EventName": "MEM_LOAD_RETIRED.LLC_MISS",
"PEBS": "1",
@@ -786,6 +923,7 @@
},
{
"BriefDescription": "Retired loads that hit valid versions in the LLC cache (Precise Event)",
+ "Counter": "0,1,2,3",
"EventCode": "0xCB",
"EventName": "MEM_LOAD_RETIRED.LLC_UNSHARED_HIT",
"PEBS": "1",
@@ -794,6 +932,7 @@
},
{
"BriefDescription": "Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)",
+ "Counter": "0,1,2,3",
"EventCode": "0xCB",
"EventName": "MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM",
"PEBS": "1",
@@ -802,6 +941,7 @@
},
{
"BriefDescription": "Load instructions retired with a data source of local DRAM or locally homed remote hitm (Precise Event)",
+ "Counter": "0,1,2,3",
"EventCode": "0xF",
"EventName": "MEM_UNCORE_RETIRED.LOCAL_DRAM",
"PEBS": "1",
@@ -810,6 +950,7 @@
},
{
"BriefDescription": "Load instructions retired that HIT modified data in sibling core (Precise Event)",
+ "Counter": "0,1,2,3",
"EventCode": "0xF",
"EventName": "MEM_UNCORE_RETIRED.OTHER_CORE_L2_HITM",
"PEBS": "1",
@@ -818,6 +959,7 @@
},
{
"BriefDescription": "Load instructions retired remote cache HIT data source (Precise Event)",
+ "Counter": "0,1,2,3",
"EventCode": "0xF",
"EventName": "MEM_UNCORE_RETIRED.REMOTE_CACHE_LOCAL_HOME_HIT",
"PEBS": "1",
@@ -826,6 +968,7 @@
},
{
"BriefDescription": "Load instructions retired remote DRAM and remote home-remote cache HITM (Precise Event)",
+ "Counter": "0,1,2,3",
"EventCode": "0xF",
"EventName": "MEM_UNCORE_RETIRED.REMOTE_DRAM",
"PEBS": "1",
@@ -834,6 +977,7 @@
},
{
"BriefDescription": "Load instructions retired IO (Precise Event)",
+ "Counter": "0,1,2,3",
"EventCode": "0xF",
"EventName": "MEM_UNCORE_RETIRED.UNCACHEABLE",
"PEBS": "1",
@@ -842,6 +986,7 @@
},
{
"BriefDescription": "Offcore L1 data cache writebacks",
+ "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.L1D_WRITEBACK",
"SampleAfterValue": "100000",
@@ -849,6 +994,7 @@
},
{
"BriefDescription": "Offcore requests blocked due to Super Queue full",
+ "Counter": "0,1,2,3",
"EventCode": "0xB2",
"EventName": "OFFCORE_REQUESTS_SQ_FULL",
"SampleAfterValue": "100000",
@@ -856,6 +1002,7 @@
},
{
"BriefDescription": "Offcore data reads satisfied by any cache or DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -865,6 +1012,7 @@
},
{
"BriefDescription": "All offcore data reads",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LOCATION",
"MSRIndex": "0x1A6",
@@ -874,6 +1022,7 @@
},
{
"BriefDescription": "Offcore data reads satisfied by the IO, CSR, MMIO unit",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
@@ -883,6 +1032,7 @@
},
{
"BriefDescription": "Offcore data reads satisfied by the LLC and not found in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
@@ -892,6 +1042,7 @@
},
{
"BriefDescription": "Offcore data reads satisfied by the LLC and HIT in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
@@ -901,6 +1052,7 @@
},
{
"BriefDescription": "Offcore data reads satisfied by the LLC and HITM in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
@@ -910,6 +1062,7 @@
},
{
"BriefDescription": "Offcore data reads satisfied by the LLC",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE",
"MSRIndex": "0x1A6",
@@ -919,6 +1072,7 @@
},
{
"BriefDescription": "Offcore data reads satisfied by the LLC or local DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -928,6 +1082,7 @@
},
{
"BriefDescription": "Offcore data reads satisfied by a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE",
"MSRIndex": "0x1A6",
@@ -937,6 +1092,7 @@
},
{
"BriefDescription": "Offcore data reads satisfied by a remote cache or remote DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -946,6 +1102,7 @@
},
{
"BriefDescription": "Offcore data reads that HIT in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
@@ -955,6 +1112,7 @@
},
{
"BriefDescription": "Offcore data reads that HITM in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
@@ -964,6 +1122,7 @@
},
{
"BriefDescription": "Offcore code reads satisfied by any cache or DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -973,6 +1132,7 @@
},
{
"BriefDescription": "All offcore code reads",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LOCATION",
"MSRIndex": "0x1A6",
@@ -982,6 +1142,7 @@
},
{
"BriefDescription": "Offcore code reads satisfied by the IO, CSR, MMIO unit",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
@@ -991,6 +1152,7 @@
},
{
"BriefDescription": "Offcore code reads satisfied by the LLC and not found in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
@@ -1000,6 +1162,7 @@
},
{
"BriefDescription": "Offcore code reads satisfied by the LLC and HIT in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
@@ -1009,6 +1172,7 @@
},
{
"BriefDescription": "Offcore code reads satisfied by the LLC and HITM in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
@@ -1018,6 +1182,7 @@
},
{
"BriefDescription": "Offcore code reads satisfied by the LLC",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE",
"MSRIndex": "0x1A6",
@@ -1027,6 +1192,7 @@
},
{
"BriefDescription": "Offcore code reads satisfied by the LLC or local DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -1036,6 +1202,7 @@
},
{
"BriefDescription": "Offcore code reads satisfied by a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE",
"MSRIndex": "0x1A6",
@@ -1045,6 +1212,7 @@
},
{
"BriefDescription": "Offcore code reads satisfied by a remote cache or remote DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -1054,6 +1222,7 @@
},
{
"BriefDescription": "Offcore code reads that HIT in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
@@ -1063,6 +1232,7 @@
},
{
"BriefDescription": "Offcore code reads that HITM in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
@@ -1072,6 +1242,7 @@
},
{
"BriefDescription": "Offcore requests satisfied by any cache or DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -1081,6 +1252,7 @@
},
{
"BriefDescription": "All offcore requests",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LOCATION",
"MSRIndex": "0x1A6",
@@ -1090,6 +1262,7 @@
},
{
"BriefDescription": "Offcore requests satisfied by the IO, CSR, MMIO unit",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
@@ -1099,6 +1272,7 @@
},
{
"BriefDescription": "Offcore requests satisfied by the LLC and not found in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
@@ -1108,6 +1282,7 @@
},
{
"BriefDescription": "Offcore requests satisfied by the LLC and HIT in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
@@ -1117,6 +1292,7 @@
},
{
"BriefDescription": "Offcore requests satisfied by the LLC and HITM in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
@@ -1126,6 +1302,7 @@
},
{
"BriefDescription": "Offcore requests satisfied by the LLC",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE",
"MSRIndex": "0x1A6",
@@ -1135,6 +1312,7 @@
},
{
"BriefDescription": "Offcore requests satisfied by the LLC or local DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -1144,6 +1322,7 @@
},
{
"BriefDescription": "Offcore requests satisfied by a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE",
"MSRIndex": "0x1A6",
@@ -1153,6 +1332,7 @@
},
{
"BriefDescription": "Offcore requests satisfied by a remote cache or remote DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -1162,6 +1342,7 @@
},
{
"BriefDescription": "Offcore requests that HIT in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
@@ -1171,6 +1352,7 @@
},
{
"BriefDescription": "Offcore requests that HITM in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
@@ -1180,6 +1362,7 @@
},
{
"BriefDescription": "Offcore RFO requests satisfied by any cache or DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -1189,6 +1372,7 @@
},
{
"BriefDescription": "All offcore RFO requests",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LOCATION",
"MSRIndex": "0x1A6",
@@ -1198,6 +1382,7 @@
},
{
"BriefDescription": "Offcore RFO requests satisfied by the IO, CSR, MMIO unit",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
@@ -1207,6 +1392,7 @@
},
{
"BriefDescription": "Offcore RFO requests satisfied by the LLC and not found in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
@@ -1216,6 +1402,7 @@
},
{
"BriefDescription": "Offcore RFO requests satisfied by the LLC and HIT in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
@@ -1225,6 +1412,7 @@
},
{
"BriefDescription": "Offcore RFO requests satisfied by the LLC and HITM in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
@@ -1234,6 +1422,7 @@
},
{
"BriefDescription": "Offcore RFO requests satisfied by the LLC",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE",
"MSRIndex": "0x1A6",
@@ -1243,6 +1432,7 @@
},
{
"BriefDescription": "Offcore RFO requests satisfied by the LLC or local DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -1252,6 +1442,7 @@
},
{
"BriefDescription": "Offcore RFO requests satisfied by a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE",
"MSRIndex": "0x1A6",
@@ -1261,6 +1452,7 @@
},
{
"BriefDescription": "Offcore RFO requests satisfied by a remote cache or remote DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -1270,6 +1462,7 @@
},
{
"BriefDescription": "Offcore RFO requests that HIT in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
@@ -1279,6 +1472,7 @@
},
{
"BriefDescription": "Offcore RFO requests that HITM in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
@@ -1288,6 +1482,7 @@
},
{
"BriefDescription": "Offcore writebacks to any cache or DRAM.",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -1297,6 +1492,7 @@
},
{
"BriefDescription": "All offcore writebacks",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.ANY_LOCATION",
"MSRIndex": "0x1A6",
@@ -1306,6 +1502,7 @@
},
{
"BriefDescription": "Offcore writebacks to the IO, CSR, MMIO unit.",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
@@ -1315,6 +1512,7 @@
},
{
"BriefDescription": "Offcore writebacks to the LLC and not found in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
@@ -1324,6 +1522,7 @@
},
{
"BriefDescription": "Offcore writebacks to the LLC and HITM in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
@@ -1333,6 +1532,7 @@
},
{
"BriefDescription": "Offcore writebacks to the LLC",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE",
"MSRIndex": "0x1A6",
@@ -1342,6 +1542,7 @@
},
{
"BriefDescription": "Offcore writebacks to the LLC or local DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -1351,6 +1552,7 @@
},
{
"BriefDescription": "Offcore writebacks to a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE",
"MSRIndex": "0x1A6",
@@ -1360,6 +1562,7 @@
},
{
"BriefDescription": "Offcore writebacks to a remote cache or remote DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -1369,6 +1572,7 @@
},
{
"BriefDescription": "Offcore writebacks that HIT in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
@@ -1378,6 +1582,7 @@
},
{
"BriefDescription": "Offcore writebacks that HITM in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
@@ -1387,6 +1592,7 @@
},
{
"BriefDescription": "Offcore code or data read requests satisfied by any cache or DRAM.",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -1396,6 +1602,7 @@
},
{
"BriefDescription": "All offcore code or data read requests",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LOCATION",
"MSRIndex": "0x1A6",
@@ -1405,6 +1612,7 @@
},
{
"BriefDescription": "Offcore code or data read requests satisfied by the IO, CSR, MMIO unit.",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
@@ -1414,6 +1622,7 @@
},
{
"BriefDescription": "Offcore code or data read requests satisfied by the LLC and not found in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
@@ -1423,6 +1632,7 @@
},
{
"BriefDescription": "Offcore code or data read requests satisfied by the LLC and HIT in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
@@ -1432,6 +1642,7 @@
},
{
"BriefDescription": "Offcore code or data read requests satisfied by the LLC and HITM in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
@@ -1441,6 +1652,7 @@
},
{
"BriefDescription": "Offcore code or data read requests satisfied by the LLC",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE",
"MSRIndex": "0x1A6",
@@ -1450,6 +1662,7 @@
},
{
"BriefDescription": "Offcore code or data read requests satisfied by the LLC or local DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -1459,6 +1672,7 @@
},
{
"BriefDescription": "Offcore code or data read requests satisfied by a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE",
"MSRIndex": "0x1A6",
@@ -1468,6 +1682,7 @@
},
{
"BriefDescription": "Offcore code or data read requests satisfied by a remote cache or remote DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -1477,6 +1692,7 @@
},
{
"BriefDescription": "Offcore code or data read requests that HIT in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
@@ -1486,6 +1702,7 @@
},
{
"BriefDescription": "Offcore code or data read requests that HITM in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
@@ -1495,6 +1712,7 @@
},
{
"BriefDescription": "Offcore request = all data, response = any cache_dram",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -1504,6 +1722,7 @@
},
{
"BriefDescription": "Offcore request = all data, response = any location",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LOCATION",
"MSRIndex": "0x1A6",
@@ -1513,6 +1732,7 @@
},
{
"BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the IO, CSR, MMIO unit",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
@@ -1522,6 +1742,7 @@
},
{
"BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC and not found in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
@@ -1531,6 +1752,7 @@
},
{
"BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC and HIT in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
@@ -1540,6 +1762,7 @@
},
{
"BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC and HITM in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
@@ -1549,6 +1772,7 @@
},
{
"BriefDescription": "Offcore request = all data, response = local cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE",
"MSRIndex": "0x1A6",
@@ -1558,6 +1782,7 @@
},
{
"BriefDescription": "Offcore request = all data, response = local cache or dram",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -1567,6 +1792,7 @@
},
{
"BriefDescription": "Offcore request = all data, response = remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE",
"MSRIndex": "0x1A6",
@@ -1576,6 +1802,7 @@
},
{
"BriefDescription": "Offcore request = all data, response = remote cache or dram",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -1585,6 +1812,7 @@
},
{
"BriefDescription": "Offcore data reads, RFOs, and prefetches that HIT in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
@@ -1594,6 +1822,7 @@
},
{
"BriefDescription": "Offcore data reads, RFOs, and prefetches that HITM in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
@@ -1603,6 +1832,7 @@
},
{
"BriefDescription": "Offcore demand data requests satisfied by any cache or DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -1612,6 +1842,7 @@
},
{
"BriefDescription": "All offcore demand data requests",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LOCATION",
"MSRIndex": "0x1A6",
@@ -1621,6 +1852,7 @@
},
{
"BriefDescription": "Offcore demand data requests satisfied by the IO, CSR, MMIO unit.",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
@@ -1630,6 +1862,7 @@
},
{
"BriefDescription": "Offcore demand data requests satisfied by the LLC and not found in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
@@ -1639,6 +1872,7 @@
},
{
"BriefDescription": "Offcore demand data requests satisfied by the LLC and HIT in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
@@ -1648,6 +1882,7 @@
},
{
"BriefDescription": "Offcore demand data requests satisfied by the LLC and HITM in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
@@ -1657,6 +1892,7 @@
},
{
"BriefDescription": "Offcore demand data requests satisfied by the LLC",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE",
"MSRIndex": "0x1A6",
@@ -1666,6 +1902,7 @@
},
{
"BriefDescription": "Offcore demand data requests satisfied by the LLC or local DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -1675,6 +1912,7 @@
},
{
"BriefDescription": "Offcore demand data requests satisfied by a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE",
"MSRIndex": "0x1A6",
@@ -1684,6 +1922,7 @@
},
{
"BriefDescription": "Offcore demand data requests satisfied by a remote cache or remote DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -1693,6 +1932,7 @@
},
{
"BriefDescription": "Offcore demand data requests that HIT in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
@@ -1702,6 +1942,7 @@
},
{
"BriefDescription": "Offcore demand data requests that HITM in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
@@ -1711,6 +1952,7 @@
},
{
"BriefDescription": "Offcore demand data reads satisfied by any cache or DRAM.",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -1720,6 +1962,7 @@
},
{
"BriefDescription": "All offcore demand data reads",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LOCATION",
"MSRIndex": "0x1A6",
@@ -1729,6 +1972,7 @@
},
{
"BriefDescription": "Offcore demand data reads satisfied by the IO, CSR, MMIO unit",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
@@ -1738,6 +1982,7 @@
},
{
"BriefDescription": "Offcore demand data reads satisfied by the LLC and not found in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
@@ -1747,6 +1992,7 @@
},
{
"BriefDescription": "Offcore demand data reads satisfied by the LLC and HIT in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
@@ -1756,6 +2002,7 @@
},
{
"BriefDescription": "Offcore demand data reads satisfied by the LLC and HITM in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
@@ -1765,6 +2012,7 @@
},
{
"BriefDescription": "Offcore demand data reads satisfied by the LLC",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE",
"MSRIndex": "0x1A6",
@@ -1774,6 +2022,7 @@
},
{
"BriefDescription": "Offcore demand data reads satisfied by the LLC or local DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -1783,6 +2032,7 @@
},
{
"BriefDescription": "Offcore demand data reads satisfied by a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE",
"MSRIndex": "0x1A6",
@@ -1792,6 +2042,7 @@
},
{
"BriefDescription": "Offcore demand data reads satisfied by a remote cache or remote DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -1801,6 +2052,7 @@
},
{
"BriefDescription": "Offcore demand data reads that HIT in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
@@ -1810,6 +2062,7 @@
},
{
"BriefDescription": "Offcore demand data reads that HITM in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
@@ -1819,6 +2072,7 @@
},
{
"BriefDescription": "Offcore demand code reads satisfied by any cache or DRAM.",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -1828,6 +2082,7 @@
},
{
"BriefDescription": "All offcore demand code reads",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LOCATION",
"MSRIndex": "0x1A6",
@@ -1837,6 +2092,7 @@
},
{
"BriefDescription": "Offcore demand code reads satisfied by the IO, CSR, MMIO unit",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
@@ -1846,6 +2102,7 @@
},
{
"BriefDescription": "Offcore demand code reads satisfied by the LLC and not found in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
@@ -1855,6 +2112,7 @@
},
{
"BriefDescription": "Offcore demand code reads satisfied by the LLC and HIT in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
@@ -1864,6 +2122,7 @@
},
{
"BriefDescription": "Offcore demand code reads satisfied by the LLC and HITM in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
@@ -1873,6 +2132,7 @@
},
{
"BriefDescription": "Offcore demand code reads satisfied by the LLC",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE",
"MSRIndex": "0x1A6",
@@ -1882,6 +2142,7 @@
},
{
"BriefDescription": "Offcore demand code reads satisfied by the LLC or local DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -1891,6 +2152,7 @@
},
{
"BriefDescription": "Offcore demand code reads satisfied by a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE",
"MSRIndex": "0x1A6",
@@ -1900,6 +2162,7 @@
},
{
"BriefDescription": "Offcore demand code reads satisfied by a remote cache or remote DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -1909,6 +2172,7 @@
},
{
"BriefDescription": "Offcore demand code reads that HIT in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
@@ -1918,6 +2182,7 @@
},
{
"BriefDescription": "Offcore demand code reads that HITM in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
@@ -1927,6 +2192,7 @@
},
{
"BriefDescription": "Offcore demand RFO requests satisfied by any cache or DRAM.",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -1936,6 +2202,7 @@
},
{
"BriefDescription": "All offcore demand RFO requests",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LOCATION",
"MSRIndex": "0x1A6",
@@ -1945,6 +2212,7 @@
},
{
"BriefDescription": "Offcore demand RFO requests satisfied by the IO, CSR, MMIO unit",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
@@ -1954,6 +2222,7 @@
},
{
"BriefDescription": "Offcore demand RFO requests satisfied by the LLC and not found in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
@@ -1963,6 +2232,7 @@
},
{
"BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HIT in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
@@ -1972,6 +2242,7 @@
},
{
"BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HITM in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
@@ -1981,6 +2252,7 @@
},
{
"BriefDescription": "Offcore demand RFO requests satisfied by the LLC",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE",
"MSRIndex": "0x1A6",
@@ -1990,6 +2262,7 @@
},
{
"BriefDescription": "Offcore demand RFO requests satisfied by the LLC or local DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -1999,6 +2272,7 @@
},
{
"BriefDescription": "Offcore demand RFO requests satisfied by a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE",
"MSRIndex": "0x1A6",
@@ -2008,6 +2282,7 @@
},
{
"BriefDescription": "Offcore demand RFO requests satisfied by a remote cache or remote DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -2017,6 +2292,7 @@
},
{
"BriefDescription": "Offcore demand RFO requests that HIT in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
@@ -2026,6 +2302,7 @@
},
{
"BriefDescription": "Offcore demand RFO requests that HITM in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
@@ -2035,6 +2312,7 @@
},
{
"BriefDescription": "Offcore other requests satisfied by any cache or DRAM.",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.OTHER.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -2044,6 +2322,7 @@
},
{
"BriefDescription": "All offcore other requests",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.OTHER.ANY_LOCATION",
"MSRIndex": "0x1A6",
@@ -2053,6 +2332,7 @@
},
{
"BriefDescription": "Offcore other requests satisfied by the IO, CSR, MMIO unit",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.OTHER.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
@@ -2062,6 +2342,7 @@
},
{
"BriefDescription": "Offcore other requests satisfied by the LLC and not found in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
@@ -2071,6 +2352,7 @@
},
{
"BriefDescription": "Offcore other requests satisfied by the LLC and HIT in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
@@ -2080,6 +2362,7 @@
},
{
"BriefDescription": "Offcore other requests satisfied by the LLC and HITM in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
@@ -2089,6 +2372,7 @@
},
{
"BriefDescription": "Offcore other requests satisfied by the LLC",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE",
"MSRIndex": "0x1A6",
@@ -2098,6 +2382,7 @@
},
{
"BriefDescription": "Offcore other requests satisfied by the LLC or local DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -2107,6 +2392,7 @@
},
{
"BriefDescription": "Offcore other requests satisfied by a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE",
"MSRIndex": "0x1A6",
@@ -2116,6 +2402,7 @@
},
{
"BriefDescription": "Offcore other requests satisfied by a remote cache or remote DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -2125,6 +2412,7 @@
},
{
"BriefDescription": "Offcore other requests that HIT in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
@@ -2134,6 +2422,7 @@
},
{
"BriefDescription": "Offcore other requests that HITM in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
@@ -2143,6 +2432,7 @@
},
{
"BriefDescription": "Offcore prefetch data requests satisfied by any cache or DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -2152,6 +2442,7 @@
},
{
"BriefDescription": "All offcore prefetch data requests",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LOCATION",
"MSRIndex": "0x1A6",
@@ -2161,6 +2452,7 @@
},
{
"BriefDescription": "Offcore prefetch data requests satisfied by the IO, CSR, MMIO unit.",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
@@ -2170,6 +2462,7 @@
},
{
"BriefDescription": "Offcore prefetch data requests satisfied by the LLC and not found in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
@@ -2179,6 +2472,7 @@
},
{
"BriefDescription": "Offcore prefetch data requests satisfied by the LLC and HIT in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
@@ -2188,6 +2482,7 @@
},
{
"BriefDescription": "Offcore prefetch data requests satisfied by the LLC and HITM in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
@@ -2197,6 +2492,7 @@
},
{
"BriefDescription": "Offcore prefetch data requests satisfied by the LLC",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE",
"MSRIndex": "0x1A6",
@@ -2206,6 +2502,7 @@
},
{
"BriefDescription": "Offcore prefetch data requests satisfied by the LLC or local DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -2215,6 +2512,7 @@
},
{
"BriefDescription": "Offcore prefetch data requests satisfied by a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE",
"MSRIndex": "0x1A6",
@@ -2224,6 +2522,7 @@
},
{
"BriefDescription": "Offcore prefetch data requests satisfied by a remote cache or remote DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -2233,6 +2532,7 @@
},
{
"BriefDescription": "Offcore prefetch data requests that HIT in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
@@ -2242,6 +2542,7 @@
},
{
"BriefDescription": "Offcore prefetch data requests that HITM in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
@@ -2251,6 +2552,7 @@
},
{
"BriefDescription": "Offcore prefetch data reads satisfied by any cache or DRAM.",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -2260,6 +2562,7 @@
},
{
"BriefDescription": "All offcore prefetch data reads",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LOCATION",
"MSRIndex": "0x1A6",
@@ -2269,6 +2572,7 @@
},
{
"BriefDescription": "Offcore prefetch data reads satisfied by the IO, CSR, MMIO unit",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
@@ -2278,6 +2582,7 @@
},
{
"BriefDescription": "Offcore prefetch data reads satisfied by the LLC and not found in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
@@ -2287,6 +2592,7 @@
},
{
"BriefDescription": "Offcore prefetch data reads satisfied by the LLC and HIT in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
@@ -2296,6 +2602,7 @@
},
{
"BriefDescription": "Offcore prefetch data reads satisfied by the LLC and HITM in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
@@ -2305,6 +2612,7 @@
},
{
"BriefDescription": "Offcore prefetch data reads satisfied by the LLC",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE",
"MSRIndex": "0x1A6",
@@ -2314,6 +2622,7 @@
},
{
"BriefDescription": "Offcore prefetch data reads satisfied by the LLC or local DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -2323,6 +2632,7 @@
},
{
"BriefDescription": "Offcore prefetch data reads satisfied by a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE",
"MSRIndex": "0x1A6",
@@ -2332,6 +2642,7 @@
},
{
"BriefDescription": "Offcore prefetch data reads satisfied by a remote cache or remote DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -2341,6 +2652,7 @@
},
{
"BriefDescription": "Offcore prefetch data reads that HIT in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
@@ -2350,6 +2662,7 @@
},
{
"BriefDescription": "Offcore prefetch data reads that HITM in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
@@ -2359,6 +2672,7 @@
},
{
"BriefDescription": "Offcore prefetch code reads satisfied by any cache or DRAM.",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -2368,6 +2682,7 @@
},
{
"BriefDescription": "All offcore prefetch code reads",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LOCATION",
"MSRIndex": "0x1A6",
@@ -2377,6 +2692,7 @@
},
{
"BriefDescription": "Offcore prefetch code reads satisfied by the IO, CSR, MMIO unit",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
@@ -2386,6 +2702,7 @@
},
{
"BriefDescription": "Offcore prefetch code reads satisfied by the LLC and not found in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
@@ -2395,6 +2712,7 @@
},
{
"BriefDescription": "Offcore prefetch code reads satisfied by the LLC and HIT in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
@@ -2404,6 +2722,7 @@
},
{
"BriefDescription": "Offcore prefetch code reads satisfied by the LLC and HITM in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
@@ -2413,6 +2732,7 @@
},
{
"BriefDescription": "Offcore prefetch code reads satisfied by the LLC",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE",
"MSRIndex": "0x1A6",
@@ -2422,6 +2742,7 @@
},
{
"BriefDescription": "Offcore prefetch code reads satisfied by the LLC or local DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -2431,6 +2752,7 @@
},
{
"BriefDescription": "Offcore prefetch code reads satisfied by a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE",
"MSRIndex": "0x1A6",
@@ -2440,6 +2762,7 @@
},
{
"BriefDescription": "Offcore prefetch code reads satisfied by a remote cache or remote DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -2449,6 +2772,7 @@
},
{
"BriefDescription": "Offcore prefetch code reads that HIT in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
@@ -2458,6 +2782,7 @@
},
{
"BriefDescription": "Offcore prefetch code reads that HITM in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
@@ -2467,6 +2792,7 @@
},
{
"BriefDescription": "Offcore prefetch RFO requests satisfied by any cache or DRAM.",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -2476,6 +2802,7 @@
},
{
"BriefDescription": "All offcore prefetch RFO requests",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LOCATION",
"MSRIndex": "0x1A6",
@@ -2485,6 +2812,7 @@
},
{
"BriefDescription": "Offcore prefetch RFO requests satisfied by the IO, CSR, MMIO unit",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_RFO.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
@@ -2494,6 +2822,7 @@
},
{
"BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and not found in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
@@ -2503,6 +2832,7 @@
},
{
"BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and HIT in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
@@ -2512,6 +2842,7 @@
},
{
"BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and HITM in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
@@ -2521,6 +2852,7 @@
},
{
"BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE",
"MSRIndex": "0x1A6",
@@ -2530,6 +2862,7 @@
},
{
"BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC or local DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -2539,6 +2872,7 @@
},
{
"BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE",
"MSRIndex": "0x1A6",
@@ -2548,6 +2882,7 @@
},
{
"BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache or remote DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -2557,6 +2892,7 @@
},
{
"BriefDescription": "Offcore prefetch RFO requests that HIT in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
@@ -2566,6 +2902,7 @@
},
{
"BriefDescription": "Offcore prefetch RFO requests that HITM in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
@@ -2575,6 +2912,7 @@
},
{
"BriefDescription": "Offcore prefetch requests satisfied by any cache or DRAM.",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -2584,6 +2922,7 @@
},
{
"BriefDescription": "All offcore prefetch requests",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LOCATION",
"MSRIndex": "0x1A6",
@@ -2593,6 +2932,7 @@
},
{
"BriefDescription": "Offcore prefetch requests satisfied by the IO, CSR, MMIO unit",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PREFETCH.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
@@ -2602,6 +2942,7 @@
},
{
"BriefDescription": "Offcore prefetch requests satisfied by the LLC and not found in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
@@ -2611,6 +2952,7 @@
},
{
"BriefDescription": "Offcore prefetch requests satisfied by the LLC and HIT in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
@@ -2620,6 +2962,7 @@
},
{
"BriefDescription": "Offcore prefetch requests satisfied by the LLC and HITM in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
@@ -2629,6 +2972,7 @@
},
{
"BriefDescription": "Offcore prefetch requests satisfied by the LLC",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE",
"MSRIndex": "0x1A6",
@@ -2638,6 +2982,7 @@
},
{
"BriefDescription": "Offcore prefetch requests satisfied by the LLC or local DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -2647,6 +2992,7 @@
},
{
"BriefDescription": "Offcore prefetch requests satisfied by a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE",
"MSRIndex": "0x1A6",
@@ -2656,6 +3002,7 @@
},
{
"BriefDescription": "Offcore prefetch requests satisfied by a remote cache or remote DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
@@ -2665,6 +3012,7 @@
},
{
"BriefDescription": "Offcore prefetch requests that HIT in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
@@ -2674,6 +3022,7 @@
},
{
"BriefDescription": "Offcore prefetch requests that HITM in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
@@ -2683,6 +3032,7 @@
},
{
"BriefDescription": "Super Queue lock splits across a cache line",
+ "Counter": "0,1,2,3",
"EventCode": "0xF4",
"EventName": "SQ_MISC.SPLIT_LOCK",
"SampleAfterValue": "2000000",
@@ -2690,6 +3040,7 @@
},
{
"BriefDescription": "Loads delayed with at-Retirement block code",
+ "Counter": "0,1,2,3",
"EventCode": "0x6",
"EventName": "STORE_BLOCKS.AT_RET",
"SampleAfterValue": "200000",
@@ -2697,6 +3048,7 @@
},
{
"BriefDescription": "Cacheable loads delayed with L1D block code",
+ "Counter": "0,1,2,3",
"EventCode": "0x6",
"EventName": "STORE_BLOCKS.L1D_BLOCK",
"SampleAfterValue": "200000",