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3 daysMerge tag 'soc-newsoc-6.17' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull new SoC support from Arnd Bergmann: "These five newly supported chips come with both devicetree descriptions and the changes to wire them up to the build system for easier bisection. The chips in question are: - Marvell PXA1908 was the first 64-bit mobile phone chip from Marvell in the product line that started with the Digital StrongARM SA1100 based PDAs and continued with the Intel PXA2xx that dominated early smartphones. This one only made it only into a few products before the entire product line was cut in 2015. - The QiLai SoC is made by RISC-V core designer Andes Technologies and is in the 'Voyager' reference board in MicroATX form factor. It uses four in-order AX45MP cores, which is the midrange product from Andes. - CIX P1 is one of the few Arm chips designed for small workstations, and this one uses 12 Cortex-A720/A520 cores, making it also one of the only ARMv9.2 machines that one can but at the moment. - Axiado AX3000 is an embedded chip with relative small Cortex-A53 CPU cores described as a "Trusted Control/Compute Unit" that can be used as a BMC in servers. In addition to the usual I/O, this one comes with 10GBit ethernet and and a 4TOPS NPU. - Sophgo SG2000 is an embedded chip that comes with both RISC-V and Arm cores that can run Linux. This was already supported for RISC-V but now it also works on Arm One more chip, the Black Sesame C1200 did not make it in tirm for the merge window" * tag 'soc-newsoc-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (38 commits) arm64: defconfig: Enable rudimentary Sophgo SG2000 support arm64: Add SOPHGO SOC family Kconfig support arm64: dts: sophgo: Add Duo Module 01 Evaluation Board arm64: dts: sophgo: Add Duo Module 01 arm64: dts: sophgo: Add initial SG2000 SoC device tree MAINTAINERS: Add entry for Axiado arm64: defconfig: enable the Axiado family arm64: dts: axiado: Add initial support for AX3000 SoC and eval board arm64: add Axiado SoC family dt-bindings: i3c: cdns: add Axiado AX3000 I3C controller dt-bindings: serial: cdns: add Axiado AX3000 UART controller dt-bindings: gpio: cdns: add Axiado AX3000 GPIO variant dt-bindings: gpio: cdns: convert to YAML dt-bindings: arm: axiado: add AX3000 EVK compatible strings dt-bindings: vendor-prefixes: Add Axiado Corporation MAINTAINERS: Add CIX SoC maintainer entry arm64: dts: cix: Add sky1 base dts initial support dt-bindings: clock: cix: Add CIX sky1 scmi clock id arm64: defconfig: Enable CIX SoC mailbox: add CIX mailbox driver ...
3 daysMerge tag 'soc-dt-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds
Pull SoC devicetree updates from Arnd Bergmann: "There are a few new variants of existing chips: - mt6572 is an older mobile phone chip from mediatek that was extremely popular a decade ago but never got upstreamed until now - exynos2200 is a recent high-end mobile phone chip used in a few Samsung phones like the Galaxy S22 - Renesas R-Car V4M-7 (R8A779H2) is an updated version of R-Car V4M (R8A779H0) and used in automotive applications - Tegra264 is a new chip from NVIDIA, but support is fairly minimal for now, and not much information is public about it There are five more chips in a separate branch, as those are new chip families that I merged along with the necessary infrastructure. New board support is not that exciting, with a total of 33 newly added machines here: - Evaluation platforms for the chips above, plus TI am62d2 and Sophgo sg2042 - Six 32-bit industrial boards based on stm32, imx6 and am33 chips, plus eight 64-bit rockchips rk33xx/rk35xx, am62d2, t527, imx8 and imx95 - Two newly added ASPEED BMC based motherboards, and one that got removed - Phones and Tablets based on 32-bit mt6572, tegra30 and 64-bit msm8976 SoCs - Three Laptops based on Mediatek mt8186 and Qualcomm Snapdragon X1 - A set-top box based on Amlogic meson-gxm Updates for existing machines are spread over all the above families. One notable change here is support for the RP1 I/O chip used in Raspberry Pi 5" * tag 'soc-dt-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (606 commits) riscv: dts: sophgo: fix mdio node name for CV180X riscv: dts: sophgo: sophgo-srd3-10: reserve uart0 device riscv: dts: sophgo: add Sophgo SG2042_EVB_V2.0 board device tree riscv: dts: sophgo: add Sophgo SG2042_EVB_V1.X board device tree dt-bindings: riscv: add Sophgo SG2042_EVB_V1.X/V2.0 bindings riscv: dts: sophgo: add ethernet GMAC device for sg2042 riscv: dts: sophgo: Enable ethernet device for Huashan Pi riscv: dts: sophgo: Add mdio multiplexer device for cv18xx riscv: dts: sophgo: Add ethernet device for cv18xx riscv: dts: sophgo: sg2044: add pmu configuration riscv: dts: sophgo: sg2044: add ziccrse extension riscv: dts: sophgo: add zfh for sg2042 riscv: dts: sophgo: add ziccrse for sg2042 riscv: dts: sophgo: Add xtheadvector to the sg2042 devicetree riscv: dts: sophgo: sg2044: add PCIe device support for SG2044 riscv: dts: sophgo: sg2044: add MSI device support for SG2044 riscv: dts: sophgo: add reset configuration for Sophgo CV1800 series SoC riscv: dts: sophgo: add reset generator for Sophgo CV1800 series SoC dt-bindings: soc: sophgo: Move SoCs/boards from riscv into soc, add SG2000 riscv: dts: sophgo: sg2044: Add missing riscv,cbop-block-size property ...
9 daysMerge tag 'riscv-dt-for-v6.17' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/dt RISC-V Misc Devicetrees for v6.17 StarFive: Sort properties on the MilkV Mars and add the power status LED to all jh7110 boards. AMD: Add 64-bit Microblaze V cpu compatible. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> * tag 'riscv-dt-for-v6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux: dt-bindings: riscv: cpus: Add AMD MicroBlaze V 64bit compatible riscv: dts: starfive: jh7110-common: add status power led node riscv: dts: starfive: jh7110-milkv-mars sort properties Link: https://lore.kernel.org/r/20250723-postage-skylight-597377b5f8e4@spud Signed-off-by: Arnd Bergmann <arnd@arndb.de>
9 daysMerge tag 'riscv-sophgo-dt-for-v6.17' of https://github.com/sophgo/linux ↵Arnd Bergmann
into soc/dt RISC-V Devicetrees for v6.17 Sophgo: For CV18xx serials: There are three major changes. The first is to add the RTCSYS MFD node, which provides rich control registers for soc power management and other rich control functions; the second is to add the reset controller node and add related reset properties for other peripherals; the third is to add ethernet controller related nodes to the soc and enable ethernet device control for HuashanPi. For SG2042: There are three major changes. The first is to add ISA extensions such as xtheadvector/ziccrse/zfh for cpu cores; the second is add ethernet controller support; the third is add two new boards EVB_V1 & EVB_V2 which use SG2042 SoC. For SG2044: There are many changes. The first is to add pmu configuration; the second is to add ISA extensions ziccrse and add missing riscv,cbop-block-size property for cpu cores; the third is to add more peripherals nodes for SoC after clock controller is ready, such as MSI/PCIe/pwm/SPI-NOR etc. This PR also add HWMON MCU device for the sophgo-srd3-10 board and reserve uart0 node for sophgo-srd3-10 board because uart0 is already occupied by the firmware. This PR also moves sophgo.yaml from the riscv directory to soc/sophgo for sharing between riscv and arm. CV18xx SoC contains a RISC-V big core and an ARM64 big core. Moving sophgo.yaml to a shared location will help us add support for ARM cores to the CV18xx chip in the future. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> * tag 'riscv-sophgo-dt-for-v6.17' of https://github.com/sophgo/linux: (32 commits) riscv: dts: sophgo: fix mdio node name for CV180X riscv: dts: sophgo: sophgo-srd3-10: reserve uart0 device riscv: dts: sophgo: add Sophgo SG2042_EVB_V2.0 board device tree riscv: dts: sophgo: add Sophgo SG2042_EVB_V1.X board device tree dt-bindings: riscv: add Sophgo SG2042_EVB_V1.X/V2.0 bindings riscv: dts: sophgo: add ethernet GMAC device for sg2042 riscv: dts: sophgo: Enable ethernet device for Huashan Pi riscv: dts: sophgo: Add mdio multiplexer device for cv18xx riscv: dts: sophgo: Add ethernet device for cv18xx riscv: dts: sophgo: sg2044: add pmu configuration riscv: dts: sophgo: sg2044: add ziccrse extension riscv: dts: sophgo: add zfh for sg2042 riscv: dts: sophgo: add ziccrse for sg2042 riscv: dts: sophgo: Add xtheadvector to the sg2042 devicetree riscv: dts: sophgo: sg2044: add PCIe device support for SG2044 riscv: dts: sophgo: sg2044: add MSI device support for SG2044 riscv: dts: sophgo: add reset configuration for Sophgo CV1800 series SoC riscv: dts: sophgo: add reset generator for Sophgo CV1800 series SoC dt-bindings: soc: sophgo: Move SoCs/boards from riscv into soc, add SG2000 riscv: dts: sophgo: sg2044: Add missing riscv,cbop-block-size property ... Link: https://lore.kernel.org/r/MAUPR01MB1107297124C9DA0CD77DA3DC1FE5FA@MAUPR01MB11072.INDPRD01.PROD.OUTLOOK.COM Signed-off-by: Arnd Bergmann <arnd@arndb.de>
9 daysriscv: dts: sophgo: fix mdio node name for CV180XInochi Amaoto
As the mdio multipledxer is marked as mdio device, the check complains the mdio bus number exceed the maximum. Change the node name to mdio-mux to remove the following warnings: mdio@3009800 (mdio-mux-mmioreg): mdio@80:reg:0:0: 128 is greater than the maximum of 31 Fixes: b7945143bc33 ("riscv: dts: sophgo: Add mdio multiplexer device for cv18xx") Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202507140738.XRjv3G8i-lkp@intel.com/ Closes: https://lore.kernel.org/oe-kbuild-all/202507121830.POx2KDVi-lkp@intel.com/ Reviewed-by: Alexander Sverdlin <alexander.sverdlin@gmail.com> Link: https://lore.kernel.org/r/20250715221349.11034-1-inochiama@gmail.com Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
9 daysriscv: dts: sophgo: sophgo-srd3-10: reserve uart0 deviceInochi Amaoto
As the uart0 is already occupied by the firmware, reserve it to avoid this port is used by mistake. Tested-by: Han Gao <rabenda.cn@gmail.com> Reviewed-by: Chen Wang <wangchen20@iscas.ac.cn> Link: https://lore.kernel.org/r/20250703004024.85221-1-inochiama@gmail.com Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
9 daysriscv: dts: sophgo: add Sophgo SG2042_EVB_V2.0 board device treeHan Gao
Sophgo SG2042_EVB_V2.0 [1] is a prototype development board based on SG2042 Currently supports serial port, sdcard/emmc, pwm, fan speed control. Link: https://github.com/sophgo/sophgo-hardware/tree/master/SG2042/SG2042-x4-EVB [1] Signed-off-by: Han Gao <rabenda.cn@gmail.com> Reviewed-by: Nutty Liu <liujingqi@lanxincomputing.com> Reviewed-by: Chen Wang <unicorn_wang@outlook.com> Link: https://lore.kernel.org/r/c1b6ccdc69af0c1457fc1486a6bc8a1e83671537.1751700954.git.rabenda.cn@gmail.com Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
9 daysriscv: dts: sophgo: add Sophgo SG2042_EVB_V1.X board device treeHan Gao
Sophgo SG2042_EVB_V1.X [1] is a prototype development board based on SG2042 Currently supports serial port, sdcard/emmc, pwm, fan speed control. Link: https://github.com/sophgo/sophgo-hardware/tree/master/SG2042/SG2042-x8-EVB [1] Signed-off-by: Han Gao <rabenda.cn@gmail.com> Reviewed-by: Nutty Liu <liujingqi@lanxincomputing.com> Reviewed-by: Chen Wang <unicorn_wang@outlook.com> Link: https://lore.kernel.org/r/27091134ce1f8a6541a349afc324d6f7402ea606.1751700954.git.rabenda.cn@gmail.com Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
9 daysriscv: dts: sophgo: add ethernet GMAC device for sg2042Inochi Amaoto
Add ethernet GMAC device node for the sg2042. Tested-by: Han Gao <rabenda.cn@gmail.com> Link: https://lore.kernel.org/r/20250708064627.509363-1-inochiama@gmail.com Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
9 daysriscv: dts: sophgo: Enable ethernet device for Huashan PiInochi Amaoto
Enable ethernet controller and mdio multiplexer device on Huashan Pi. Link: https://lore.kernel.org/r/20250703021600.125550-4-inochiama@gmail.com Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
9 daysriscv: dts: sophgo: Add mdio multiplexer device for cv18xxInochi Amaoto
Add DT device node of mdio multiplexer device for cv18xx SoC. Link: https://lore.kernel.org/r/20250703021600.125550-3-inochiama@gmail.com Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
9 daysriscv: dts: sophgo: Add ethernet device for cv18xxInochi Amaoto
Add ethernet controller device node for cv18xx SoC. Link: https://lore.kernel.org/r/20250703021600.125550-2-inochiama@gmail.com Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
9 daysriscv: dts: sophgo: sg2044: add pmu configurationInochi Amaoto
Add PMU configuration for the cpu of sg2044, which is the V2 version of C920. Reviewed-by: Chen Wang <unicorn_wang@outlook.com> Tested-by: Han Gao <rabenda.cn@gmail.com> Link: https://lore.kernel.org/r/20250703003844.84617-1-inochiama@gmail.com Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
9 daysriscv: dts: sophgo: sg2044: add ziccrse extensionHan Gao
sg2044 support ziccrse extension. Signed-off-by: Han Gao <rabenda.cn@gmail.com> Reviewed-by: Chen Wang <unicorn_wang@outlook.com> Reviewed-by: Nutty Liu <liujingqi@lanxincomputing.com> Link: https://lore.kernel.org/r/0889174f2e013e095b94940614f4a0a6e614b09c.1751858054.git.rabenda.cn@gmail.com Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
9 daysriscv: dts: sophgo: add zfh for sg2042Han Gao
sg2042 support Zfh ISA extension [1]. Link: https://occ-oss-prod.oss-cn-hangzhou.aliyuncs.com/resource//1737721869472/%E7%8E%84%E9%93%81C910%E4%B8%8EC920R1S6%E7%94%A8%E6%88%B7%E6%89%8B%E5%86%8C%28xrvm%29_20250124.pdf [1] Signed-off-by: Han Gao <rabenda.cn@gmail.com> Reviewed-by: Inochi Amaoto <inochiama@gmail.com> Reviewed-by: Nutty Liu <liujingqi@lanxincomputing.com> Reviewed-by: Chen Wang <unicorn_wang@outlook.com> Link: https://lore.kernel.org/r/bcaf5684c614959f49a9770bf3cd41096cee5fe6.1751698574.git.rabenda.cn@gmail.com Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
9 daysriscv: dts: sophgo: add ziccrse for sg2042Han Gao
sg2042 support Ziccrse ISA extension [1]. Link: https://lore.kernel.org/all/20241103145153.105097-12-alexghiti@rivosinc.com/ [1] Signed-off-by: Han Gao <rabenda.cn@gmail.com> Reviewed-by: Inochi Amaoto <inochiama@gmail.com> Reviewed-by: Nutty Liu <liujingqi@lanxincomputing.com> Reviewed-by: Chen Wang <unicorn_wang@outlook.com> Link: https://lore.kernel.org/r/859df9a05e1693fec9bd2c7dcf14415bb15230bd.1751698574.git.rabenda.cn@gmail.com Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
9 daysriscv: dts: sophgo: Add xtheadvector to the sg2042 devicetreeHan Gao
The sg2042 SoCs support xtheadvector [1] so it can be included in the devicetree. Also include vlenb for the cpu. And set vlenb=16 [2]. This can be tested by passing the "mitigations=off" kernel parameter. Link: https://lore.kernel.org/linux-riscv/20241113-xtheadvector-v11-4-236c22791ef9@rivosinc.com/ [1] Link: https://lore.kernel.org/linux-riscv/aCO44SAoS2kIP61r@ghost/ [2] Signed-off-by: Han Gao <rabenda.cn@gmail.com> Reviewed-by: Inochi Amaoto <inochiama@gmail.com> Reviewed-by: Nutty Liu <liujingqi@lanxincomputing.com> Reviewed-by: Chen Wang <unicorn_wang@outlook.com> Link: https://lore.kernel.org/r/915bef0530dee6c8bc0ae473837a4bd6786fa4fb.1751698574.git.rabenda.cn@gmail.com Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
9 daysriscv: dts: sophgo: sg2044: add PCIe device support for SG2044Inochi Amaoto
Add PCIe device node for SG2044 and configuration for Sophgo SRD3-10. Link: https://lore.kernel.org/r/20250618015851.272188-3-inochiama@gmail.com Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
9 daysriscv: dts: sophgo: sg2044: add MSI device support for SG2044Inochi Amaoto
Add MSI device tree node for SG2044. Reviewed-by: Chen Wang <unicorn_wang@outlook.com> Link: https://lore.kernel.org/r/20250618015851.272188-2-inochiama@gmail.com Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
9 daysriscv: dts: sophgo: add reset configuration for Sophgo CV1800 series SoCInochi Amaoto
Add known reset configuration for existed device. Reviewed-by: Alexander Sverdlin <alexander.sverdlin@gmail.com> Link: https://lore.kernel.org/r/20250617070144.1149926-5-inochiama@gmail.com Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
9 daysriscv: dts: sophgo: add reset generator for Sophgo CV1800 series SoCInochi Amaoto
Add reset generator node for all CV18XX series SoC. Reviewed-by: Alexander Sverdlin <alexander.sverdlin@gmail.com> Tested-by: Junhui Liu <junhui.liu@pigmoral.tech> Tested-by: Alexander Sverdlin <alexander.sverdlin@gmail.com> Link: https://lore.kernel.org/r/20250617070144.1149926-4-inochiama@gmail.com Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
9 daysriscv: dts: sophgo: sg2044: Add missing riscv,cbop-block-size propertyInochi Amaoto
The kernel complains no "riscv,cbop-block-size" and disables the Zicbop extension. Add the missing property to keep it functional. Fixes: ae5bac370ed4 ("riscv: dts: sophgo: Add initial device tree of Sophgo SRD3-10") Link: https://lore.kernel.org/r/20250613074513.1683624-1-inochiama@gmail.com Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
9 daysriscv: dts: sophgo: add pwm controller for SG2044Longbin Li
Add pwm device node for SG2044. Signed-off-by: Longbin Li <looong.bin@gmail.com> Reviewed-by: Chen Wang <unicorn_wang@outlook.com> Link: https://lore.kernel.org/r/20250608232836.784737-12-inochiama@gmail.com Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
9 daysriscv: dts: sophgo: add SG2044 SPI NOR controller driverLongbin Li
Add SPI NOR device node for SG2044. Signed-off-by: Longbin Li <looong.bin@gmail.com> Link: https://lore.kernel.org/r/20250608232836.784737-11-inochiama@gmail.com Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
9 daysriscv: dts: sophgo: sg2044: Add pinctrl deviceInochi Amaoto
Add pinctrl DT node and configuration for SG2044. Link: https://lore.kernel.org/r/20250608232836.784737-10-inochiama@gmail.com Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
9 daysriscv: dts: sophgo: sg2044: Add ethernet control deviceInochi Amaoto
Add ethernet control node for sg2044. Link: https://lore.kernel.org/r/20250608232836.784737-9-inochiama@gmail.com Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
9 daysriscv: dts: sophgo: sophgo-srd3-10: add HWMON MCU deviceInochi Amaoto
Add MCU devicetree node for Sophgo SRD3-10 board. This is used to provide SUSP function for the board. Link: https://lore.kernel.org/r/20250608232836.784737-8-inochiama@gmail.com Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
9 daysriscv: dts: sophgo: sg2044: Add MMC controller deviceInochi Amaoto
Add emmc controller and sd controller DT node for SG2044. Link: https://lore.kernel.org/r/20250608232836.784737-7-inochiama@gmail.com Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
9 daysriscv: dts: sophgo: sg2044: add DMA controller deviceInochi Amaoto
The DMA controller of SG2044 is a standard Synopsys IP, which is already supported by the kernel. Add DMA controller DT node for SG2044. Link: https://lore.kernel.org/r/20250608232836.784737-6-inochiama@gmail.com Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
9 daysriscv: dts: sophgo: sg2044: Add I2C deviceInochi Amaoto
The I2C controller of SG2044 is a standard Synopsys IP, with one the ref clock is need. Add I2C DT node for SG2044 SoC. Link: https://lore.kernel.org/r/20250608232836.784737-5-inochiama@gmail.com Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
9 daysriscv: dts: sophgo: sg2044: Add GPIO deviceInochi Amaoto
The GPIO controller is a standard Synopsys IP, which is already supported by the kernel. Add GPIO DT node for SG2044 SoC. Link: https://lore.kernel.org/r/20250608232836.784737-4-inochiama@gmail.com Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
9 daysriscv: dts: sophgo: sg2044: Add clock controller deviceInochi Amaoto
Add clock controller and pll clock node for sg2044. Link: https://lore.kernel.org/r/20250608232836.784737-3-inochiama@gmail.com Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
9 daysriscv: dts: sophgo: sg2044: Add system controller deviceInochi Amaoto
The TOP system controller device is necessary for the SG2044 clock controller. Add it to the SoC device tree. Link: https://lore.kernel.org/r/20250608232836.784737-2-inochiama@gmail.com Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
9 daysriscv: dts: sophgo: cv18xx: Add RTCSYS device nodeAlexander Sverdlin
Add the RTCSYS MFD node: in Cvitek CV18xx and its successors RTC Subsystem is quite advanced and provides SoC power management functions as well. The SoC family also contains DW8051 block (Intel 8051 compatible CPU core) and an associated SRAM. The corresponding control registers are mapped into RTCSYS address space as well. Link: https://github.com/sophgo/sophgo-doc/tree/main/SG200X/TRM Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com> Reviewed-by: Inochi Amaoto <inochiama@gmail.com> Link: https://lore.kernel.org/r/20250513203128.620731-1-alexander.sverdlin@gmail.com Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
10 daysMerge tag 'thead-dt-for-v6.17' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/fustini/linux into soc/dt T-HEAD Devicetrees for v6.17 There are several additions for the T-Head TH1520 SoC: - Add PVT node for thermal sensor which works with the existing Moortec MR75203 driver. - Add "gpu-clkgen" reset property to the AON node which allows the power domain driver to detect the capability to power sequence the GPU. All of these patches have been tested in linux-next. Signed-off-by: Drew Fustini <fustini@kernel.org> * tag 'thead-dt-for-v6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/fustini/linux: riscv: dts: thead: Add PVT node riscv: dts: thead: th1520: Add GPU clkgen reset to AON node Link: https://lore.kernel.org/r/aHtnwthmTpfkIBMr@x1 Signed-off-by: Arnd Bergmann <arnd@arndb.de>
11 daysriscv: dts: andes: add Voyager board device treeBen Zong-You Xie
Introduce the device tree support for Voyager development board. Currently only support booting into console with only uart, other features will be added later. Signed-off-by: Ben Zong-You Xie <ben717@andestech.com> Link: https://lore.kernel.org/r/20250711133025.2192404-8-ben717@andestech.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
11 daysriscv: dts: andes: add QiLai SoC device treeBen Zong-You Xie
Introduce the initial device tree support for the Andes QiLai SoC. For further information, you can refer to [1]. [1] https://www.andestech.com/en/products-solutions/andeshape-platforms/qilai-chip/ Signed-off-by: Ben Zong-You Xie <ben717@andestech.com> Link: https://lore.kernel.org/r/20250711133025.2192404-7-ben717@andestech.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-07-16riscv: dts: starfive: jh7110-common: add status power led nodeE Shattow
Add status power led node for StarFive VisionFive2 and variant boards. Signed-off-by: E Shattow <e@freeshell.de> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2025-07-16riscv: dts: starfive: jh7110-milkv-mars sort propertiesE Shattow
Improve style with node property order sort of common properties before vendor prefixes Signed-off-by: E Shattow <e@freeshell.de> Acked-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2025-07-09riscv: dts: spacemit: Move eMMC under storage-bus for K1Vivian Wang
SDHCI devices in Spacemit K1 use storage-bus translations. Move the node emmc under storage-bus to reflect this fact. Signed-off-by: Vivian Wang <wangruikang@iscas.ac.cn> Link: https://lore.kernel.org/r/20250623-k1-dma-buses-rfc-wip-v1-3-c0144082061f@iscas.ac.cn Signed-off-by: Yixun Lan <dlan@gentoo.org>
2025-07-09riscv: dts: spacemit: Move UARTs under dma-bus for K1Vivian Wang
UART devices in Spacemit K1 use dma-bus DMA translations. Move these nodes under dma-bus to reflect this fact. Signed-off-by: Vivian Wang <wangruikang@iscas.ac.cn> Reviewed-by: Guodong Xu <guodong@riscstar.com> Link: https://lore.kernel.org/r/20250623-k1-dma-buses-rfc-wip-v1-2-c0144082061f@iscas.ac.cn Signed-off-by: Yixun Lan <dlan@gentoo.org>
2025-07-09riscv: dts: spacemit: Add DMA translation buses for K1Vivian Wang
The SpacemiT K1 has various static translations of DMA accesses. Add these as simple-bus nodes with dma-ranges. Devices actually using these translations will be added to or moved inside the bus nodes in later patches. The bus names are assigned according to consensus with SpacemiT [1]. Link: https://lore.kernel.org/r/CAH1PCMaC+imcMZCFYtRdmH6ge=dPgnANn_GqVfsGRS=+YhyJCw@mail.gmail.com [1] Signed-off-by: Vivian Wang <wangruikang@iscas.ac.cn> Reviewed-by: Guodong Xu <guodong@riscstar.com> Link: https://lore.kernel.org/r/20250623-k1-dma-buses-rfc-wip-v1-1-c0144082061f@iscas.ac.cn Signed-off-by: Yixun Lan <dlan@gentoo.org>
2025-07-09riscv: dts: spacemit: add pwm14_1 pinctrl settingGuodong Xu
This patch adds the option 1 (hence the name pwm14_1) pinctrl configuration for PWM14 on the SpacemiT K1 SoC. PWM14 option 1 is used for PWM-based backlight control on MIPI displays. This configuration is present on all existing K1 development boards, such as the Banana Pi BPI-F3 and the Milk-V Jupiter. For reference, a more complete list of PWM0-PWM19 pinctrl configurations including all options can be found in [1]. Note: Since the corresponding functionality for other pins is not yet in use or ready for upstreaming, this patch includes only the pwm14_1 setting. [1] https://lore.kernel.org/all/20250411131423.3802611-7-guodong@riscstar.com/ Signed-off-by: Guodong Xu <guodong@riscstar.com> Link: https://lore.kernel.org/r/20250429085048.1310409-5-guodong@riscstar.com Signed-off-by: Yixun Lan <dlan@gentoo.org>
2025-07-09riscv: dts: spacemit: add PWM support for K1 SoCGuodong Xu
The SpacemiT K1 SoC features a PWM controller with 20 independent channels. Add the corresponding 20 PWM nodes to the device tree. Signed-off-by: Guodong Xu <guodong@riscstar.com> Link: https://lore.kernel.org/r/20250429085048.1310409-4-guodong@riscstar.com Signed-off-by: Yixun Lan <dlan@gentoo.org>
2025-07-07riscv: dts: sifive: unleashed/unmatched: Remove PWM controlled LED's ↵Nylon Chen
active-low properties This removes the active-low properties of the PWM-controlled LEDs in the HiFive Unmatched device tree. The reference is hifive-unleashed-a00.pdf[0] and hifive-unmatched-schematics-v3.pdf[1]. Link: https://sifive.cdn.prismic.io/sifive/c52a8e32-05ce-4aaf-95c8-7bf8453f8698_hifive-unleashed-a00-schematics-1.pdf [0] Link: https://sifive.cdn.prismic.io/sifive/6a06d6c0-6e66-49b5-8e9e-e68ce76f4192_hifive-unmatched-schematics-v3.pdf [1] Acked-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Vincent Chen <vincent.chen@sifive.com> Signed-off-by: Nylon Chen <nylon.chen@sifive.com> Link: https://lore.kernel.org/r/20250529035341.51736-2-nylon.chen@sifive.com Signed-off-by: Uwe Kleine-König <ukleinek@kernel.org>
2025-07-04riscv: dts: spacemit: add reset support for the K1 SoCAlex Elder
Define syscon nodes for the RCPU, RCPU2, and APBC2 SpacemiT CCUS, which currently support resets but not clocks in the SpacemiT K1. Signed-off-by: Alex Elder <elder@riscstar.com> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Yixun Lan <dlan@gentoo.org> Link: https://lore.kernel.org/r/20250702113709.291748-7-elder@riscstar.com Signed-off-by: Yixun Lan <dlan@gentoo.org>
2025-06-30riscv: dts: thead: Add PVT nodeMichal Wilczynski
Add PVT DT node for thermal sensor. Reviewed-by: Drew Fustini <drew@pdp7.com> Signed-off-by: Michal Wilczynski <m.wilczynski@samsung.com> Signed-off-by: Drew Fustini <drew@pdp7.com>
2025-06-30riscv: dts: thead: th1520: Add GPU clkgen reset to AON nodeMichal Wilczynski
Add the "gpu-clkgen" reset property to the AON device tree node. This allows the AON power domain driver to detect the capability to power sequence the GPU and spawn the necessary pwrseq-thead-gpu auxiliary driver for managing the GPU's complex power sequence. This commit also adds the prerequisite dt-bindings/reset/thead,th1520-reset.h include to make the TH1520_RESET_ID_GPU_CLKGEN available. This include was previously dropped during a conflict resolution [1]. Link: https://lore.kernel.org/all/aAvfn2mq0Ksi8DF2@x1/ [1] Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Drew Fustini <drew@pdp7.com> Signed-off-by: Michal Wilczynski <m.wilczynski@samsung.com> Signed-off-by: Drew Fustini <drew@pdp7.com>
2025-06-10riscv: dts: spacemit: enable eMMC for K1 SoCYixun Lan
Enable eMMC support for SpacemiT K1 SoC, successfully tested on Bananapi-F3 board which shipped with a 16GB eMMC chip - KLMAG1JETD-B041. Link: https://lore.kernel.org/r/20250523-22-k1-sdhci-v1-1-6e0adddf7494@gentoo.org Signed-off-by: Yixun Lan <dlan@gentoo.org>
2025-05-31Merge tag 'soc-newsoc-6.16' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull sophgo SoC devicetree updates from Arnd Bergmann: "The Sophgo SG2044 SoC is their second generation server chip with 64 cores, following the SG2042. In addition, there are minor updates for the cv180x SoCs" * tag 'soc-newsoc-6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: riscv: dts: sophgo: switch precise compatible for existed clock device for CV18XX riscv: dts: sophgo: Add initial device tree of Sophgo SRD3-10 dt-bindings: riscv: sophgo: Add SG2044 compatible string dt-bindings: interrupt-controller: Add Sophgo SG2044 PLIC dt-bindings: interrupt-controller: Add Sophgo SG2044 CLINT mswi riscv: dts: sopgho: use SOC_PERIPHERAL_IRQ to calculate interrupt number riscv: dts: sophgo: rename header file cv18xx.dtsi to cv180x.dtsi riscv: dts: sophgo: Move riscv cpu definition to a separate file riscv: dts: sophgo: Move all soc specific device into soc dtsi file riscv: sophgo: dts: Add spi controller for SG2042 riscv: dts: sophgo: sg2042: add pinctrl support
generated by cgit (git 2.34.1) at 2025-08-01 09:43:06 +0000