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path: root/drivers/gpu/drm/nouveau/nvkm/engine/sec2/base.c
AgeCommit message (Collapse)Author
2022-11-09drm/nouveau/acr/ga102: initial supportBen Skeggs
v2. fixup for ga103 early merge Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Gourav Samaiya <gsamaiya@nvidia.com>
2022-11-09drm/nouveau/sec2: switch to newer style interrupt handlerBen Skeggs
Ampere. Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
2022-11-09drm/nouveau/sec2: unload RTOS before tearing down WPRBen Skeggs
Reset regs won't be available on Ampere while SEC2 RTOS is running, and we're apparently supposed to be doing this on earlier GPUs too. v2: - fixed some excessive indentation Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
2021-02-11drm/nouveau/sec2: switch to instanced constructorBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
2021-02-11drm/nouveau/subdev: store full subdev name in structBen Skeggs
Much easier to store this to avoid having to reconstruct a string for a specific subdev, taking into account whether it's instanced or not. Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
2020-01-15drm/nouveau/secboot: move code to boot LS falcons to subdevsBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2020-01-15drm/nouveau/flcn/msgq: pass explicit message queue pointer to recv()Ben Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2020-01-15drm/nouveau/flcn/msgq: move handling of init message to subdevsBen Skeggs
When the PMU/SEC2 LS FWs have booted, they'll send a message to the host with various information, including the configuration of message/command queues that are available. Move the handling for this to the relevant subdevs. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2020-01-15drm/nouveau/flcn/msgq: explicitly create message queue from subdevsBen Skeggs
Code to interface with LS firmwares is being moved to the subdevs where it belongs, rather than living in the common falcon code. This is an incremental step towards that goal. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2020-01-15drm/nouveau/flcn/cmdq: explicitly create command queue(s) from subdevsBen Skeggs
Code to interface with LS firmwares is being moved to the subdevs where it belongs, rather than living in the common falcon code. This is an incremental step towards that goal. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2020-01-15drm/nouveau/flcn/qmgr: explicitly create queue manager from subdevsBen Skeggs
Code to interface with LS firmwares is being moved to the subdevs where it belongs, rather than living in the common falcon code. This is an incremental step towards that goal. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2020-01-15drm/nouveau/sec2: move interrupt handler to hw-specific moduleBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2020-01-15drm/nouveau/sec2: use falcon funcsBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2020-01-15drm/nouveau/sec2: initialise SW state for falcon from constructorBen Skeggs
This will allow us to register the falcon with ACR, and further customise its behaviour by providing the nvkm_falcon_func structure directly. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2020-01-15drm/nouveau/sec2: select implementation based on available firmwareBen Skeggs
This will allow for further customisation of the subdev depending on what firmware is available. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-02-20drm/nouveau/sec2: utilise engine PRI address from TOPBen Skeggs
Turing has its SEC2 instance in an alternate location, and this avoids needing to duplicate the code here for it. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-03-17drm/nouveau/secboot: fix NULL pointer dereferenceAlexandre Courbot
The msgqueue pointer validity should be checked by its owner, not by the msgqueue code itself to avoid this situation. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Reported-by: Julia Lawall <julia.lawall@lip6.fr> Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-03-07drm/nouveau/core: add SEC2 engineAlexandre Courbot
SEC2 is the name given by NVIDIA to the SEC engine post-Fermi (reasons unknown). Even though it shares the same address range as SEC, its usage is quite different and this justifies a new engine. Add this engine and make TOP use it all post-TOP devices should use this implementation and not the older SEC. Also quickly add the short gp102 implementation which will be used for falcon booting purposes. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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