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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/amlogic,meson-nand.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Amlogic NAND Flash Controller (NFC) for GXBB/GXL/AXG family SoCs
allOf:
- $ref: nand-controller.yaml
maintainers:
- liang.yang@amlogic.com
properties:
compatible:
enum:
- amlogic,meson-gxl-nfc
- amlogic,meson-axg-nfc
reg:
maxItems: 2
reg-names:
items:
- const: nfc
- const: emmc
interrupts:
maxItems: 1
clocks:
minItems: 2
clock-names:
items:
- const: core
- const: device
patternProperties:
"^nand@[0-7]$":
type: object
$ref: raw-nand-chip.yaml
properties:
reg:
minimum: 0
maximum: 1
nand-ecc-mode:
const: hw
nand-ecc-step-size:
enum: [512, 1024]
nand-ecc-strength:
enum: [8, 16, 24, 30, 40, 50, 60]
description: |
The ECC configurations that can be supported are as follows.
meson-gxl-nfc 8, 16, 24, 30, 40, 50, 60
meson-axg-nfc 8
nand-rb:
maxItems: 1
items:
maximum: 0
amlogic,boot-pages:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Number of pages starting from offset 0, where a special ECC
configuration must be used because it is accessed by the ROM
code. This ECC configuration uses 384 bytes data blocks.
Also scrambling mode is enabled for such pages.
amlogic,boot-page-step:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Interval between pages, accessed by the ROM code. For example
we have 8 pages [0, 7]. Pages 0,2,4,6 are accessed by the
ROM code, so this field will be 2 (e.g. every 2nd page). Rest
of pages - 1,3,5,7 are read/written without this mode.
unevaluatedProperties: false
dependencies:
nand-ecc-strength: [nand-ecc-step-size]
nand-ecc-step-size: [nand-ecc-strength]
amlogic,boot-pages: [nand-is-boot-medium, "amlogic,boot-page-step"]
amlogic,boot-page-step: [nand-is-boot-medium, "amlogic,boot-pages"]
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/axg-clkc.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
nand-controller@ffe07800 {
compatible = "amlogic,meson-axg-nfc";
reg = <0xffe07800 0x100>, <0xffe07000 0x800>;
reg-names = "nfc", "emmc";
interrupts = <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>;
clocks = <&clkc CLKID_SD_EMMC_C>, <&clkc CLKID_FCLK_DIV2>;
clock-names = "core", "device";
pinctrl-0 = <&nand_pins>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
nand@0 {
reg = <0>;
nand-rb = <0>;
};
};
...
|
