1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
|
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (c) 2024 Blaize, Inc. All rights reserved.
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu0: cpu@0 {
compatible = "arm,cortex-a53";
reg = <0x0 0x0>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&l2>;
};
cpu1: cpu@1 {
compatible = "arm,cortex-a53";
reg = <0x0 0x1>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&l2>;
};
l2: l2-cache0 {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};
firmware {
scmi {
compatible = "arm,scmi-smc";
arm,smc-id = <0x82002000>;
#address-cells = <1>;
#size-cells = <0>;
shmem = <&scmi0_shm>;
scmi_clk: protocol@14 {
reg = <0x14>;
#clock-cells = <1>;
};
scmi_rst: protocol@16 {
reg = <0x16>;
#reset-cells = <1>;
};
};
};
pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>, <&cpu1>;
};
psci {
compatible = "arm,psci-1.0", "arm,psci-0.2";
method = "smc";
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
/* SCMI reserved buffer space on DDR space */
scmi0_shm: scmi-shmem@800 {
compatible = "arm,scmi-shmem";
reg = <0x0 0x800 0x0 0x80>;
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = /* Physical Secure PPI */
<GIC_PPI 13 (GIC_CPU_MASK_RAW(0x3) |
IRQ_TYPE_LEVEL_LOW)>,
/* Physical Non-Secure PPI */
<GIC_PPI 14 (GIC_CPU_MASK_RAW(0x3) |
IRQ_TYPE_LEVEL_LOW)>,
/* Hypervisor PPI */
<GIC_PPI 10 (GIC_CPU_MASK_RAW(0x3) |
IRQ_TYPE_LEVEL_LOW)>,
/* Virtual PPI */
<GIC_PPI 11 (GIC_CPU_MASK_RAW(0x3) |
IRQ_TYPE_LEVEL_LOW)>;
};
soc@200000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x2 0x0 0x850000>;
gic: interrupt-controller@410000 {
compatible = "arm,gic-400";
reg = <0x410000 0x20000>,
<0x420000 0x20000>,
<0x440000 0x20000>,
<0x460000 0x20000>;
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0x3) |
IRQ_TYPE_LEVEL_LOW)>;
};
gpio0: gpio@4c0000 {
compatible = "blaize,blzp1600-gpio";
reg = <0x4c0000 0x1000>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <32>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
status = "disabled";
};
uart0: serial@4d0000 {
compatible = "ns16550a";
reg = <0x4d0000 0x1000>;
clocks = <&scmi_clk 59>;
resets = <&scmi_rst 59>;
reg-shift = <2>;
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
uart1: serial@4e0000 {
compatible = "ns16550a";
reg = <0x4e0000 0x1000>;
clocks = <&scmi_clk 60>;
resets = <&scmi_rst 60>;
reg-shift = <2>;
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
i2c0: i2c@4f0000 {
compatible = "snps,designware-i2c";
reg = <0x4f0000 0x1000>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&scmi_clk 54>;
resets = <&scmi_rst 54>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c1: i2c@500000 {
compatible = "snps,designware-i2c";
reg = <0x500000 0x1000>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&scmi_clk 55>;
resets = <&scmi_rst 55>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c2: i2c@510000 {
compatible = "snps,designware-i2c";
reg = <0x510000 0x1000>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&scmi_clk 56>;
resets = <&scmi_rst 56>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c3: i2c@520000 {
compatible = "snps,designware-i2c";
reg = <0x520000 0x1000>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&scmi_clk 57>;
resets = <&scmi_rst 57>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c4: i2c@530000 {
compatible = "snps,designware-i2c";
reg = <0x530000 0x1000>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&scmi_clk 58>;
resets = <&scmi_rst 58>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
arm_cc712: crypto@550000 {
compatible = "arm,cryptocell-712-ree";
reg = <0x550000 0x1000>;
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&scmi_clk 7>;
};
};
};
|
