drivers: Add drivers for Marvell A7K and A8K platforms

Add Marvell drivers for A7K and A8K SoC families

Change-Id: I7fb530e543e4f64782f41f8a058b6aabd82af9e8
Signed-off-by: Haim Boot <hayim@marvell.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/37916

4 files changed, 187 insertions, 0 deletions

diff --git a/docs/marvell/misc/mvebu-amb.txt b/docs/marvell/misc/mvebu-amb.txt
new file mode 100644
index 00000000..40a74674
--- /dev/null
+++ b/docs/marvell/misc/mvebu-amb.txt
@@ -0,0 +1,45 @@
+AMB - AXI MBUS address decoding
+-------------------------------
+
+- The Runit offers a second level of address windows lookup. It is used to map transaction towards
+the CD BootROM, SPI0, SPI1 and Device bus (NOR).
+- The Runit contains eight configurable windows. Each window defines a contiguous,
+address space and the properties associated with that address space.
+
+Unit		Bank		ATTR
+Device-Bus	DEV_BOOT_CS 	0x2F
+		DEV_CS0     	0x3E
+		DEV_CS1     	0x3D
+		DEV_CS2     	0x3B
+		DEV_CS3     	0x37
+SPI-0		SPI_A_CS0 	0x1E
+		SPI_A_CS1 	0x5E
+		SPI_A_CS2 	0x9E
+		SPI_A_CS3 	0xDE
+		SPI_A_CS4 	0x1F
+		SPI_A_CS5 	0x5F
+		SPI_A_CS6 	0x9F
+		SPI_A_CS7 	0xDF
+SPI1		SPI_B_CS0 	0x1A
+		SPI_B_CS1 	0x5A
+		SPI_B_CS2	0x9A
+		SPI_B_CS3	0xDA
+BOOT_ROM	BOOT_ROM	0x1D
+UART		UART		0x01
+
+Mandatory functions:
+	- marvell_get_amb_reg_offs
+		returns the base address of the AXI-MBUS(AMB) unit
+	- marvell_get_amb_memory_map
+		returns the AMB windows configuration and the number of windows
+
+Mandatory structures:
+	amb_memory_map - Array that include the configuration of the windows
+	  every window/entry is a struct which has 2 parameters:
+	  - base address of the window
+	  - Attribute of the window
+
+Examples:
+	struct amb_win amb_memory_map[] = {
+		{0xf900,	AMB_DEV_CS0_ID},
+	};
diff --git a/docs/marvell/misc/mvebu-ccu.txt b/docs/marvell/misc/mvebu-ccu.txt
new file mode 100644
index 00000000..c8b5df5d
--- /dev/null
+++ b/docs/marvell/misc/mvebu-ccu.txt
@@ -0,0 +1,38 @@
+Marvell CCU address decoding bindings
+=====================================
+
+The CCU node includes a description of the address decoding configuration.
+
+Mandatory functions:
+	- marvell_get_ccu_reg_offs
+		returns the base address of the CCU unit
+	- marvell_get_ccu_max_win
+		returns the number of the max mbus windows
+	- marvell_get_ccu_memory_map
+		return the CCU windows configuration and the number of windows
+
+Mandatory structures:
+	ccu_memory_map - Array that includes the configuration of the windows
+	  every window/entry is a struct which has 5 parameters:
+	  - High base address of the window
+	  - Low base address of the window
+	  - High size of the window
+	  - Low size of the window
+	  - Target-ID of the window
+
+Note: if the base address is more than 32 bits, it should be divided into high and low.
+	The same goes for the Size field. If it is larger than 32 bits, it is divided into
+	high and low.
+	Base example:
+		base address: 0x10f0000000 should be divided into:
+		base address high: 0x10
+		base address low: 0xf0000000
+	Size example:
+		size: 0x1E00F00000 should be divided into:
+		size high: 0x1E
+		size low: 0x00F00000
+
+Example:
+	struct ccu_win ccu_memory_map[] = {
+		{0x0,   0xf2000000,     0x0,    0xe000000,      IO_0_TID}, /* IO window */
+	};
diff --git a/docs/marvell/misc/mvebu-iob.txt b/docs/marvell/misc/mvebu-iob.txt
new file mode 100644
index 00000000..5bd81c62
--- /dev/null
+++ b/docs/marvell/misc/mvebu-iob.txt
@@ -0,0 +1,56 @@
+Marvell IOB address decoding bindings
+=====================================
+
+The IOB includes a description of the address decoding configuration.
+
+IOB supports up to n (in CP110 n=24) windows for external memory transaction.
+When a transaction passes through the IOB, its address is compared to each of
+the enabled windows. If there is a hit and it passes the security checks, it is
+advanced to the target port.
+
+Mandatory functions:
+	- marvell_get_iob_reg_offs
+		returns the base address of the IOB unit
+	- marvell_get_iob_max_win
+		returns the number of the max IOB windows
+	- marvell_get_iob_memory_map
+		returns the IOB windows configuration and the number of windows
+
+Mandatory structures:
+	iob_memory_map - Array that include the configuration of the windows
+	  every window/entry is a struct which has 5 parameters:
+	  - High base address of the window
+	  - Low base address of the window
+	  - High size of the window
+	  - Low size of the window
+	  - Target-ID of the window
+
+Target ID options:
+	- 0x0 = Internal configuration space
+	- 0x1 = MCI0
+	- 0x2 = PEX1_X1
+	- 0x3 = PEX2_X1
+	- 0x4 = PEX0_X4
+	- 0x5 = NAND flash
+	- 0x6 = RUNIT (NOR/SPI/BootRoom)
+	- 0x7 = MCI1
+
+Note: if the base address is more than 32 bits, it divided into high and low.
+	The same goes for the Size field, if it more that 32 bits, it divided into
+	high and low.
+	Base example:
+		base address: 0x10f0000000 should divided into:
+		base address high: 0x10
+		base address low: 0xf0000000
+	Size example:
+		size: 0x1E00F00000 should divided into:
+		size high: 0x1E
+		size low: 0x00F00000
+
+Example:
+	struct iob_win iob_memory_map[] = {
+		{0x0,	0xf7000000,	0x0,	0x1000000,	PEX1_TID}, /* PEX1_X1 window */
+		{0x0,	0xf8000000,	0x0,	0x1000000,	PEX2_TID}, /* PEX2_X1 window */
+		{0x0,	0xf6000000,	0x0,	0x1000000,	PEX0_TID}, /* PEX0_X4 window */
+		{0x0,	0xf9000000,	0x0,	0x1000000,	NAND_TID}  /* NAND window */
+	};
diff --git a/docs/marvell/misc/mvebu-rfu.txt b/docs/marvell/misc/mvebu-rfu.txt
new file mode 100644
index 00000000..e525c960
--- /dev/null
+++ b/docs/marvell/misc/mvebu-rfu.txt
@@ -0,0 +1,48 @@
+Marvell RFU address decoding bindings
+=====================================
+
+The RFU includes a description of the address decoding configuration.
+
+Transactions that are decoded by CCU windows as IO peripheral, have an additional
+layer of decoding. This additional address decoding layer defines one of the
+following targets:
+	0x0 = BootRom
+	0x1 = STM (Serial Trace Macro-cell, a programmer's port into trace stream)
+	0x2 = SPI direct access
+	0x3 = PCIe registers
+	0x4 = MCI Port
+	0x5 = PCIe port
+
+Mandatory functions:
+	- marvell_get_rfu_reg_offs
+		returns the base address of the RFU unit
+	- marvell_get_rfu_memory_map
+		returns the RFU windows configuration and the number of windows
+
+Mandatory structures:
+	rfu_memory_map - Array that include the configuration of the windows
+	  every window/entry is a struct which has 5 parameters:
+	  - High base address of the window
+	  - Low base address of the window
+	  - High size of the window
+	  - Low size of the window
+	  - Target-ID of the window
+
+Note: if the base address is more than 32 bits, it divided into high and low.
+	The same goes for the Size field, if it more that 32 bits, is divided into
+	high and low.
+	Base example:
+		base address: 0x10f0000000 should divided into:
+		base address high: 0x10
+		base address low: 0xf0000000
+	Size example:
+		size: 0x1E00F00000 should divided into:
+		size high: 0x1E
+		size low: 0x00F00000
+
+Example:
+	struct rfu_win rfu_memory_map[] = {
+		{0x0,	0xfe000000,	0x0,	0x1f00000,	PCIE_PORT_TID}, /* PCIe window 31Mb for PCIe port*/
+		{0x0,	0xffe00000,	0x0,	0x100000,	PCIE_REGS_TID}, /* PCI-REG window 64Kb for PCIe-reg*/
+		{0x0,	0xf6000000,	0x0,	0x100000,	MCIPHY_TID},	/* MCI window  1Mb for PHY-reg*/
+	};